Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9384848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17057647

1

T19

14

T107

12

T108

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8165307	1			T19	19		T107	11		T108	20
values[0x0]	6952828	1			T19	7		T107	5		T108	11
values[0x1]	11324360	1			T19	12		T107	6		T108	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4877370	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21565125

1

T19

16

T107

13

T108

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	108630	1			T110	6		T191	1		T222	17
valid_sources[0x01]	97511	1			T110	5		T191	1		T190	1
valid_sources[0x02]	96933	1			T110	4		T111	20		T223	19
valid_sources[0x03]	107966	1			T19	1		T110	3		T191	5
valid_sources[0x04]	96297	1			T109	7		T110	3		T191	1
valid_sources[0x05]	96357	1			T110	3		T191	1		T222	4
valid_sources[0x06]	98092	1			T110	3		T191	1		T222	5
valid_sources[0x07]	101913	1			T110	4		T191	1		T219	1
valid_sources[0x08]	99997	1			T110	3		T190	1		T222	5
valid_sources[0x09]	100112	1			T110	4		T191	1		T222	7
valid_sources[0x0a]	97954	1			T107	1		T110	2		T191	3
valid_sources[0x0b]	97340	1			T187	3		T110	5		T191	3
valid_sources[0x0c]	100692	1			T110	3		T222	9		T234	5
valid_sources[0x0d]	100988	1			T110	5		T191	3		T222	6
valid_sources[0x0e]	100440	1			T107	1		T110	4		T222	11
valid_sources[0x0f]	100906	1			T110	2		T191	2		T230	6
valid_sources[0x10]	103599	1			T110	1		T191	4		T222	9
valid_sources[0x11]	104442	1			T19	3		T187	2		T110	1
valid_sources[0x12]	99662	1			T110	3		T111	1		T191	1
valid_sources[0x13]	106617	1			T110	2		T191	3		T219	2
valid_sources[0x14]	108858	1			T110	2		T191	1		T222	9
valid_sources[0x15]	100995	1			T110	7		T222	10		T195	2
valid_sources[0x16]	104809	1			T110	2		T222	13		T194	3
valid_sources[0x17]	103440	1			T110	4		T191	2		T230	2
valid_sources[0x18]	103751	1			T187	4		T110	8		T111	41
valid_sources[0x19]	97227	1			T110	2		T191	4		T222	16
valid_sources[0x1a]	99487	1			T187	3		T110	2		T222	13
valid_sources[0x1b]	100293	1			T110	6		T190	1		T222	9
valid_sources[0x1c]	103309	1			T19	3		T110	1		T191	2
valid_sources[0x1d]	99549	1			T110	2		T191	1		T222	6
valid_sources[0x1e]	105185	1			T110	2		T191	1		T190	1
valid_sources[0x1f]	97640	1			T186	38		T110	4		T191	1
valid_sources[0x20]	104949	1			T110	4		T191	1		T230	13
valid_sources[0x21]	105198	1			T110	2		T111	4		T222	13
valid_sources[0x22]	102691	1			T110	1		T230	4		T222	10
valid_sources[0x23]	98652	1			T110	3		T222	10		T192	1
valid_sources[0x24]	99662	1			T110	4		T222	6		T224	24
valid_sources[0x25]	103552	1			T110	7		T200	1		T222	10
valid_sources[0x26]	100267	1			T110	4		T191	5		T222	9
valid_sources[0x27]	98160	1			T187	1		T222	12		T195	2
valid_sources[0x28]	102273	1			T110	1		T191	3		T190	1
valid_sources[0x29]	110935	1			T107	1		T191	7		T219	1
valid_sources[0x2a]	102368	1			T110	3		T219	2		T222	5
valid_sources[0x2b]	101968	1			T110	1		T191	4		T222	8
valid_sources[0x2c]	97180	1			T110	4		T191	5		T190	1
valid_sources[0x2d]	105678	1			T191	1		T190	1		T222	6
valid_sources[0x2e]	107942	1			T110	4		T190	1		T222	6
valid_sources[0x2f]	99879	1			T110	3		T191	2		T219	2
valid_sources[0x30]	111665	1			T110	4		T191	3		T190	1
valid_sources[0x31]	99126	1			T187	1		T110	3		T191	2
valid_sources[0x32]	99375	1			T187	2		T110	1		T190	1
valid_sources[0x33]	112511	1			T110	3		T191	1		T222	11
valid_sources[0x34]	103514	1			T110	3		T111	21		T200	1
valid_sources[0x35]	97971	1			T110	4		T191	2		T230	15
valid_sources[0x36]	100006	1			T110	2		T191	2		T200	2
valid_sources[0x37]	101728	1			T110	3		T111	3		T191	2
valid_sources[0x38]	98710	1			T191	1		T219	2		T222	7
valid_sources[0x39]	99773	1			T187	5		T110	8		T191	3
valid_sources[0x3a]	100243	1			T110	5		T191	1		T230	7
valid_sources[0x3b]	98939	1			T110	2		T111	74		T191	3
valid_sources[0x3c]	97962	1			T110	2		T111	3		T191	6
valid_sources[0x3d]	97934	1			T110	4		T190	2		T222	12
valid_sources[0x3e]	99118	1			T110	4		T191	1		T190	1
valid_sources[0x3f]	102778	1			T110	4		T222	5		T192	1
valid_sources[0x40]	102577	1			T110	3		T191	2		T190	1
valid_sources[0x41]	99879	1			T19	5		T110	5		T191	1
valid_sources[0x42]	101758	1			T110	4		T191	1		T222	6
valid_sources[0x43]	97013	1			T110	4		T191	1		T190	1
valid_sources[0x44]	104348	1			T110	4		T191	2		T190	2
valid_sources[0x45]	99430	1			T110	5		T191	2		T222	6
valid_sources[0x46]	99367	1			T110	2		T222	8		T192	2
valid_sources[0x47]	104743	1			T110	3		T191	6		T230	21
valid_sources[0x48]	99890	1			T110	3		T191	1		T200	1
valid_sources[0x49]	102083	1			T110	6		T230	15		T222	13
valid_sources[0x4a]	98807	1			T191	2		T230	25		T222	10
valid_sources[0x4b]	103048	1			T110	4		T191	2		T222	5
valid_sources[0x4c]	97743	1			T110	7		T191	3		T200	1
valid_sources[0x4d]	100314	1			T191	1		T222	8		T193	3
valid_sources[0x4e]	98985	1			T110	1		T191	4		T222	8
valid_sources[0x4f]	103416	1			T110	3		T191	1		T222	13
valid_sources[0x50]	99009	1			T107	2		T110	1		T191	2
valid_sources[0x51]	100869	1			T109	8		T110	2		T191	1
valid_sources[0x52]	105763	1			T110	6		T191	1		T222	13
valid_sources[0x53]	97555	1			T110	8		T230	37		T222	10
valid_sources[0x54]	97522	1			T110	4		T191	2		T190	1
valid_sources[0x55]	100051	1			T109	152		T110	4		T191	1
valid_sources[0x56]	99750	1			T110	1		T191	2		T222	8
valid_sources[0x57]	106266	1			T110	1		T111	98		T222	10
valid_sources[0x58]	101155	1			T187	2		T110	3		T231	15
valid_sources[0x59]	104162	1			T110	1		T230	3		T222	8
valid_sources[0x5a]	100320	1			T110	5		T230	20		T222	13
valid_sources[0x5b]	109579	1			T110	2		T191	1		T190	1
valid_sources[0x5c]	102731	1			T110	6		T191	1		T222	8
valid_sources[0x5d]	100695	1			T110	2		T191	2		T222	11
valid_sources[0x5e]	105880	1			T110	8		T111	2		T222	4
valid_sources[0x5f]	102309	1			T110	3		T191	3		T219	6
valid_sources[0x60]	98189	1			T107	1		T110	8		T111	1
valid_sources[0x61]	104168	1			T110	2		T191	3		T222	8
valid_sources[0x62]	101431	1			T110	4		T191	1		T222	7
valid_sources[0x63]	100798	1			T110	3		T191	4		T222	5
valid_sources[0x64]	100427	1			T110	2		T111	29		T191	2
valid_sources[0x65]	100375	1			T110	3		T222	7		T235	4
valid_sources[0x66]	105685	1			T110	2		T191	4		T222	4
valid_sources[0x67]	99456	1			T110	6		T190	1		T219	1
valid_sources[0x68]	103404	1			T110	5		T190	1		T230	18
valid_sources[0x69]	103438	1			T110	2		T111	6		T191	1
valid_sources[0x6a]	181971	1			T19	2		T110	3		T191	1
valid_sources[0x6b]	102595	1			T110	7		T191	1		T200	1
valid_sources[0x6c]	100138	1			T110	2		T190	1		T222	11
valid_sources[0x6d]	96351	1			T110	1		T191	4		T222	3
valid_sources[0x6e]	106959	1			T188	22		T110	4		T191	3
valid_sources[0x6f]	100939	1			T110	7		T230	8		T222	4
valid_sources[0x70]	105235	1			T191	2		T222	9		T192	1
valid_sources[0x71]	97803	1			T110	2		T191	1		T222	13
valid_sources[0x72]	96958	1			T110	4		T222	10		T192	1
valid_sources[0x73]	103678	1			T110	1		T111	21		T191	2
valid_sources[0x74]	106513	1			T110	3		T191	1		T219	5
valid_sources[0x75]	102384	1			T19	1		T110	6		T191	1
valid_sources[0x76]	97118	1			T187	3		T110	6		T111	22
valid_sources[0x77]	99455	1			T107	1		T110	4		T191	1
valid_sources[0x78]	96874	1			T110	4		T200	1		T222	14
valid_sources[0x79]	97307	1			T110	5		T222	10		T194	3
valid_sources[0x7a]	103707	1			T110	4		T191	1		T219	3
valid_sources[0x7b]	102105	1			T110	4		T191	2		T200	1
valid_sources[0x7c]	96884	1			T110	2		T191	1		T230	12
valid_sources[0x7d]	99067	1			T110	2		T191	5		T222	6
valid_sources[0x7e]	98652	1			T187	5		T110	2		T191	3
valid_sources[0x7f]	97489	1			T110	1		T191	2		T230	6
valid_sources[0x80]	104778	1			T110	2		T191	1		T190	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4667244

1

T19

9

T107

8

T108

8

values[0x0]

all_enables

biggest_size

6234248

1

T19

3

T107

3

T108

4

values[0x1]

all_enables

biggest_size

6156155

1

T19

2

T107

1

T108

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	868477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31899447

1

T109

78

T110

151

T111

84

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8028523	1			T109	71		T110	459		T111	226
values[0x0]	12002420	1			T109	32		T110	70		T111	41
values[0x1]	12736981	1			T109	33		T110	90		T111	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	298922	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

32469002

1

T109

105

T110

315

T111

164

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	124022	1			T109	1		T110	8		T222	15
valid_sources[0x01]	128216	1			T109	1		T230	3		T222	6
valid_sources[0x02]	125661	1			T109	2		T110	3		T222	6
valid_sources[0x03]	130086	1			T109	1		T110	2		T222	6
valid_sources[0x04]	126772	1			T109	1		T110	1		T111	16
valid_sources[0x05]	128815	1			T109	1		T110	2		T230	8
valid_sources[0x06]	127744	1			T110	2		T222	12		T192	2
valid_sources[0x07]	128565	1			T109	2		T110	2		T230	2
valid_sources[0x08]	126880	1			T110	1		T230	16		T222	5
valid_sources[0x09]	129384	1			T109	1		T110	2		T223	2
valid_sources[0x0a]	122662	1			T110	1		T111	75		T222	8
valid_sources[0x0b]	126458	1			T109	1		T110	1		T222	6
valid_sources[0x0c]	130024	1			T110	3		T230	3		T222	19
valid_sources[0x0d]	124242	1			T110	4		T219	14		T222	2
valid_sources[0x0e]	121442	1			T109	2		T110	3		T222	2
valid_sources[0x0f]	131347	1			T110	3		T219	9		T222	3
valid_sources[0x10]	125985	1			T109	1		T110	3		T191	74
valid_sources[0x11]	127224	1			T110	1		T111	15		T230	16
valid_sources[0x12]	124201	1			T110	1		T222	8		T193	1
valid_sources[0x13]	131878	1			T109	3		T110	1		T223	1
valid_sources[0x14]	126920	1			T110	3		T222	10		T194	1
valid_sources[0x15]	133414	1			T110	2		T230	4		T222	6
valid_sources[0x16]	128522	1			T110	4		T230	9		T222	5
valid_sources[0x17]	125305	1			T109	1		T191	20		T222	12
valid_sources[0x18]	131261	1			T110	2		T222	9		T235	2
valid_sources[0x19]	125872	1			T110	1		T222	9		T193	1
valid_sources[0x1a]	120873	1			T109	1		T110	2		T222	2
valid_sources[0x1b]	133486	1			T110	1		T222	7		T194	2
valid_sources[0x1c]	127579	1			T109	1		T110	1		T222	3
valid_sources[0x1d]	130549	1			T109	1		T110	1		T222	7
valid_sources[0x1e]	125192	1			T110	2		T111	14		T191	9
valid_sources[0x1f]	128268	1			T109	1		T110	2		T222	7
valid_sources[0x20]	133030	1			T110	2		T222	3		T193	1
valid_sources[0x21]	119713	1			T109	1		T110	1		T230	9
valid_sources[0x22]	128983	1			T110	3		T230	20		T222	13
valid_sources[0x23]	131061	1			T109	1		T110	1		T191	51
valid_sources[0x24]	126433	1			T110	2		T222	4		T192	1
valid_sources[0x25]	136760	1			T110	1		T222	5		T193	1
valid_sources[0x26]	133862	1			T110	2		T222	1		T196	5
valid_sources[0x27]	132471	1			T109	2		T110	2		T222	4
valid_sources[0x28]	123086	1			T110	1		T222	4		T192	1
valid_sources[0x29]	128638	1			T109	1		T231	2		T222	3
valid_sources[0x2a]	125894	1			T110	1		T222	15		T193	1
valid_sources[0x2b]	129460	1			T110	1		T230	20		T222	2
valid_sources[0x2c]	129154	1			T110	2		T230	9		T222	3
valid_sources[0x2d]	121744	1			T109	2		T110	3		T193	1
valid_sources[0x2e]	127212	1			T110	1		T223	1		T222	16
valid_sources[0x2f]	136447	1			T110	2		T230	8		T222	3
valid_sources[0x30]	124925	1			T110	6		T222	20		T192	1
valid_sources[0x31]	125890	1			T109	1		T110	3		T222	3
valid_sources[0x32]	129882	1			T109	2		T110	2		T222	3
valid_sources[0x33]	127390	1			T110	2		T222	9		T194	2
valid_sources[0x34]	130028	1			T110	2		T222	12		T194	1
valid_sources[0x35]	131860	1			T110	2		T230	6		T222	9
valid_sources[0x36]	124905	1			T109	1		T110	1		T222	12
valid_sources[0x37]	123843	1			T110	3		T230	2		T222	5
valid_sources[0x38]	131723	1			T110	1		T222	14		T193	1
valid_sources[0x39]	129845	1			T109	1		T110	1		T230	1
valid_sources[0x3a]	126391	1			T110	4		T222	9		T193	1
valid_sources[0x3b]	123844	1			T110	2		T222	6		T193	1
valid_sources[0x3c]	137553	1			T110	3		T222	2		T192	2
valid_sources[0x3d]	125661	1			T109	1		T110	1		T230	6
valid_sources[0x3e]	130224	1			T109	1		T110	2		T222	5
valid_sources[0x3f]	126969	1			T110	3		T222	13		T192	1
valid_sources[0x40]	124766	1			T110	5		T222	3		T193	1
valid_sources[0x41]	125199	1			T110	4		T231	1		T222	4
valid_sources[0x42]	128896	1			T110	5		T222	13		T194	4
valid_sources[0x43]	128275	1			T110	1		T230	13		T222	6
valid_sources[0x44]	121898	1			T110	6		T222	3		T192	1
valid_sources[0x45]	126001	1			T109	1		T110	3		T230	19
valid_sources[0x46]	128599	1			T110	1		T222	19		T235	2
valid_sources[0x47]	124629	1			T109	1		T110	3		T222	4
valid_sources[0x48]	131158	1			T110	2		T222	2		T193	3
valid_sources[0x49]	125334	1			T110	5		T230	9		T223	1
valid_sources[0x4a]	131608	1			T110	2		T230	5		T222	5
valid_sources[0x4b]	131389	1			T109	1		T110	2		T222	3
valid_sources[0x4c]	125154	1			T109	1		T110	2		T223	1
valid_sources[0x4d]	129148	1			T109	2		T110	2		T230	10
valid_sources[0x4e]	129768	1			T110	3		T190	31		T222	6
valid_sources[0x4f]	128099	1			T110	1		T222	5		T194	1
valid_sources[0x50]	123735	1			T110	3		T222	9		T194	2
valid_sources[0x51]	129366	1			T110	5		T222	7		T194	1
valid_sources[0x52]	133490	1			T109	1		T110	1		T222	26
valid_sources[0x53]	128367	1			T110	5		T222	10		T224	2
valid_sources[0x54]	139233	1			T109	2		T223	1		T231	1
valid_sources[0x55]	138314	1			T110	2		T230	2		T222	2
valid_sources[0x56]	128882	1			T110	4		T222	9		T193	1
valid_sources[0x57]	132103	1			T191	13		T222	6		T192	1
valid_sources[0x58]	130090	1			T109	1		T110	3		T111	18
valid_sources[0x59]	130665	1			T110	4		T230	8		T222	5
valid_sources[0x5a]	127167	1			T109	3		T110	2		T230	7
valid_sources[0x5b]	132991	1			T110	1		T222	6		T193	1
valid_sources[0x5c]	126468	1			T109	1		T110	2		T230	1
valid_sources[0x5d]	123145	1			T110	1		T230	5		T222	13
valid_sources[0x5e]	127814	1			T110	4		T230	2		T222	4
valid_sources[0x5f]	125695	1			T110	2		T230	1		T222	27
valid_sources[0x60]	127142	1			T109	2		T110	1		T231	1
valid_sources[0x61]	133503	1			T109	1		T110	3		T222	9
valid_sources[0x62]	122749	1			T109	1		T110	5		T222	6
valid_sources[0x63]	128559	1			T109	1		T110	3		T230	12
valid_sources[0x64]	127435	1			T109	1		T110	2		T230	1
valid_sources[0x65]	128356	1			T110	3		T222	4		T194	2
valid_sources[0x66]	124886	1			T110	1		T230	10		T223	1
valid_sources[0x67]	125463	1			T110	3		T222	13		T197	5
valid_sources[0x68]	129567	1			T109	1		T110	1		T219	4
valid_sources[0x69]	129028	1			T110	2		T191	1		T223	2
valid_sources[0x6a]	123681	1			T110	2		T230	19		T222	4
valid_sources[0x6b]	131658	1			T110	3		T219	5		T230	8
valid_sources[0x6c]	130092	1			T110	5		T191	18		T222	5
valid_sources[0x6d]	132422	1			T109	1		T110	4		T222	19
valid_sources[0x6e]	131379	1			T110	2		T230	4		T222	12
valid_sources[0x6f]	133483	1			T109	1		T110	2		T230	4
valid_sources[0x70]	128520	1			T109	1		T110	2		T230	9
valid_sources[0x71]	127125	1			T109	1		T110	3		T222	8
valid_sources[0x72]	126465	1			T109	1		T110	1		T230	6
valid_sources[0x73]	124762	1			T110	1		T222	5		T192	2
valid_sources[0x74]	124734	1			T109	1		T110	2		T231	1
valid_sources[0x75]	132070	1			T109	1		T110	1		T111	71
valid_sources[0x76]	124879	1			T110	3		T230	2		T222	5
valid_sources[0x77]	125132	1			T110	3		T111	46		T230	9
valid_sources[0x78]	122702	1			T109	1		T110	2		T191	17
valid_sources[0x79]	130990	1			T109	1		T110	3		T222	1
valid_sources[0x7a]	123196	1			T222	5		T192	1		T194	1
valid_sources[0x7b]	125736	1			T109	1		T110	4		T190	41
valid_sources[0x7c]	124227	1			T109	1		T110	2		T191	48
valid_sources[0x7d]	127272	1			T109	1		T110	3		T222	8
valid_sources[0x7e]	131678	1			T109	1		T110	3		T231	1
valid_sources[0x7f]	127850	1			T110	1		T222	7		T234	1
valid_sources[0x80]	130548	1			T110	4		T222	13		T224	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8015840

1

T109

26

T110

39

T111

25

values[0x0]

all_enables

biggest_size

11941830

1

T109

29

T110

54

T111

28

values[0x1]

all_enables

biggest_size

11941777

1

T109

23

T110

58

T111

31