Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

70894344

1

T19

24

T107

10

T108

27

full_word

21062744

1

T19

14

T107

12

T108

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	91956818	1			T19	38		T107	22		T108	40
auto[TlIntgErrCmd]	86	1			T110	9		T111	6		T191	1
auto[TlIntgErrData]	85	1			T110	7		T111	1		T191	4
auto[TlIntgErrBoth]	99	1			T110	4		T111	3		T191	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12972326

1

T19

19

T107

11

T108

20

auto[1]

78984762

1

T19

19

T107

11

T108

20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7818023	1			T19	10		T107	3		T108	12
auto[TlIntgErrNone]	partial	auto[1]	63076071	1			T19	14		T107	7		T108	15
auto[TlIntgErrNone]	full_word	auto[0]	5154181	1			T19	9		T107	8		T108	8
auto[TlIntgErrNone]	full_word	auto[1]	15908543	1			T19	5		T107	4		T108	5
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T110	3		T111	5		T191	1
auto[TlIntgErrCmd]	partial	auto[1]	37	1			T110	5		T111	1		T232	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T313	1		T314	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T110	1		T230	1		T245	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T110	2		T191	3		T230	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T110	4		T111	1		T191	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T110	1		T245	1		T239	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T110	1		T111	1		T191	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T110	3		T111	2		T191	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T191	1		T315	1		T316	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T315	1		T317	1		-	-