Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.80		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	22667850	0	0
check_regwen_rd_A	2147483647	3556	0	0
check_timeout_rd_A	2147483647	2813	0	0
check_trigger_regwen_rd_A	2147483647	3772	0	0
consistency_check_period_rd_A	2147483647	3784	0	0
creator_sw_cfg_read_lock_rd_A	2147483647	2805	0	0
direct_access_address_rd_A	2147483647	2174	0	0
direct_access_wdata_0_rd_A	2147483647	1851	0	0
direct_access_wdata_1_rd_A	2147483647	1887	0	0
integrity_check_period_rd_A	2147483647	3517	0	0
intr_enable_rd_A	2147483647	4325	0	0
owner_sw_cfg_read_lock_rd_A	2147483647	2478	0	0
vendor_test_read_lock_rd_A	2147483647	2767	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22667850	0	0
T109	10001	85	0	0
T110	112102	3	0	0
T111	60168	3	0	0
T186	3770	0	0	0
T187	3434	0	0	0
T188	3328	0	0	0
T189	3625	0	0	0
T190	6864	10	0	0
T191	60680	1	0	0
T192	0	33	0	0
T193	0	129	0	0
T194	0	314	0	0
T195	0	274	0	0
T200	3576	0	0	0
T230	0	4	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3556	0	0
T111	60168	26	0	0
T189	3625	0	0	0
T190	6864	3	0	0
T191	60680	0	0	0
T192	0	8	0	0
T199	0	6	0	0
T200	3576	0	0	0
T219	3734	4	0	0
T223	3116	0	0	0
T224	0	86	0	0
T230	120402	57	0	0
T231	3549	0	0	0
T233	3310	0	0	0
T240	0	154	0	0
T241	0	111	0	0
T248	0	6	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2813	0	0
T192	7494	1	0	0
T195	13861	0	0	0
T196	17394	0	0	0
T199	0	17	0	0
T220	7483	0	0	0
T224	12006	38	0	0
T234	4011	0	0	0
T235	10487	0	0	0
T236	0	9	0	0
T240	0	123	0	0
T241	0	102	0	0
T248	0	3	0	0
T272	3351	0	0	0
T273	4224	0	0	0
T274	3078	0	0	0
T279	0	7	0	0
T280	0	2	0	0
T281	0	19	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3772	0	0
T111	60168	37	0	0
T189	3625	0	0	0
T190	6864	1	0	0
T191	60680	0	0	0
T192	0	5	0	0
T199	0	3	0	0
T200	3576	0	0	0
T219	3734	3	0	0
T223	3116	0	0	0
T224	0	41	0	0
T230	120402	76	0	0
T231	3549	0	0	0
T233	3310	0	0	0
T236	0	5	0	0
T237	0	5	0	0
T240	0	141	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3784	0	0
T111	60168	21	0	0
T189	3625	0	0	0
T190	6864	2	0	0
T191	60680	0	0	0
T192	0	16	0	0
T196	0	1	0	0
T199	0	15	0	0
T200	3576	0	0	0
T219	3734	0	0	0
T223	3116	0	0	0
T224	0	31	0	0
T230	120402	69	0	0
T231	3549	0	0	0
T233	3310	0	0	0
T236	0	19	0	0
T237	0	9	0	0
T240	0	157	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2805	0	0
T190	6864	3	0	0
T192	7494	0	0	0
T199	0	7	0	0
T219	3734	0	0	0
T220	7483	0	0	0
T222	37991	0	0	0
T223	3116	0	0	0
T224	12006	26	0	0
T230	120402	0	0	0
T231	3549	0	0	0
T233	3310	0	0	0
T236	0	4	0	0
T237	0	6	0	0
T240	0	130	0	0
T241	0	123	0	0
T248	0	1	0	0
T279	0	1	0	0
T280	0	4	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2174	0	0
T12	0	43	0	0
T17	0	154	0	0
T121	0	192	0	0
T190	6864	3	0	0
T192	7494	7	0	0
T199	9055	12	0	0
T203	0	30	0	0
T219	3734	0	0	0
T222	37991	0	0	0
T223	3116	0	0	0
T230	120402	0	0	0
T231	3549	0	0	0
T233	3310	0	0	0
T248	6399	1	0	0
T279	0	6	0	0
T280	0	4	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1851	0	0
T12	226861	28	0	0
T17	208952	164	0	0
T63	15793	0	0	0
T64	13413	0	0	0
T65	10066	0	0	0
T82	13853	0	0	0
T89	47638	0	0	0
T121	513904	141	0	0
T167	13303	0	0	0
T203	0	59	0	0
T204	19969	0	0	0
T282	0	51	0	0
T283	0	136	0	0
T284	0	71	0	0
T285	0	141	0	0
T286	0	11	0	0
T287	0	94	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1887	0	0
T12	226861	28	0	0
T17	208952	207	0	0
T63	15793	0	0	0
T64	13413	0	0	0
T65	10066	0	0	0
T82	13853	0	0	0
T89	47638	0	0	0
T121	513904	94	0	0
T167	13303	0	0	0
T203	0	3	0	0
T204	19969	0	0	0
T282	0	58	0	0
T283	0	89	0	0
T284	0	71	0	0
T285	0	123	0	0
T286	0	30	0	0
T287	0	183	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3517	0	0
T111	60168	33	0	0
T189	3625	0	0	0
T190	6864	1	0	0
T191	60680	0	0	0
T192	0	13	0	0
T199	0	11	0	0
T200	3576	0	0	0
T219	3734	0	0	0
T223	3116	0	0	0
T224	0	25	0	0
T230	120402	78	0	0
T231	3549	0	0	0
T233	3310	0	0	0
T236	0	19	0	0
T240	0	151	0	0
T241	0	163	0	0
T248	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4325	0	0
T111	60168	36	0	0
T189	3625	0	0	0
T190	6864	5	0	0
T191	60680	0	0	0
T192	0	15	0	0
T199	0	17	0	0
T200	3576	0	0	0
T219	3734	10	0	0
T223	3116	0	0	0
T224	0	41	0	0
T230	120402	106	0	0
T231	3549	0	0	0
T233	3310	0	0	0
T236	0	2	0	0
T240	0	127	0	0
T272	0	7	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2478	0	0
T192	7494	2	0	0
T195	13861	0	0	0
T196	17394	0	0	0
T199	0	5	0	0
T220	7483	0	0	0
T224	12006	50	0	0
T234	4011	0	0	0
T235	10487	0	0	0
T236	0	11	0	0
T237	0	7	0	0
T240	0	109	0	0
T241	0	108	0	0
T248	0	6	0	0
T272	3351	0	0	0
T273	4224	0	0	0
T274	3078	0	0	0
T279	0	9	0	0
T280	0	1	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2767	0	0
T192	7494	7	0	0
T195	13861	0	0	0
T196	17394	0	0	0
T199	0	6	0	0
T220	7483	0	0	0
T224	12006	79	0	0
T234	4011	0	0	0
T235	10487	0	0	0
T236	0	21	0	0
T240	0	150	0	0
T241	0	153	0	0
T262	0	35	0	0
T272	3351	0	0	0
T273	4224	0	0	0
T274	3078	0	0	0
T279	0	8	0	0
T280	0	8	0	0
T281	0	10	0	0