Module Definition
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Module : prim_generic_otp
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.39 96.91 95.45 100.00 94.59 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp.gen_generic.u_impl_generic 97.39 96.91 95.45 100.00 94.59 100.00



Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.39 96.91 95.45 100.00 94.59 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.17 91.72 94.58 100.00 100.00 90.71 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_otp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_dec 100.00 100.00 100.00
u_enc 100.00 100.00
u_prim_ram_1p_adv 99.58 98.31 100.00 100.00 100.00
u_reg_top 94.50 89.51 93.19 100.00 89.82 100.00
u_state_regs 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_otp
Line No.TotalCoveredPercent
TOTAL979496.91
CONT_ASSIGN7411100.00
CONT_ASSIGN78100.00
CONT_ASSIGN82100.00
CONT_ASSIGN84100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17411100.00
ALWAYS1786060100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN32911100.00
ALWAYS33300
ALWAYS33333100.00
ALWAYS36633100.00
ALWAYS3691717100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 1 1
78 0 1
82 0 1
84 0 1
87 1 1
90 1 1
114 1 1
170 1 1
173 1 1
174 1 1
178 1 1
179 1 1
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
189 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
==> MISSING_ELSE
MISSING_ELSE
202 1 1
203 1 1
204 1 1
208 1 1
209 1 1
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
MISSING_ELSE
222 1 1
223 1 1
227 1 1
228 1 1
230 1 1
231 1 1
232 1 1
233 1 1
235 1 1
236 1 1
237 1 1
239 1 1
242 1 1
243 1 1
MISSING_ELSE
MISSING_ELSE
251 1 1
252 1 1
254 1 1
259 1 1
260 1 1
261 1 1
263 1 1
264 1 1
265 1 1
267 1 1
MISSING_ELSE
274 1 1
275 1 1
276 1 1
277 1 1
278 1 1
MISSING_ELSE
281 1 1
282 1 1
283 1 1
MISSING_ELSE
288 1 1
302 1 1
322 1 1
326 1 1
329 1 1
333 1 1
334 1 1
336 1 1
366 3 3
369 1 1
370 1 1
371 1 1
372 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
382 1 1
383 1 1
384 1 1
MISSING_ELSE
386 1 1
387 1 1
MISSING_ELSE


Cond Coverage for Module : prim_generic_otp
TotalCoveredPercent
Conditions222195.45
Logical222195.45
Non-Logical00
Event00

 LINE       90
 EXPRESSION (intg_err || fsm_err)
             ----1---    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T23,T24
10CoveredT5,T23,T24

 LINE       170
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (cmd_i == Init)
            -------1-------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       235
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       263
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       281
 EXPRESSION (cnt_q == size_q)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       322
 EXPRESSION (read_ecc_on ? ({{EccWidth {1'b0}}, rdata_corr}) : rdata_ecc)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       329
 EXPRESSION ((rdata_q[cnt_q] & wdata_ecc) != rdata_q[cnt_q])
            ------------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       381
 EXPRESSION (ready_o && valid_i)
             ---1---    ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

FSM Coverage for Module : prim_generic_otp
Summary for FSM :: state_q
TotalCoveredPercent
States 9 9 100.00 (Not included in score)
Transitions 11 11 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
ErrorSt 287 Covered T19
IdleSt 202 Covered T19
InitSt 196 Covered T19
ReadSt 214 Covered T19
ReadWaitSt 222 Covered T19
ResetSt 191 Covered T19
WriteCheckSt 215 Covered T19
WriteSt 265 Covered T19
WriteWaitSt 251 Covered T19


transitionsLine No.CoveredTests
IdleSt->ReadSt 214 Covered T19
IdleSt->WriteCheckSt 215 Covered T19
InitSt->IdleSt 202 Covered T19
ReadSt->ReadWaitSt 222 Covered T19
ReadWaitSt->IdleSt 231 Covered T19
ReadWaitSt->ReadSt 239 Covered T19
ResetSt->InitSt 196 Covered T19
WriteCheckSt->WriteWaitSt 251 Covered T19
WriteSt->IdleSt 283 Covered T19
WriteWaitSt->WriteCheckSt 267 Covered T19
WriteWaitSt->WriteSt 265 Covered T19



Branch Coverage for Module : prim_generic_otp
Line No.TotalCoveredPercent
Branches 37 35 94.59
TERNARY 170 3 3 100.00
TERNARY 322 2 2 100.00
CASE 189 25 23 92.00
IF 366 2 2 100.00
IF 369 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv' or '../src/lowrisc_prim_generic_otp_0/rtl/prim_generic_otp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 170 (cnt_clr) ? -2-: 170 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 322 (read_ecc_on) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 189 case (state_q) -2-: 194 if (valid_i) -3-: 195 if ((cmd_i == Init)) -4-: 210 if (valid_i) -5-: 213 case (cmd_i) -6-: 227 if (rvalid) -7-: 230 if (rerror[1]) -8-: 235 if ((cnt_q == size_q)) -9-: 242 if (rerror[0]) -10-: 260 if (rvalid) -11-: 263 if ((cnt_q == size_q)) -12-: 277 if (wdata_inconsistent) -13-: 281 if ((cnt_q == size_q))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
ResetSt 1 1 - - - - - - - - - - Covered T1,T2,T3
ResetSt 1 0 - - - - - - - - - - Not Covered
ResetSt 0 - - - - - - - - - - - Covered T1,T2,T3
InitSt - - - - - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 Read - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 Write - - - - - - - - Covered T1,T2,T3
IdleSt - - 1 default - - - - - - - - Not Covered
IdleSt - - 0 - - - - - - - - - Covered T1,T2,T3
ReadSt - - - - - - - - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 1 - - - - - - Covered T3,T44,T94
ReadWaitSt - - - - 1 0 1 - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 0 0 - - - - - Covered T1,T2,T3
ReadWaitSt - - - - 1 0 - 1 - - - - Covered T3,T44,T94
ReadWaitSt - - - - 1 0 - 0 - - - - Covered T1,T2,T3
ReadWaitSt - - - - 0 - - - - - - - Covered T1,T2,T3
WriteCheckSt - - - - - - - - - - - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 1 1 - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 1 0 - - Covered T1,T2,T3
WriteWaitSt - - - - - - - - 0 - - - Covered T1,T2,T3
WriteSt - - - - - - - - - - 1 - Covered T12,T84,T115
WriteSt - - - - - - - - - - 0 - Covered T1,T2,T3
WriteSt - - - - - - - - - - - 1 Covered T1,T2,T3
WriteSt - - - - - - - - - - - 0 Covered T1,T2,T3
ErrorSt - - - - - - - - - - - - Covered T5,T23,T24
default - - - - - - - - - - - - Covered T5,T23,T24


LineNo. Expression -1-: 366 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if ((!rst_ni)) -2-: 381 if ((ready_o && valid_i)) -3-: 386 if (rvalid)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : prim_generic_otp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckCommands0_A 2147483647 11891 0 0
CheckCommands1_A 2147483647 1316668 0 0
NoWrapArounds_A 2147483647 4017323 0 0
SecDecWidth_A 1160 1160 0 0
u_state_regs_A 2147483647 2147483647 0 0


CheckCommands0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 11891 0 0
T1 16190 4 0 0
T2 17931 4 0 0
T3 11516 3 0 0
T4 52884 9 0 0
T5 800083 301 0 0
T6 23145 6 0 0
T7 16974 3 0 0
T8 10927 4 0 0
T9 11671 4 0 0
T10 11346 5 0 0

CheckCommands1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1316668 0 0
T1 16190 145 0 0
T2 17931 165 0 0
T3 11516 197 0 0
T4 52884 649 0 0
T5 800083 15351 0 0
T6 23145 476 0 0
T7 16974 281 0 0
T8 10927 118 0 0
T9 11671 174 0 0
T10 11346 168 0 0

NoWrapArounds_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 4017323 0 0
T1 16190 587 0 0
T2 17931 676 0 0
T3 11516 766 0 0
T4 52884 2346 0 0
T5 800083 61404 0 0
T6 23145 1722 0 0
T7 16974 1094 0 0
T8 10927 470 0 0
T9 11671 694 0 0
T10 11346 704 0 0

SecDecWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1160 1160 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 16190 15916 0 0
T2 17931 17671 0 0
T3 11516 11297 0 0
T4 52884 52304 0 0
T5 800083 780123 0 0
T6 23145 22587 0 0
T7 16974 16660 0 0
T8 10927 10658 0 0
T9 11671 11457 0 0
T10 11346 10483 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%