Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1306020
Category 01306020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1306020
Severity 01306020

Summary for Assertions
NUMBERPERCENT
Total Number1306100.00
Uncovered463.52
Success126096.48
Failure00.00
Incomplete100.77
Without Attempts40.31

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001226122600
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 00211590577117234400100
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001226122600
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 0021159057714630025700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001226122600
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 0021159057717279482800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001226122600
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 0021159057716766404200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001226122600
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 0021159057719954917300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 002115905771211511066900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001226122600
tb.dut.u_reg_core.u_socket.maxN 001226122600
tb.dut.u_reg_core.wePulse 002115905771266092400
tb.dut.u_scrmbl_mtx.CheckHotOne_A 002113347341211259980100
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A 001074107400
tb.dut.u_scrmbl_mtx.GrantKnown_A 002113347341211259980100
tb.dut.u_scrmbl_mtx.IdxKnown_A 002113347341211259980100
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A 002113347341207809612800
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A 0021133473413450367300
tb.dut.u_scrmbl_mtx.ValidKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A 001074107400
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A 001074107400
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A 001074107400
tb.dut.u_tlul_adapter_sram.TlOutKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_A 0021133473417277196100
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_AKnownEnable 002113347341211259980100
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.WeOutKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite 001074107400
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty 0021133473418028200
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull 0021133473418028200
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A 001074107400
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A 0021133473417324199500
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0021133473417324199500
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A 001074107400
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck 001074107400
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A 00211334734119199100
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00211334734119199100
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A 00211334734155031600
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A 002113347341211259980100
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00211334734155031600
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001074107400
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A 002113347341211259980100
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 002113347341211259980100
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A 001074107400
tb.dut.u_tlul_lc_gate.u_state_regs_A 002113347341211259980100
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001074107400
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001074107400

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_edn_arb.RoundRobin_A 002113347341001074
tb.dut.u_otp_arb.RoundRobin_A 002113347341001074
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A 002113347341001074
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 002113347341001074
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 002113347341211256454903222
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 002113347341211256454903222
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 002113347341211256454903222
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 002113347341211256454903222
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 002113347341211256454903222
tb.dut.u_scrmbl_mtx.RoundRobin_A 002113347341001074

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A 000000

Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021159066096196190
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021159066091291290
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021159066091321320
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00211590660992920
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00211590660911110
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00211590660965650
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00211590660960600
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002115906609275327530
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 002115906609692669260
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 002115906609161464116146411142
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021159066092392390
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00211590660958580
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00211590660959590
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00211590660937370
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 002115906609220
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00211590660931310
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00211590660923230
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002115906609119111910
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 002115906609322232220
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 002115906609476844768471

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021159066096196190
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021159066091291290
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021159066091321320
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00211590660992920
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00211590660911110
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00211590660965650
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00211590660960600
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002115906609275327530
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 002115906609692669260
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 002115906609161464116146411142
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021159066092392390
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00211590660958580
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00211590660959590
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00211590660937370
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 002115906609220
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00211590660931310
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00211590660923230
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002115906609119111910
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 002115906609322232220
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 002115906609476844768471