Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[5].gen_buffered.u_part_buf

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	91.88	87.50		94.44	84.93	94.29

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	93.87	86.44	93.73	94.44	87.36	95.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.98	97.18	88.57	97.19		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	92.07	100.00	66.67	93.69		100.00	100.00
u_prim_count	100.00			100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.05	91.88	87.50		91.67	84.93	94.29

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.44	93.87	86.44	93.73	91.67	87.36	95.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.98	97.18	88.57	97.19		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	92.07	100.00	66.67	93.69		100.00	100.00
u_prim_count	100.00			100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		160	147	91.88
CONT_ASSIGN	182	1	1	100.00
ALWAYS	190	140	127	90.71
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
ALWAYS	748	3	3	100.00
ALWAYS	751	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
190	1	1
193	1	1
196	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
217	1	1
218	1	1
221	1	1
222	1	1
224	1	1
229	1	1
230	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
			MISSING_ELSE
249	1	1
250	1	1
253	1	1
258	1	1
259	1	1
262	1	1
263	1	1
265		unreachable
266		unreachable
273	1	1
274	1	1
			MISSING_ELSE
277	1	1
278	1	1
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
			MISSING_ELSE
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
322		unreachable
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
334	1	1
339	1	1
340	1	1
			==> MISSING_ELSE
342	1	1
343	1	1
			MISSING_ELSE
353	1	1
356	1	1
360	1	1
362	1	1
363	1	1
364	1	1
367	0	1
368	0	1
370	0	1
375		unreachable
379		unreachable
380		unreachable
381		unreachable
384		unreachable
385		unreachable
388		unreachable
389		unreachable
391		unreachable
399	1	1
400	1	1
			MISSING_ELSE
403	1	1
404	1	1
406	1	1
			MISSING_ELSE
415	1	1
416	1	1
417	1	1
418	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
			MISSING_ELSE
430		unreachable
431		unreachable
432		unreachable
			==> MISSING_ELSE
441		unreachable
442		unreachable
443		unreachable
			==> MISSING_ELSE
453	1	1
454	1	1
455	1	1
456	1	1
457	1	1
458	1	1
			MISSING_ELSE
465	1	1
466	1	1
467	1	1
468	1	1
			MISSING_ELSE
478	1	1
479	1	1
480	1	1
481	1	1
483	1	1
487	1	1
488	1	1
489	1	1
491	0	1
492	0	1
496	1	1
497	1	1
			MISSING_ELSE
501	1	1
502	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
514	0	1
515	0	1
516	0	1
517	0	1
518	0	1
			==> MISSING_ELSE
526	1	1
527	1	1
528	1	1
529	1	1
530	1	1
			MISSING_ELSE
540	1	1
541	1	1
542	1	1
545	1	1
546	1	1
549	1	1
550	1	1
554	1	1
558	1	1
559	1	1
561	1	1
			MISSING_ELSE
570	1	1
571	1	1
572	1	1
			MISSING_ELSE
576	1	1
577	1	1
593	1	1
594	0	1
595	0	1
596	0	1
			==> MISSING_ELSE
			MISSING_ELSE
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
			MISSING_ELSE
			MISSING_ELSE
633	1	1
638	1	1
639	1	1
643	1	1
650	1	1
652	1	1
673	1	1
676	1	1
678	1	1
707	1	1
727	1	1
748	3	3
751	1	1
752	1	1
754	1	1
756	1	1
757	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	56	49	87.50
Logical	56	49	87.50
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T66,T67
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       258
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T23,T68

 LINE       293
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       356
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T52,T26
0	1	Covered	T5,T6,T7
1	0	Unreachable

 LINE       362
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T7,T11,T15
1	0	Covered	T6,T10,T29

 LINE       362
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T7,T11,T15
1	Covered	T5,T6,T7

 LINE       362
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T6,T10,T29
1	Covered	T5,T6,T7

 LINE       379
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       399
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T60,T47,T69

 LINE       424
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       483
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       545
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T70,T71,T72
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T10

 LINE       545
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T10

 LINE       545
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T17,T18,T19

 LINE       595
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       603
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T5,T7

 LINE       633
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011111000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       633
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       676
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       707
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T10

 LINE       707
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T10

 LINE       727
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T10

 LINE       727
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	31	30	96.77
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyReadSt	325	Covered	T14
CnstyReadWaitSt	343	Covered	T14
ErrorSt	277	Covered	T14
IdleSt	363	Covered	T14
InitDescrSt	263	Covered	T14
InitDescrWaitSt	294	Covered	T14
InitSt	230	Covered	T14
InitWaitSt	240	Covered	T14
IntegDigClrSt	259	Covered	T14
IntegDigFinSt	489	Covered	T14
IntegDigPadSt	491	Excluded
IntegDigSt	432	Covered	T14
IntegDigWaitSt	530	Covered	T14
IntegScrSt	425	Covered	T14
IntegScrWaitSt	458	Covered	T14
ResetSt	228	Covered	T14

transitions	Line No.	Covered	Tests
CnstyReadSt->CnstyReadWaitSt	343	Covered	T14
CnstyReadSt->ErrorSt	594	Covered	T14
CnstyReadWaitSt->CnstyReadSt	384	Excluded
CnstyReadWaitSt->ErrorSt	367	Covered	T14
CnstyReadWaitSt->IdleSt	363	Covered	T14
IdleSt->CnstyReadSt	325	Covered	T14
IdleSt->ErrorSt	594	Covered	T14
IdleSt->IntegDigClrSt	317	Covered	T14
InitDescrSt->ErrorSt	594	Covered	T14
InitDescrSt->InitDescrWaitSt	294	Covered	T14
InitDescrWaitSt->ErrorSt	594	Covered	T14
InitDescrWaitSt->InitSt	306	Covered	T14
InitSt->ErrorSt	594	Covered	T14
InitSt->InitWaitSt	240	Covered	T14
InitWaitSt->ErrorSt	277	Covered	T14
InitWaitSt->InitDescrSt	263	Covered	T14
InitWaitSt->InitSt	265	Excluded
InitWaitSt->IntegDigClrSt	259	Covered	T14
IntegDigClrSt->ErrorSt	594	Covered	T14
IntegDigClrSt->IdleSt	441	Excluded
IntegDigClrSt->IntegDigSt	432	Excluded
IntegDigClrSt->IntegScrSt	425	Covered	T14
IntegDigFinSt->ErrorSt	594	Covered	T14
IntegDigFinSt->IntegDigWaitSt	530	Covered	T14
IntegDigPadSt->ErrorSt	594	Excluded
IntegDigPadSt->IntegDigFinSt	518	Excluded
IntegDigSt->ErrorSt	594	Not Covered
IntegDigSt->IntegDigFinSt	489	Covered	T14
IntegDigSt->IntegDigPadSt	491	Excluded
IntegDigSt->IntegScrSt	502	Covered	T14
IntegDigWaitSt->ErrorSt	558	Covered	T14
IntegDigWaitSt->IdleSt	546	Covered	T14
IntegScrSt->ErrorSt	594	Covered	T14
IntegScrSt->IntegScrWaitSt	458	Covered	T14
IntegScrWaitSt->ErrorSt	594	Covered	T14
IntegScrWaitSt->IntegDigSt	468	Covered	T14
ResetSt->ErrorSt	594	Covered	T14
ResetSt->InitSt	230	Covered	T14

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	368	Covered	T14
FsmStateError	572	Covered	T14
MacroEccCorrError	274	Covered	T14
NoError	571	Covered	T14

transitions	Line No.	Covered	Tests
CheckFailError->FsmStateError	604	Excluded
CheckFailError->MacroEccCorrError	274	Excluded
FsmStateError->CheckFailError	368	Excluded
FsmStateError->MacroEccCorrError	274	Excluded
MacroEccCorrError->CheckFailError	368	Not Covered
MacroEccCorrError->FsmStateError	604	Covered	T14
NoError->CheckFailError	368	Covered	T14
NoError->FsmStateError	572	Covered	T14
NoError->MacroEccCorrError	274	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
Branches		73	62	84.93
TERNARY	633	2	2	100.00
TERNARY	652	2	2	100.00
TERNARY	676	2	2	100.00
TERNARY	707	2	2	100.00
TERNARY	727	2	2	100.00
CASE	224	53	44	83.02
IF	593	3	1	33.33
IF	600	3	3	100.00
IF	748	2	2	100.00
IF	751	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	633	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	652	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	676	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	707	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	727	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	case (state_q)
-2-:	229	if (init_req_i)
-3-:	239	if (otp_gnt_i)
-4-:	249	if (otp_rvalid_i)
-5-:	253	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	258	if ((cnt == LastScrmblBlock))
-7-:	262	if (1'b1)
-8-:	273	if ((otp_err_e'(otp_err_i) != NoError))
-9-:	293	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	305	if (scrmbl_valid_i)
-11-:	315	if (integ_chk_req_i)
-12-:	316	if (1'b1)
-13-:	324	if (cnsty_chk_req_i)
-14-:	339	if (1'b1)
-15-:	342	if (otp_gnt_i)
-16-:	353	if (otp_rvalid_i)
-17-:	356	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-18-:	360	if (1'b1)
-19-:	362	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	375	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	379	if ((cnt == LastScrmblBlock))
-22-:	399	if ((otp_err_e'(otp_err_i) != NoError))
-23-:	415	if (1'b1)
-24-:	422	if (1'b1)
-25-:	424	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	431	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	442	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	457	if (scrmbl_ready_i)
-29-:	467	if (scrmbl_valid_i)
-30-:	480	if (scrmbl_ready_i)
-31-:	483	if ((cnt == PenultimateScrmblBlock))
-32-:	487	if (cnt[0])
-33-:	496	if (cnt[0])
-34-:	501	if (1'b1)
-35-:	517	if (scrmbl_ready_i)
-36-:	529	if (scrmbl_ready_i)
-37-:	542	if (scrmbl_valid_i)
-38-:	545	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	549	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	571	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T23,T68
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T66,T67
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T60,T47,T69
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T52,T26
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Covered	T4,T5,T6
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T70,T71,T72
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	593	if (ecc_err)
-2-:	595	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	603	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T5,T7
1	0	Covered	T1,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	748	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	751	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	34	97.14	33	94.29
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	34	97.14	33	94.29

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2113347341	2112599801	0	0
BypassEnable0_A	2113347341	2112599801	0	0
BypassEnable1_A	2113347341	2112599801	0	0
CnstyChkAckKnown_A	2113347341	2112599801	0	0
DataKnown_A	2113347341	2112599801	0	0
DigestKnown_A	2113347341	2112599801	0	0
DigestOffsetMustBeRepresentable_A	1074	1074	0	0
EccErrorState_A	2113347341	0	0	0
ErrorKnown_A	2113347341	2112599801	0	0
InitDoneKnown_A	2113347341	2112599801	0	0
InitReadLocksPartition_A	2113347341	520835186	0	0
InitWriteLocksPartition_A	2113347341	520835186	0	0
IntegChkAckKnown_A	2113347341	2112599801	0	0
OffsetMustBeBlockAligned_A	1074	1074	0	0
OtpAddrKnown_A	2113347341	2112599801	0	0
OtpCmdKnown_A	2113347341	2112599801	0	0
OtpErrorState_A	0	0	0	0
OtpReqKnown_A	2113347341	2112599801	0	0
OtpSizeKnown_A	2113347341	2112599801	0	0
OtpWdataKnown_A	2113347341	2112599801	0	0
ReadLockImpliesDigest_A	2113347341	2112599801	0	0
ReadLockPropagation_A	2113347341	866561	0	0
ScrambledImpliesDigest_A	2113347341	2112599801	0	0
ScrmblCmdKnown_A	2113347341	2112599801	0	0
ScrmblDataKnown_A	2113071478	2112323938	0	0
ScrmblModeKnown_A	2113347341	2112599801	0	0
ScrmblMtxReqKnown_A	2113347341	2112599801	0	0
ScrmblSelKnown_A	2113347341	2112599801	0	0
ScrmblValidKnown_A	2113347341	2112599801	0	0
SizeMustBeBlockAligned_A	1074	1074	0	0
WriteLockImpliesDigest_A	2113347341	2112599801	0	0
WriteLockPropagation_A	2113347341	1005490	0	0
gen_digest_read_lock.DigestReadLocksPartition_A	2113347341	12750203	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2113347341	12750203	0	0
u_state_regs_A	2113347341	2112599801	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

BypassEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

BypassEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

CnstyChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	520835186	0	0
T1	11113	5332	0	0
T2	3878	1892	0	0
T3	13890	6784	0	0
T4	299830	11245	0	0
T5	53537	23321	0	0
T6	41089	18747	0	0
T7	107806	242297	0	0
T8	19001	9253	0	0
T9	31345	25774	0	0
T10	47178	19189	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	520835186	0	0
T1	11113	5332	0	0
T2	3878	1892	0	0
T3	13890	6784	0	0
T4	299830	11245	0	0
T5	53537	23321	0	0
T6	41089	18747	0	0
T7	107806	242297	0	0
T8	19001	9253	0	0
T9	31345	25774	0	0
T10	47178	19189	0	0

IntegChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ReadLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	866561	0	0
T6	41089	1916	0	0
T7	107806	0	0	0
T8	19001	0	0	0
T9	31345	0	0	0
T10	47178	0	0	0
T29	49609	753	0	0
T30	0	3767	0	0
T31	0	597	0	0
T38	23629	0	0	0
T85	0	2158	0	0
T89	0	684	0	0
T91	0	4704	0	0
T93	0	9547	0	0
T95	0	378	0	0
T96	0	2140	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T99	18996	0	0	0

ScrambledImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113071478	2112323938	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WriteLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	1005490	0	0
T6	41089	2253	0	0
T7	107806	0	0	0
T8	19001	0	0	0
T9	31345	0	0	0
T10	47178	593	0	0
T29	49609	0	0	0
T30	0	2812	0	0
T38	23629	0	0	0
T85	0	2076	0	0
T87	0	13680	0	0
T89	0	4333	0	0
T91	0	1056	0	0
T92	0	2973	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T99	18996	0	0	0
T105	0	3047	0	0
T106	0	10726	0	0

gen_digest_read_lock.DigestReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	12750203	0	0
T5	53537	3953	0	0
T6	41089	17106	0	0
T7	107806	0	0	0
T8	19001	0	0	0
T9	31345	0	0	0
T10	47178	19347	0	0
T29	49609	14363	0	0
T30	0	61531	0	0
T31	0	28287	0	0
T35	0	4084	0	0
T38	23629	0	0	0
T87	0	79080	0	0
T88	0	27933	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T103	0	8902	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	12750203	0	0
T5	53537	3953	0	0
T6	41089	17106	0	0
T7	107806	0	0	0
T8	19001	0	0	0
T9	31345	0	0	0
T10	47178	19347	0	0
T29	49609	14363	0	0
T30	0	61531	0	0
T31	0	28287	0	0
T35	0	4084	0	0
T38	23629	0	0	0
T87	0	79080	0	0
T88	0	27933	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T103	0	8902	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		160	147	91.88
CONT_ASSIGN	182	1	1	100.00
ALWAYS	190	140	127	90.71
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
ALWAYS	748	3	3	100.00
ALWAYS	751	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
190	1	1
193	1	1
196	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
217	1	1
218	1	1
221	1	1
222	1	1
224	1	1
229	1	1
230	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
			MISSING_ELSE
249	1	1
250	1	1
253	1	1
258	1	1
259	1	1
262	1	1
263	1	1
265		unreachable
266		unreachable
273	1	1
274	1	1
			MISSING_ELSE
277	1	1
278	1	1
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
			MISSING_ELSE
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
322		unreachable
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
334	1	1
339	1	1
340	1	1
			==> MISSING_ELSE
342	1	1
343	1	1
			MISSING_ELSE
353	1	1
356	1	1
360	1	1
362	1	1
363	1	1
364	1	1
367	0	1
368	0	1
370	0	1
375		unreachable
379		unreachable
380		unreachable
381		unreachable
384		unreachable
385		unreachable
388		unreachable
389		unreachable
391		unreachable
399	1	1
400	1	1
			MISSING_ELSE
403	1	1
404	1	1
406	1	1
			MISSING_ELSE
415	1	1
416	1	1
417	1	1
418	1	1
421	1	1
422	1	1
423	1	1
424	1	1
425	1	1
			MISSING_ELSE
430		unreachable
431		unreachable
432		unreachable
			==> MISSING_ELSE
441		unreachable
442		unreachable
443		unreachable
			==> MISSING_ELSE
453	1	1
454	1	1
455	1	1
456	1	1
457	1	1
458	1	1
			MISSING_ELSE
465	1	1
466	1	1
467	1	1
468	1	1
			MISSING_ELSE
478	1	1
479	1	1
480	1	1
481	1	1
483	1	1
487	1	1
488	1	1
489	1	1
491	0	1
492	0	1
496	1	1
497	1	1
			MISSING_ELSE
501	1	1
502	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
514	0	1
515	0	1
516	0	1
517	0	1
518	0	1
			==> MISSING_ELSE
526	1	1
527	1	1
528	1	1
529	1	1
530	1	1
			MISSING_ELSE
540	1	1
541	1	1
542	1	1
545	1	1
546	1	1
549	1	1
550	1	1
554	1	1
558	1	1
559	1	1
561	1	1
			MISSING_ELSE
570	1	1
571	1	1
572	1	1
			MISSING_ELSE
576	1	1
577	1	1
593	1	1
594	0	1
595	0	1
596	0	1
			==> MISSING_ELSE
			MISSING_ELSE
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
			MISSING_ELSE
			MISSING_ELSE
633	1	1
638	1	1
639	1	1
643	1	1
650	1	1
652	1	1
673	1	1
676	1	1
678	1	1
707	1	1
727	1	1
748	3	3
751	1	1
752	1	1
754	1	1
756	1	1
757	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	56	49	87.50
Logical	56	49	87.50
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       258
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T23,T24

 LINE       293
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       356
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T27
0	1	Covered	T5,T6,T7
1	0	Unreachable

 LINE       362
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T15,T12,T28
1	0	Covered	T29,T30,T31

 LINE       362
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T15,T12,T28
1	Covered	T5,T6,T7

 LINE       362
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T29,T30,T31
1	Covered	T5,T6,T7

 LINE       379
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       399
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T32,T33,T34

 LINE       424
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       431
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       483
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       545
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T38

 LINE       545
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T38

 LINE       545
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T6,T8,T38
1	Covered	T1,T2,T3

 LINE       571
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T17,T18,T19

 LINE       595
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       603
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T5

 LINE       633
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11101010000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       633
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       676
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       707
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T38

 LINE       707
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T38

 LINE       727
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T38

 LINE       727
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T38

---

FSM Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	31	29	93.55
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyReadSt	325	Covered	T14
CnstyReadWaitSt	343	Covered	T14
ErrorSt	277	Covered	T14
IdleSt	363	Covered	T14
InitDescrSt	263	Covered	T14
InitDescrWaitSt	294	Covered	T14
InitSt	230	Covered	T14
InitWaitSt	240	Covered	T14
IntegDigClrSt	259	Covered	T14
IntegDigFinSt	489	Covered	T14
IntegDigPadSt	491	Excluded
IntegDigSt	432	Covered	T14
IntegDigWaitSt	530	Covered	T14
IntegScrSt	425	Covered	T14
IntegScrWaitSt	458	Covered	T14
ResetSt	228	Covered	T14

transitions	Line No.	Covered	Tests
CnstyReadSt->CnstyReadWaitSt	343	Covered	T14
CnstyReadSt->ErrorSt	594	Covered	T14
CnstyReadWaitSt->CnstyReadSt	384	Excluded
CnstyReadWaitSt->ErrorSt	367	Covered	T14
CnstyReadWaitSt->IdleSt	363	Covered	T14
IdleSt->CnstyReadSt	325	Covered	T14
IdleSt->ErrorSt	594	Covered	T14
IdleSt->IntegDigClrSt	317	Covered	T14
InitDescrSt->ErrorSt	594	Covered	T14
InitDescrSt->InitDescrWaitSt	294	Covered	T14
InitDescrWaitSt->ErrorSt	594	Covered	T14
InitDescrWaitSt->InitSt	306	Covered	T14
InitSt->ErrorSt	594	Covered	T14
InitSt->InitWaitSt	240	Covered	T14
InitWaitSt->ErrorSt	277	Covered	T14
InitWaitSt->InitDescrSt	263	Covered	T14
InitWaitSt->InitSt	265	Excluded
InitWaitSt->IntegDigClrSt	259	Covered	T14
IntegDigClrSt->ErrorSt	594	Covered	T14
IntegDigClrSt->IdleSt	441	Excluded
IntegDigClrSt->IntegDigSt	432	Excluded
IntegDigClrSt->IntegScrSt	425	Covered	T14
IntegDigFinSt->ErrorSt	594	Not Covered
IntegDigFinSt->IntegDigWaitSt	530	Covered	T14
IntegDigPadSt->ErrorSt	594	Excluded
IntegDigPadSt->IntegDigFinSt	518	Excluded
IntegDigSt->ErrorSt	594	Not Covered
IntegDigSt->IntegDigFinSt	489	Covered	T14
IntegDigSt->IntegDigPadSt	491	Excluded
IntegDigSt->IntegScrSt	502	Covered	T14
IntegDigWaitSt->ErrorSt	558	Covered	T14
IntegDigWaitSt->IdleSt	546	Covered	T14
IntegScrSt->ErrorSt	594	Covered	T14
IntegScrSt->IntegScrWaitSt	458	Covered	T14
IntegScrWaitSt->ErrorSt	594	Covered	T14
IntegScrWaitSt->IntegDigSt	468	Covered	T14
ResetSt->ErrorSt	594	Covered	T14
ResetSt->InitSt	230	Covered	T14

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	368	Covered	T14
FsmStateError	572	Covered	T14
MacroEccCorrError	274	Covered	T14
NoError	571	Covered	T14

transitions	Line No.	Covered	Tests
CheckFailError->FsmStateError	604	Excluded
CheckFailError->MacroEccCorrError	274	Excluded
FsmStateError->CheckFailError	368	Excluded
FsmStateError->MacroEccCorrError	274	Excluded
MacroEccCorrError->CheckFailError	368	Not Covered
MacroEccCorrError->FsmStateError	604	Covered	T14
NoError->CheckFailError	368	Covered	T14
NoError->FsmStateError	572	Covered	T14
NoError->MacroEccCorrError	274	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
Branches		73	62	84.93
TERNARY	633	2	2	100.00
TERNARY	652	2	2	100.00
TERNARY	676	2	2	100.00
TERNARY	707	2	2	100.00
TERNARY	727	2	2	100.00
CASE	224	53	44	83.02
IF	593	3	1	33.33
IF	600	3	3	100.00
IF	748	2	2	100.00
IF	751	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	633	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	652	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	676	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	707	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	727	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T38
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	case (state_q)
-2-:	229	if (init_req_i)
-3-:	239	if (otp_gnt_i)
-4-:	249	if (otp_rvalid_i)
-5-:	253	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	258	if ((cnt == LastScrmblBlock))
-7-:	262	if (1'b1)
-8-:	273	if ((otp_err_e'(otp_err_i) != NoError))
-9-:	293	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	305	if (scrmbl_valid_i)
-11-:	315	if (integ_chk_req_i)
-12-:	316	if (1'b1)
-13-:	324	if (cnsty_chk_req_i)
-14-:	339	if (1'b1)
-15-:	342	if (otp_gnt_i)
-16-:	353	if (otp_rvalid_i)
-17-:	356	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-18-:	360	if (1'b1)
-19-:	362	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	375	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	379	if ((cnt == LastScrmblBlock))
-22-:	399	if ((otp_err_e'(otp_err_i) != NoError))
-23-:	415	if (1'b1)
-24-:	422	if (1'b1)
-25-:	424	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	431	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	442	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	457	if (scrmbl_ready_i)
-29-:	467	if (scrmbl_valid_i)
-30-:	480	if (scrmbl_ready_i)
-31-:	483	if ((cnt == PenultimateScrmblBlock))
-32-:	487	if (cnt[0])
-33-:	496	if (cnt[0])
-34-:	501	if (1'b1)
-35-:	517	if (scrmbl_ready_i)
-36-:	529	if (scrmbl_ready_i)
-37-:	542	if (scrmbl_valid_i)
-38-:	545	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	549	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	571	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T24
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Covered	T4,T5,T6
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T35,T36,T37
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	593	if (ecc_err)
-2-:	595	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	603	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	748	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	751	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	34	97.14	33	94.29
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	34	97.14	33	94.29

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2113347341	2112599801	0	0
BypassEnable0_A	2113347341	2112599801	0	0
BypassEnable1_A	2113347341	2112599801	0	0
CnstyChkAckKnown_A	2113347341	2112599801	0	0
DataKnown_A	2113347341	2112599801	0	0
DigestKnown_A	2113347341	2112599801	0	0
DigestOffsetMustBeRepresentable_A	1074	1074	0	0
EccErrorState_A	2113347341	0	0	0
ErrorKnown_A	2113347341	2112599801	0	0
InitDoneKnown_A	2113347341	2112599801	0	0
InitReadLocksPartition_A	2113347341	524664383	0	0
InitWriteLocksPartition_A	2113347341	524664383	0	0
IntegChkAckKnown_A	2113347341	2112599801	0	0
OffsetMustBeBlockAligned_A	1074	1074	0	0
OtpAddrKnown_A	2113347341	2112599801	0	0
OtpCmdKnown_A	2113347341	2112599801	0	0
OtpErrorState_A	0	0	0	0
OtpReqKnown_A	2113347341	2112599801	0	0
OtpSizeKnown_A	2113347341	2112599801	0	0
OtpWdataKnown_A	2113347341	2112599801	0	0
ReadLockImpliesDigest_A	2113347341	2112599801	0	0
ReadLockPropagation_A	2113347341	1234147067	0	0
ScrambledImpliesDigest_A	2113347341	2112599801	0	0
ScrmblCmdKnown_A	2113347341	2112599801	0	0
ScrmblDataKnown_A	2113071478	2112323938	0	0
ScrmblModeKnown_A	2113347341	2112599801	0	0
ScrmblMtxReqKnown_A	2113347341	2112599801	0	0
ScrmblSelKnown_A	2113347341	2112599801	0	0
ScrmblValidKnown_A	2113347341	2112599801	0	0
SizeMustBeBlockAligned_A	1074	1074	0	0
WriteLockImpliesDigest_A	2113347341	2112599801	0	0
WriteLockPropagation_A	2113347341	1234176530	0	0
gen_digest_read_lock.DigestReadLocksPartition_A	2113347341	9232462	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2113347341	9232462	0	0
u_state_regs_A	2113347341	2112599801	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

BypassEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

BypassEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

CnstyChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	524664383	0	0
T1	11113	5861	0	0
T2	3878	2421	0	0
T3	13890	7313	0	0
T4	299830	14419	0	0
T5	53537	29099	0	0
T6	41089	22296	0	0
T7	107806	242879	0	0
T8	19001	11369	0	0
T9	31345	26832	0	0
T10	47178	23930	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	524664383	0	0
T1	11113	5861	0	0
T2	3878	2421	0	0
T3	13890	7313	0	0
T4	299830	14419	0	0
T5	53537	29099	0	0
T6	41089	22296	0	0
T7	107806	242879	0	0
T8	19001	11369	0	0
T9	31345	26832	0	0
T10	47178	23930	0	0

IntegChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ReadLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	1234147067	0	0
T1	11113	6	0	0
T2	3878	2	0	0
T3	13890	8	0	0
T4	299830	145953	0	0
T5	53537	10881	0	0
T6	41089	6630	0	0
T7	107806	249722	0	0
T8	19001	16	0	0
T9	31345	26071	0	0
T10	47178	11676	0	0

ScrambledImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113071478	2112323938	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WriteLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	1234176530	0	0
T1	11113	6	0	0
T2	3878	2	0	0
T3	13890	8	0	0
T4	299830	145953	0	0
T5	53537	10881	0	0
T6	41089	6630	0	0
T7	107806	249722	0	0
T8	19001	16	0	0
T9	31345	26071	0	0
T10	47178	11676	0	0

gen_digest_read_lock.DigestReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	9232462	0	0
T6	41089	2970	0	0
T7	107806	0	0	0
T8	19001	2368	0	0
T9	31345	0	0	0
T10	47178	0	0	0
T29	49609	21083	0	0
T30	0	39183	0	0
T31	0	27990	0	0
T35	0	4051	0	0
T38	23629	3406	0	0
T87	0	72021	0	0
T88	0	25678	0	0
T89	0	27760	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T99	18996	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	9232462	0	0
T6	41089	2970	0	0
T7	107806	0	0	0
T8	19001	2368	0	0
T9	31345	0	0	0
T10	47178	0	0	0
T29	49609	21083	0	0
T30	0	39183	0	0
T31	0	27990	0	0
T35	0	4051	0	0
T38	23629	3406	0	0
T87	0	72021	0	0
T88	0	25678	0	0
T89	0	27760	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T99	18996	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0