Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.07	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if	10.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if	20.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
10.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	9	1	10.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	9	1	10.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
20.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	8	2	20.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	8	2	20.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	9	1	10.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1
true	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

12354

1

T14

1

T107

1

T108

41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	8	2	20.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

8982

1

T14

1

T107

1

T108

41

true

14481

1

T14

1

T107

1

T108

41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	58	1			T31	2		T87	2		T85	2
others[1]	82	1			T29	2		T88	2		T91	2
others[2]	72	1			T90	2		T92	2		T162	2
others[3]	84	1			T96	2		T32	2		T321	4
others[4]	68	1			T6	2		T29	2		T31	2
others[5]	68	1			T31	2		T321	2		T164	2
others[6]	106	1			T87	2		T90	2		T91	2
others[7]	80	1			T10	2		T104	2		T91	2
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	84	1			T6	2		T29	2		T104	2
others[1]	80	1			T52	8		T321	4		T322	2
others[2]	80	1			T10	2		T90	2		T92	2
others[3]	74	1			T106	2		T96	2		T52	2
others[4]	66	1			T85	4		T92	2		T33	2
others[5]	58	1			T96	2		T323	2		T166	2
others[6]	50	1			T166	2		T324	2		T325	8
others[7]	100	1			T321	6		T62	2		T33	2
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	82	1			T87	2		T96	2		T44	2
others[1]	74	1			T30	2		T89	2		T25	2
others[2]	74	1			T96	2		T326	4		T179	2
others[3]	76	1			T89	2		T162	4		T166	2
others[4]	62	1			T106	2		T164	2		T179	2
others[5]	48	1			T31	2		T85	2		T92	2
others[6]	90	1			T87	4		T96	4		T164	2
others[7]	98	1			T96	2		T163	2		T321	4
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	60	1			T30	2		T87	2		T91	4
others[1]	74	1			T93	2		T327	2		T138	2
others[2]	70	1			T162	2		T328	2		T329	2
others[3]	74	1			T88	2		T85	2		T92	2
others[4]	64	1			T87	2		T85	2		T321	4
others[5]	84	1			T87	2		T85	2		T90	2
others[6]	62	1			T52	2		T326	2		T146	2
others[7]	84	1			T31	2		T85	2		T92	2
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	70	1			T104	2		T96	2		T321	2
others[1]	112	1			T30	2		T88	2		T85	2
others[2]	86	1			T10	4		T31	2		T92	2
others[3]	88	1			T87	2		T91	2		T105	2
others[4]	70	1			T88	2		T85	2		T52	4
others[5]	82	1			T6	2		T92	2		T321	4
others[6]	56	1			T10	2		T106	2		T327	2
others[7]	52	1			T88	2		T89	2		T90	2
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	52	1			T6	2		T325	4		T330	2
others[1]	62	1			T30	2		T321	2		T326	2
others[2]	70	1			T93	2		T95	2		T326	4
others[3]	68	1			T29	2		T321	4		T326	2
others[4]	68	1			T85	2		T96	2		T32	2
others[5]	68	1			T31	2		T85	2		T91	2
others[6]	72	1			T162	2		T321	2		T33	2
others[7]	86	1			T89	2		T91	2		T162	2
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	76	1			T89	2		T85	2		T92	2
others[1]	70	1			T30	2		T95	2		T321	2
others[2]	80	1			T6	2		T87	2		T85	2
others[3]	90	1			T91	2		T96	4		T162	2
others[4]	68	1			T87	2		T162	2		T321	4
others[5]	66	1			T10	2		T95	2		T162	2
others[6]	78	1			T105	2		T321	2		T33	2
others[7]	82	1			T87	2		T89	2		T106	2
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	22	1			T163	2		T326	6		T324	2
others[1]	22	1			T31	2		T106	2		T258	2
others[2]	28	1			T87	2		T166	2		T326	2
others[3]	38	1			T164	4		T165	2		T328	2
others[4]	30	1			T29	2		T331	2		T180	2
others[5]	26	1			T161	2		T53	2		T151	4
others[6]	28	1			T10	2		T31	2		T87	2
others[7]	44	1			T10	2		T164	2		T326	2
false	12354	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	40	1			T4	1		T11	1		T213	1
others[1]	42	1			T7	1		T11	1		T12	1
others[2]	47	1			T7	1		T213	2		T214	1
others[3]	40	1			T15	2		T16	1		T28	1
others[4]	34	1			T7	1		T11	1		T15	1
others[5]	45	1			T7	2		T11	1		T15	2
others[6]	39	1			T7	1		T15	1		T28	1
others[7]	42	1			T15	2		T16	1		T28	1
false	12354	1			T14	1		T107	1		T108	41
true	1980	1			T4	2		T5	1		T6	5

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	46	1			T15	1		T214	1		T215	2
others[1]	36	1			T7	1		T15	1		T96	2
others[2]	39	1			T7	1		T15	1		T16	1
others[3]	41	1			T11	1		T15	1		T16	1
others[4]	44	1			T7	2		T11	2		T213	1
others[5]	29	1			T15	1		T28	1		T221	1
others[6]	41	1			T7	2		T11	1		T15	1
others[7]	54	1			T4	1		T15	2		T12	1
false	10075	1			T14	1		T107	1		T108	41
true	16435	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	90	1			T29	2		T31	2		T88	2
others[1]	72	1			T29	2		T91	2		T96	2
others[2]	80	1			T31	2		T85	2		T91	2
others[3]	66	1			T6	2		T10	2		T85	2
others[4]	80	1			T87	2		T90	2		T95	2
others[5]	80	1			T92	2		T162	2		T143	2
others[6]	78	1			T31	2		T91	2		T231	2
others[7]	72	1			T87	2		T104	2		T91	2
false	6720	1			T14	1		T107	1		T108	41
true	14547	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	76	1			T104	2		T85	2		T96	2
others[1]	64	1			T106	2		T321	2		T164	2
others[2]	76	1			T85	2		T92	2		T96	4
others[3]	82	1			T10	2		T92	2		T165	2
others[4]	78	1			T90	2		T52	4		T166	2
others[5]	54	1			T6	2		T85	2		T62	2
others[6]	86	1			T93	2		T323	2		T52	2
others[7]	76	1			T29	2		T323	2		T52	4
false	6191	1			T14	1		T107	1		T108	41
true	14368	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31	1			T12	1		T28	1		T91	2
others[1]	40	1			T213	1		T214	1		T321	2
others[2]	38	1			T7	1		T15	1		T28	2
others[3]	34	1			T7	1		T11	1		T28	1
others[4]	34	1			T7	1		T11	1		T214	1
others[5]	36	1			T11	1		T28	2		T213	1
others[6]	36	1			T4	1		T11	1		T15	1
others[7]	38	1			T12	1		T332	1		T214	2
false	10021	1			T14	1		T107	1		T108	41
true	16385	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	60	1			T30	2		T92	2		T96	2
others[1]	62	1			T85	2		T179	2		T333	2
others[2]	92	1			T31	2		T89	2		T163	2
others[3]	82	1			T87	4		T96	4		T44	2
others[4]	60	1			T25	2		T164	2		T326	2
others[5]	100	1			T87	2		T96	2		T162	4
others[6]	72	1			T106	2		T96	4		T148	2
others[7]	76	1			T89	2		T326	2		T328	2
false	6918	1			T14	1		T107	1		T108	41
true	14530	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	64	1			T166	2		T326	2		T179	2
others[1]	66	1			T88	2		T85	2		T91	4
others[2]	56	1			T30	2		T87	2		T95	2
others[3]	86	1			T31	2		T87	2		T85	2
others[4]	82	1			T87	2		T85	2		T321	2
others[5]	54	1			T92	2		T326	2		T334	2
others[6]	66	1			T90	2		T93	2		T94	2
others[7]	98	1			T85	2		T92	2		T96	2
false	6450	1			T14	1		T107	1		T108	41
true	14386	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	68	1			T10	2		T30	2		T104	2
others[1]	54	1			T10	2		T106	2		T323	2
others[2]	78	1			T10	2		T88	4		T91	2
others[3]	66	1			T90	2		T96	2		T335	2
others[4]	80	1			T31	2		T91	2		T95	2
others[5]	82	1			T87	2		T92	4		T96	2
others[6]	100	1			T89	2		T85	2		T91	2
others[7]	88	1			T6	2		T88	2		T85	2
false	6450	1			T14	1		T107	1		T108	41
true	14386	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	64	1			T96	2		T52	2		T326	2
others[1]	54	1			T89	2		T85	2		T162	2
others[2]	68	1			T162	2		T32	2		T326	2
others[3]	80	1			T30	2		T85	2		T33	2
others[4]	86	1			T29	2		T91	4		T93	2
others[5]	60	1			T6	2		T321	2		T325	4
others[6]	62	1			T31	2		T326	4		T179	2
others[7]	72	1			T162	2		T321	4		T148	2
false	5875	1			T14	1		T107	1		T108	41
true	14359	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	66	1			T162	2		T326	2		T179	2
others[1]	72	1			T87	2		T85	2		T96	2
others[2]	58	1			T10	2		T321	4		T165	2
others[3]	86	1			T92	2		T105	2		T162	2
others[4]	88	1			T6	2		T87	2		T91	2
others[5]	82	1			T87	2		T89	2		T95	2
others[6]	74	1			T89	2		T321	2		T322	2
others[7]	84	1			T30	2		T85	2		T106	2
false	5875	1			T14	1		T107	1		T108	41
true	14359	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	48	1			T329	2		T336	2		T337	2
others[1]	30	1			T163	2		T52	4		T338	2
others[2]	44	1			T326	2		T179	2		T325	2
others[3]	38	1			T33	2		T326	4		T324	2
others[4]	42	1			T323	2		T52	2		T165	2
others[5]	54	1			T88	2		T92	2		T321	4
others[6]	40	1			T31	2		T89	2		T90	2
others[7]	46	1			T89	2		T92	2		T326	4
false	6193	1			T14	1		T107	1		T108	41
true	15630	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	56	1			T106	2		T325	4		T182	2
others[1]	52	1			T162	2		T44	2		T326	4
others[2]	32	1			T91	2		T105	2		T325	2
others[3]	48	1			T30	2		T87	2		T323	2
others[4]	60	1			T29	2		T85	4		T95	2
others[5]	42	1			T31	2		T85	2		T179	2
others[6]	54	1			T88	2		T52	2		T164	4
others[7]	68	1			T85	2		T96	2		T179	2
false	6193	1			T14	1		T107	1		T108	41
true	15630	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	42	1			T15	1		T28	2		T104	2
others[1]	50	1			T28	2		T332	1		T213	2
others[2]	38	1			T11	2		T12	1		T28	1
others[3]	34	1			T11	1		T339	1		T295	2
others[4]	25	1			T11	1		T16	1		T214	1
others[5]	36	1			T4	1		T7	1		T16	1
others[6]	35	1			T11	1		T28	2		T340	1
others[7]	40	1			T16	1		T12	1		T28	1
false	10155	1			T14	1		T107	1		T108	41
true	16519	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	28	1			T10	2		T165	2		T326	4
others[1]	24	1			T161	2		T326	2		T341	2
others[2]	40	1			T87	2		T106	2		T165	2
others[3]	16	1			T324	2		T336	2		T331	2
others[4]	38	1			T10	2		T164	2		T326	2
others[5]	30	1			T163	2		T164	4		T148	2
others[6]	26	1			T29	2		T87	2		T326	2
others[7]	36	1			T31	4		T326	4		T325	2
false	8991	1			T14	1		T107	1		T108	41
true	14652	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35	1			T15	1		T28	2		T215	1
others[1]	44	1			T4	1		T11	1		T28	1
others[2]	34	1			T332	1		T342	1		T223	1
others[3]	38	1			T15	1		T91	2		T213	1
others[4]	47	1			T11	2		T213	1		T214	1
others[5]	25	1			T7	1		T332	1		T214	1
others[6]	34	1			T12	1		T326	2		T295	1
others[7]	31	1			T7	2		T11	1		T12	1
false	12354	1			T14	1		T107	1		T108	41
true	1975	1			T4	2		T5	2		T6	4

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	46	1			T89	2		T162	2		T52	2
others[1]	44	1			T31	2		T179	2		T324	2
others[2]	46	1			T326	2		T328	2		T333	2
others[3]	22	1			T323	2		T343	2		T344	2
others[4]	32	1			T92	4		T321	2		T179	2
others[5]	40	1			T33	2		T165	2		T338	2
others[6]	54	1			T163	2		T33	2		T326	4
others[7]	58	1			T88	2		T89	2		T90	2
false	12282	1			T14	1		T107	1		T108	41
true	14599	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	42	1			T31	2		T106	2		T96	2
others[1]	50	1			T85	4		T326	2		T345	2
others[2]	42	1			T95	2		T321	2		T346	2
others[3]	66	1			T29	2		T85	2		T326	2
others[4]	56	1			T30	2		T87	2		T105	2
others[5]	48	1			T85	2		T52	2		T164	2
others[6]	44	1			T323	2		T44	2		T33	2
others[7]	64	1			T88	2		T91	2		T162	2
false	12282	1			T14	1		T107	1		T108	41
true	14567	1			T14	1		T107	1		T108	41

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34	1			T12	1		T28	2		T213	1
others[1]	29	1			T11	1		T16	1		T339	1
others[2]	40	1			T11	1		T28	1		T104	2
others[3]	51	1			T11	2		T12	1		T332	1
others[4]	32	1			T11	1		T215	1		T326	4
others[5]	24	1			T4	1		T28	1		T347	1
others[6]	36	1			T7	1		T15	1		T16	1
others[7]	55	1			T16	1		T28	4		T213	1
false	12354	1			T14	1		T107	1		T108	41
true	2001	1			T4	2		T5	1		T6	5