Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	80.95	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]	71.43	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	85.71	1	100	1	64	64

---

Group Instance : unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	2	5	71.43

Variables for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	2	5	71.43	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	2	5	71.43

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
ecc_uncorr_err	0	1	1
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	99878	1			T3	1		T5	45		T9	389
check_fail	6	1			T119	1		T120	1		T121	1
access_err	63517	1			T4	422		T5	6		T6	120
ecc_corr_err	1395	1			T5	4		T86	3		T113	39
no_err	333279	1			T4	754		T5	187		T6	558

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	99447	1			T5	45		T9	389		T97	765
check_fail	8	1			T123	1		T120	1		T127	1
access_err	61900	1			T4	327		T6	140		T7	628
ecc_uncorr_err	440	1			T99	1		T102	1		T125	1
ecc_corr_err	957	1			T5	32		T93	7		T52	14
no_err	335334	1			T4	849		T5	165		T6	538

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	99370	1			T5	31		T9	389		T97	765
check_fail	7	1			T123	1		T119	1		T120	1
access_err	61946	1			T4	435		T6	65		T7	436
ecc_uncorr_err	527	1			T1	1		T5	14		T118	1
ecc_corr_err	826	1			T113	38		T93	44		T44	29
no_err	335419	1			T4	741		T5	197		T6	613