Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7992470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14757962

1

T107

57

T108

574

T109

490

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6963276	1			T14	1		T107	24		T108	228
values[0x0]	6013947	1			T107	25		T108	283		T109	167
values[0x1]	9773209	1			T107	33		T108	294		T109	143

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4144149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18606283

1

T107

65

T108

646

T109

490

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87354	1			T109	1		T171	4		T172	3
valid_sources[0x01]	87620	1			T108	1		T109	2		T175	1
valid_sources[0x02]	83724	1			T108	6		T109	3		T167	2
valid_sources[0x03]	105929	1			T107	1		T108	8		T109	3
valid_sources[0x04]	88842	1			T108	4		T109	2		T171	1
valid_sources[0x05]	89706	1			T108	6		T109	1		T173	2
valid_sources[0x06]	85728	1			T108	2		T109	3		T169	1
valid_sources[0x07]	90898	1			T109	1		T169	1		T211	5
valid_sources[0x08]	87835	1			T108	6		T171	2		T177	1
valid_sources[0x09]	85742	1			T108	8		T171	4		T209	2
valid_sources[0x0a]	82601	1			T108	2		T109	2		T171	1
valid_sources[0x0b]	89465	1			T108	4		T109	2		T167	3
valid_sources[0x0c]	106222	1			T107	1		T108	3		T109	2
valid_sources[0x0d]	89687	1			T171	2		T170	2		T173	1
valid_sources[0x0e]	90838	1			T209	1		T173	4		T211	6
valid_sources[0x0f]	90201	1			T107	1		T108	4		T169	3
valid_sources[0x10]	83560	1			T109	3		T169	1		T176	4
valid_sources[0x11]	91890	1			T108	2		T109	1		T169	1
valid_sources[0x12]	84942	1			T108	5		T169	1		T171	4
valid_sources[0x13]	93956	1			T108	8		T109	6		T169	4
valid_sources[0x14]	106198	1			T108	4		T109	2		T171	3
valid_sources[0x15]	86872	1			T108	2		T169	10		T171	1
valid_sources[0x16]	86829	1			T108	2		T171	7		T173	1
valid_sources[0x17]	83374	1			T108	2		T109	2		T173	6
valid_sources[0x18]	89259	1			T107	1		T108	4		T109	1
valid_sources[0x19]	88547	1			T108	2		T109	1		T111	2
valid_sources[0x1a]	85344	1			T107	1		T108	4		T109	1
valid_sources[0x1b]	87460	1			T108	2		T109	1		T171	2
valid_sources[0x1c]	92485	1			T108	2		T109	2		T171	1
valid_sources[0x1d]	87909	1			T108	4		T109	1		T169	1
valid_sources[0x1e]	91840	1			T107	1		T108	3		T171	6
valid_sources[0x1f]	88138	1			T109	5		T169	3		T171	2
valid_sources[0x20]	87379	1			T108	3		T109	2		T171	2
valid_sources[0x21]	90344	1			T108	4		T109	1		T167	4
valid_sources[0x22]	116021	1			T108	3		T109	2		T175	1
valid_sources[0x23]	140513	1			T108	5		T109	3		T168	1
valid_sources[0x24]	86654	1			T108	1		T109	1		T171	1
valid_sources[0x25]	84745	1			T108	8		T109	2		T169	1
valid_sources[0x26]	89085	1			T108	3		T109	2		T173	2
valid_sources[0x27]	88295	1			T108	3		T111	2		T171	3
valid_sources[0x28]	89288	1			T107	1		T108	3		T172	1
valid_sources[0x29]	89112	1			T108	6		T109	3		T171	3
valid_sources[0x2a]	85827	1			T108	3		T109	1		T169	1
valid_sources[0x2b]	92512	1			T107	1		T108	1		T109	1
valid_sources[0x2c]	92797	1			T107	1		T109	1		T171	2
valid_sources[0x2d]	83653	1			T108	3		T109	1		T171	1
valid_sources[0x2e]	91086	1			T108	3		T109	4		T169	1
valid_sources[0x2f]	86380	1			T108	4		T109	1		T169	2
valid_sources[0x30]	84916	1			T108	4		T109	3		T171	1
valid_sources[0x31]	95560	1			T108	1		T109	2		T167	2
valid_sources[0x32]	87039	1			T107	1		T109	2		T171	4
valid_sources[0x33]	89133	1			T108	2		T109	3		T171	3
valid_sources[0x34]	87564	1			T108	4		T109	3		T171	2
valid_sources[0x35]	82920	1			T107	2		T108	3		T210	2
valid_sources[0x36]	85881	1			T108	1		T176	21		T173	2
valid_sources[0x37]	85176	1			T109	1		T171	3		T210	2
valid_sources[0x38]	84647	1			T108	4		T109	2		T171	1
valid_sources[0x39]	91171	1			T108	2		T109	2		T209	2
valid_sources[0x3a]	84431	1			T109	3		T167	1		T169	1
valid_sources[0x3b]	86269	1			T108	2		T109	4		T171	1
valid_sources[0x3c]	84122	1			T108	4		T171	2		T176	7
valid_sources[0x3d]	86669	1			T107	1		T108	2		T109	2
valid_sources[0x3e]	92336	1			T108	3		T169	2		T171	4
valid_sources[0x3f]	89127	1			T108	2		T109	3		T171	1
valid_sources[0x40]	84450	1			T108	9		T109	1		T171	4
valid_sources[0x41]	90163	1			T107	1		T108	5		T109	1
valid_sources[0x42]	87607	1			T108	3		T109	2		T169	1
valid_sources[0x43]	128567	1			T108	5		T109	2		T270	1
valid_sources[0x44]	86399	1			T108	2		T109	3		T169	1
valid_sources[0x45]	86285	1			T108	1		T109	2		T169	2
valid_sources[0x46]	90178	1			T108	4		T109	1		T171	2
valid_sources[0x47]	84965	1			T108	5		T109	2		T171	2
valid_sources[0x48]	85976	1			T109	2		T169	2		T110	21
valid_sources[0x49]	84168	1			T108	7		T109	6		T111	1
valid_sources[0x4a]	87445	1			T108	9		T109	1		T111	2
valid_sources[0x4b]	89866	1			T108	3		T109	6		T171	2
valid_sources[0x4c]	88160	1			T107	2		T108	3		T109	2
valid_sources[0x4d]	89300	1			T108	5		T109	2		T169	1
valid_sources[0x4e]	85416	1			T108	6		T109	2		T111	1
valid_sources[0x4f]	85184	1			T14	1		T108	2		T109	2
valid_sources[0x50]	88542	1			T107	1		T108	5		T109	7
valid_sources[0x51]	91060	1			T108	9		T109	3		T171	2
valid_sources[0x52]	86534	1			T108	2		T109	2		T171	2
valid_sources[0x53]	91153	1			T107	1		T108	5		T109	3
valid_sources[0x54]	84346	1			T108	2		T109	1		T171	2
valid_sources[0x55]	85552	1			T108	3		T109	2		T169	1
valid_sources[0x56]	88369	1			T107	3		T108	5		T109	3
valid_sources[0x57]	89431	1			T108	2		T109	2		T171	2
valid_sources[0x58]	85267	1			T108	3		T109	3		T171	8
valid_sources[0x59]	93780	1			T108	2		T109	2		T171	4
valid_sources[0x5a]	89634	1			T107	1		T108	2		T109	3
valid_sources[0x5b]	83494	1			T107	1		T108	1		T109	1
valid_sources[0x5c]	88279	1			T107	1		T108	2		T109	1
valid_sources[0x5d]	86674	1			T108	1		T109	2		T169	3
valid_sources[0x5e]	89703	1			T109	1		T169	1		T211	3
valid_sources[0x5f]	88947	1			T108	4		T109	2		T169	1
valid_sources[0x60]	90960	1			T108	2		T171	2		T173	2
valid_sources[0x61]	88386	1			T108	4		T109	1		T167	1
valid_sources[0x62]	94106	1			T108	4		T109	2		T169	1
valid_sources[0x63]	87303	1			T108	1		T109	5		T169	1
valid_sources[0x64]	88606	1			T109	4		T171	3		T170	4
valid_sources[0x65]	83720	1			T108	7		T109	3		T209	3
valid_sources[0x66]	90226	1			T108	5		T109	2		T110	1
valid_sources[0x67]	89638	1			T108	1		T109	2		T169	2
valid_sources[0x68]	84136	1			T170	8		T173	3		T211	4
valid_sources[0x69]	101096	1			T107	2		T108	1		T109	1
valid_sources[0x6a]	88404	1			T107	1		T108	5		T109	1
valid_sources[0x6b]	88531	1			T109	2		T169	2		T209	1
valid_sources[0x6c]	88714	1			T108	5		T109	1		T169	3
valid_sources[0x6d]	89760	1			T108	4		T109	1		T169	2
valid_sources[0x6e]	88473	1			T107	1		T108	6		T109	1
valid_sources[0x6f]	89462	1			T108	5		T109	1		T171	3
valid_sources[0x70]	85705	1			T109	3		T171	8		T170	6
valid_sources[0x71]	97082	1			T108	4		T109	1		T171	1
valid_sources[0x72]	88052	1			T108	3		T109	1		T169	2
valid_sources[0x73]	90604	1			T108	7		T169	1		T209	3
valid_sources[0x74]	84853	1			T108	3		T171	7		T209	3
valid_sources[0x75]	89013	1			T108	2		T109	3		T211	5
valid_sources[0x76]	88446	1			T108	5		T109	3		T171	1
valid_sources[0x77]	89930	1			T108	5		T109	1		T169	2
valid_sources[0x78]	99850	1			T107	1		T109	6		T209	2
valid_sources[0x79]	85455	1			T108	4		T109	2		T169	1
valid_sources[0x7a]	90238	1			T107	1		T108	2		T109	3
valid_sources[0x7b]	86095	1			T107	3		T108	1		T109	3
valid_sources[0x7c]	84277	1			T108	2		T109	2		T169	4
valid_sources[0x7d]	87562	1			T108	3		T109	1		T171	3
valid_sources[0x7e]	90111	1			T107	2		T108	1		T109	3
valid_sources[0x7f]	85776	1			T107	1		T108	3		T109	3
valid_sources[0x80]	84381	1			T109	1		T169	4		T170	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4043165

1

T107

9

T108

82

T109

180

values[0x0]

all_enables

biggest_size

5391027

1

T107

19

T108

254

T109

167

values[0x1]

all_enables

biggest_size

5323770

1

T107

29

T108

238

T109

143

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	746537	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27682475

1

T107

13

T108

164

T109

146

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6972412	1			T107	53		T108	466		T109	78
values[0x0]	10413992	1			T107	3		T108	74		T109	29
values[0x1]	11042608	1			T107	12		T108	93		T109	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28171917

1

T107

35

T108

354

T109

146

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	113601	1			T108	3		T170	1		T4	2149
valid_sources[0x01]	113099	1			T108	2		T171	23		T170	1
valid_sources[0x02]	109011	1			T108	4		T109	1		T211	3
valid_sources[0x03]	110300	1			T108	3		T109	2		T211	2
valid_sources[0x04]	112338	1			T108	1		T109	1		T176	1
valid_sources[0x05]	111615	1			T108	4		T109	2		T168	3
valid_sources[0x06]	108325	1			T108	6		T211	2		T4	1779
valid_sources[0x07]	111094	1			T108	1		T168	2		T211	5
valid_sources[0x08]	108392	1			T108	4		T170	1		T211	11
valid_sources[0x09]	112826	1			T108	3		T210	15		T211	11
valid_sources[0x0a]	109338	1			T107	9		T108	3		T109	1
valid_sources[0x0b]	111702	1			T108	4		T109	2		T170	1
valid_sources[0x0c]	108699	1			T108	1		T4	1615		T5	1
valid_sources[0x0d]	109119	1			T108	1		T176	2		T211	1
valid_sources[0x0e]	108795	1			T108	5		T109	1		T211	3
valid_sources[0x0f]	110685	1			T108	2		T109	1		T168	2
valid_sources[0x10]	111395	1			T174	1		T4	1852		T7	804
valid_sources[0x11]	109729	1			T174	1		T4	1709		T6	1
valid_sources[0x12]	110353	1			T108	3		T172	4		T209	3
valid_sources[0x13]	112141	1			T108	1		T109	1		T168	5
valid_sources[0x14]	110499	1			T107	4		T108	4		T109	3
valid_sources[0x15]	114499	1			T168	1		T211	1		T4	2105
valid_sources[0x16]	110488	1			T107	9		T108	1		T109	1
valid_sources[0x17]	112967	1			T108	2		T211	1		T4	1829
valid_sources[0x18]	109762	1			T108	2		T168	2		T176	8
valid_sources[0x19]	111441	1			T109	1		T211	1		T174	1
valid_sources[0x1a]	112353	1			T108	3		T170	1		T173	49
valid_sources[0x1b]	111679	1			T108	6		T211	1		T4	2228
valid_sources[0x1c]	112542	1			T109	1		T211	1		T212	25
valid_sources[0x1d]	111121	1			T108	6		T209	1		T4	1564
valid_sources[0x1e]	108770	1			T108	6		T109	1		T170	1
valid_sources[0x1f]	109072	1			T108	2		T109	1		T174	1
valid_sources[0x20]	109236	1			T108	2		T211	14		T4	1563
valid_sources[0x21]	110405	1			T108	4		T168	2		T211	3
valid_sources[0x22]	108607	1			T108	2		T211	5		T4	1677
valid_sources[0x23]	111905	1			T108	1		T109	2		T168	1
valid_sources[0x24]	108521	1			T108	4		T211	1		T4	2250
valid_sources[0x25]	110954	1			T172	4		T174	1		T4	2099
valid_sources[0x26]	112618	1			T108	6		T211	5		T4	1465
valid_sources[0x27]	110677	1			T108	3		T109	1		T173	5
valid_sources[0x28]	110403	1			T109	2		T170	2		T211	2
valid_sources[0x29]	112009	1			T108	3		T109	2		T211	2
valid_sources[0x2a]	110195	1			T109	1		T168	2		T211	1
valid_sources[0x2b]	112728	1			T108	2		T211	5		T174	1
valid_sources[0x2c]	110716	1			T109	1		T168	1		T170	1
valid_sources[0x2d]	109706	1			T108	4		T168	2		T209	3
valid_sources[0x2e]	111757	1			T108	3		T211	1		T4	1995
valid_sources[0x2f]	113904	1			T108	3		T168	3		T173	2
valid_sources[0x30]	112595	1			T108	3		T168	2		T209	1
valid_sources[0x31]	111414	1			T108	2		T168	3		T4	1980
valid_sources[0x32]	111249	1			T108	6		T176	1		T211	1
valid_sources[0x33]	111394	1			T108	10		T211	8		T4	1670
valid_sources[0x34]	110018	1			T108	4		T109	1		T168	2
valid_sources[0x35]	112392	1			T108	6		T109	1		T4	1971
valid_sources[0x36]	112211	1			T109	1		T168	1		T170	1
valid_sources[0x37]	113314	1			T108	5		T168	1		T4	2039
valid_sources[0x38]	108931	1			T108	3		T109	1		T211	3
valid_sources[0x39]	110603	1			T108	1		T168	1		T4	1457
valid_sources[0x3a]	109524	1			T108	2		T109	2		T168	1
valid_sources[0x3b]	110425	1			T170	2		T4	1819		T5	2
valid_sources[0x3c]	109913	1			T108	1		T170	1		T4	1763
valid_sources[0x3d]	114691	1			T108	4		T109	1		T168	1
valid_sources[0x3e]	111840	1			T108	9		T211	5		T4	2098
valid_sources[0x3f]	113120	1			T108	2		T170	1		T176	4
valid_sources[0x40]	110398	1			T108	2		T170	1		T211	6
valid_sources[0x41]	109652	1			T108	2		T170	2		T173	7
valid_sources[0x42]	110870	1			T108	5		T109	2		T168	1
valid_sources[0x43]	110107	1			T108	1		T109	2		T168	1
valid_sources[0x44]	110141	1			T108	3		T168	2		T170	3
valid_sources[0x45]	112258	1			T109	2		T211	4		T4	2190
valid_sources[0x46]	109613	1			T108	3		T171	5		T170	1
valid_sources[0x47]	111649	1			T108	3		T168	1		T176	4
valid_sources[0x48]	111384	1			T108	2		T109	1		T168	1
valid_sources[0x49]	112410	1			T107	2		T108	2		T209	1
valid_sources[0x4a]	111816	1			T108	4		T174	1		T4	1965
valid_sources[0x4b]	108797	1			T108	2		T170	1		T211	1
valid_sources[0x4c]	110933	1			T109	1		T168	1		T4	1992
valid_sources[0x4d]	108423	1			T108	1		T168	2		T170	1
valid_sources[0x4e]	109958	1			T108	3		T211	1		T174	1
valid_sources[0x4f]	107318	1			T108	1		T211	2		T4	1282
valid_sources[0x50]	111445	1			T108	4		T211	1		T4	2230
valid_sources[0x51]	110851	1			T108	5		T170	1		T209	4
valid_sources[0x52]	108650	1			T108	7		T109	2		T170	1
valid_sources[0x53]	111044	1			T108	3		T109	1		T174	1
valid_sources[0x54]	112867	1			T108	2		T211	7		T174	3
valid_sources[0x55]	112202	1			T109	1		T172	1		T211	9
valid_sources[0x56]	109380	1			T167	4		T168	2		T170	1
valid_sources[0x57]	111555	1			T108	6		T211	3		T4	1595
valid_sources[0x58]	110550	1			T108	3		T168	1		T170	1
valid_sources[0x59]	109312	1			T108	2		T4	2103		T7	755
valid_sources[0x5a]	111091	1			T107	13		T108	1		T4	1460
valid_sources[0x5b]	111992	1			T108	1		T170	1		T172	9
valid_sources[0x5c]	111463	1			T108	4		T168	1		T173	17
valid_sources[0x5d]	113303	1			T108	2		T171	15		T170	1
valid_sources[0x5e]	110442	1			T108	3		T170	1		T4	2480
valid_sources[0x5f]	109570	1			T109	1		T4	1922		T5	1
valid_sources[0x60]	109705	1			T108	1		T168	1		T170	1
valid_sources[0x61]	111162	1			T108	2		T4	1846		T7	794
valid_sources[0x62]	111188	1			T108	5		T168	2		T170	1
valid_sources[0x63]	111392	1			T108	1		T109	1		T168	1
valid_sources[0x64]	112459	1			T108	6		T4	2069		T7	877
valid_sources[0x65]	110584	1			T108	2		T109	2		T173	22
valid_sources[0x66]	109432	1			T108	4		T109	2		T176	5
valid_sources[0x67]	110713	1			T108	3		T109	2		T211	1
valid_sources[0x68]	110766	1			T108	1		T171	18		T211	3
valid_sources[0x69]	112433	1			T108	2		T171	16		T170	2
valid_sources[0x6a]	111986	1			T108	2		T174	1		T4	1900
valid_sources[0x6b]	109649	1			T108	2		T109	1		T170	1
valid_sources[0x6c]	108270	1			T170	1		T211	5		T174	1
valid_sources[0x6d]	112077	1			T108	2		T109	1		T168	2
valid_sources[0x6e]	111827	1			T107	5		T108	2		T172	10
valid_sources[0x6f]	114747	1			T108	3		T168	3		T172	1
valid_sources[0x70]	110833	1			T108	4		T109	1		T169	9
valid_sources[0x71]	110277	1			T108	3		T4	1614		T5	1
valid_sources[0x72]	111529	1			T108	3		T109	1		T170	1
valid_sources[0x73]	112042	1			T108	8		T109	1		T170	1
valid_sources[0x74]	109595	1			T108	2		T168	2		T176	2
valid_sources[0x75]	109951	1			T108	3		T168	1		T211	9
valid_sources[0x76]	110278	1			T108	3		T109	1		T176	1
valid_sources[0x77]	110111	1			T108	1		T109	1		T168	2
valid_sources[0x78]	112213	1			T171	9		T176	9		T209	2
valid_sources[0x79]	111543	1			T108	4		T109	1		T168	1
valid_sources[0x7a]	115923	1			T108	2		T109	1		T171	1
valid_sources[0x7b]	111336	1			T107	3		T108	1		T109	1
valid_sources[0x7c]	111122	1			T108	2		T109	2		T211	4
valid_sources[0x7d]	110505	1			T108	1		T109	1		T168	1
valid_sources[0x7e]	111681	1			T108	3		T170	1		T209	2
valid_sources[0x7f]	112099	1			T108	3		T109	2		T176	1
valid_sources[0x80]	110529	1			T108	2		T168	3		T211	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6960206

1

T107

4

T108

44

T109

78

values[0x0]

all_enables

biggest_size

10362262

1

T107

3

T108

57

T109

29

values[0x1]

all_enables

biggest_size

10360007

1

T107

6

T108

63

T109

39