Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

60924334

1

T14

1

T107

25

T108

234

full_word

18207443

1

T107

57

T108

575

T109

490

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	79131507	1			T14	1		T107	82		T108	789
auto[TlIntgErrCmd]	88	1			T108	8		T206	3		T207	6
auto[TlIntgErrData]	96	1			T108	7		T206	2		T207	5
auto[TlIntgErrBoth]	86	1			T108	5		T206	5		T207	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11104007

1

T14

1

T107

24

T108

229

auto[1]

68027770

1

T107

58

T108

580

T109

310

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6641249	1			T14	1		T107	15		T108	139
auto[TlIntgErrNone]	partial	auto[1]	54282836	1			T107	10		T108	79		T167	2
auto[TlIntgErrNone]	full_word	auto[0]	4462638	1			T107	9		T108	81		T109	180
auto[TlIntgErrNone]	full_word	auto[1]	13744784	1			T107	48		T108	490		T109	310
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T108	4		T206	1		T207	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T108	3		T206	2		T207	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T304	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T108	1		T208	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T108	3		T206	1		T207	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T108	3		T207	2		T208	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T108	1		T206	1		T301	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T301	1		T304	1		T305	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T108	1		T206	3		T207	4
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T108	2		T206	2		T207	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T306	1		T301	1		T305	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T108	2		T207	1		T303	3