Unified Coverage Report :: Module :: prim_secded_inv_72_64_enc

Module : prim_secded_inv_72_64_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
data_o[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
data_o[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
data_o[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.u_prim_secded_inv_72_64_enc

	Total	Covered	Percent
Totals	2	2	100.00
Total Bits	272	272	100.00
Total Bits 0->1	136	136	100.00
Total Bits 1->0	136	136	100.00

Ports	2	2	100.00
Port Bits	272	272	100.00
Port Bits 0->1	136	136	100.00
Port Bits 1->0	136	136	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
data_o[71:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT