Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.98	97.18	88.57	97.19		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2115905771	19539821	0	0
check_regwen_rd_A	2115905771	5064	0	0
check_timeout_rd_A	2115905771	4902	0	0
check_trigger_regwen_rd_A	2115905771	4950	0	0
consistency_check_period_rd_A	2115905771	5684	0	0
creator_sw_cfg_read_lock_rd_A	2115905771	4788	0	0
direct_access_address_rd_A	2115905771	4531	0	0
direct_access_wdata_0_rd_A	2115905771	3235	0	0
direct_access_wdata_1_rd_A	2115905771	3874	0	0
integrity_check_period_rd_A	2115905771	5073	0	0
intr_enable_rd_A	2115905771	5425	0	0
owner_sw_cfg_read_lock_rd_A	2115905771	4597	0	0
vendor_test_read_lock_rd_A	2115905771	4279	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	19539821	0	0
T4	0	339583	0	0
T7	0	129930	0	0
T11	0	510597	0	0
T108	121045	3	0	0
T109	7775	0	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	0	0	0
T168	6723	78	0	0
T169	7444	63	0	0
T170	10133	70	0	0
T171	11726	0	0	0
T172	0	77	0	0
T173	0	447	0	0
T174	0	23	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	5064	0	0
T7	0	96	0	0
T11	0	313	0	0
T12	0	111	0	0
T109	7775	52	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	2	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	54	0	0
T174	0	12	0	0
T175	3480	0	0	0
T213	0	387	0	0
T219	0	244	0	0
T221	0	43	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	4902	0	0
T7	0	76	0	0
T11	0	307	0	0
T12	0	146	0	0
T109	7775	13	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	8	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	27	0	0
T174	0	1	0	0
T175	3480	0	0	0
T213	0	351	0	0
T219	0	335	0	0
T221	0	84	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	4950	0	0
T7	0	52	0	0
T11	0	257	0	0
T12	0	80	0	0
T109	7775	31	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	6	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	11	0	0
T175	3480	0	0	0
T213	0	303	0	0
T219	0	372	0	0
T221	0	43	0	0
T222	0	171	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	5684	0	0
T7	0	91	0	0
T11	0	422	0	0
T12	0	140	0	0
T109	7775	29	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	4	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	15	0	0
T174	0	7	0	0
T175	3480	0	0	0
T213	0	418	0	0
T219	0	368	0	0
T221	0	62	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	4788	0	0
T7	0	53	0	0
T11	0	329	0	0
T12	0	83	0	0
T109	7775	38	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	4	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	13	0	0
T174	0	1	0	0
T175	3480	0	0	0
T213	0	400	0	0
T219	0	275	0	0
T221	0	60	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	4531	0	0
T7	0	75	0	0
T11	0	368	0	0
T12	0	69	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	1	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	0	0	0
T174	0	7	0	0
T175	3480	0	0	0
T176	4132	0	0	0
T213	0	433	0	0
T219	0	319	0	0
T221	0	77	0	0
T222	0	223	0	0
T271	0	73	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	3235	0	0
T7	107806	36	0	0
T8	19001	0	0	0
T9	31345	0	0	0
T10	47178	0	0	0
T11	0	234	0	0
T12	0	94	0	0
T29	49609	0	0	0
T38	23629	0	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T99	18996	0	0	0
T158	12417	0	0	0
T213	0	232	0	0
T219	0	280	0	0
T221	0	43	0	0
T222	0	189	0	0
T271	0	31	0	0
T272	0	174	0	0
T273	0	190	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	3874	0	0
T7	107806	27	0	0
T8	19001	0	0	0
T9	31345	0	0	0
T10	47178	0	0	0
T11	0	363	0	0
T12	0	116	0	0
T29	49609	0	0	0
T38	23629	0	0	0
T97	18654	0	0	0
T98	11848	0	0	0
T99	18996	0	0	0
T158	12417	0	0	0
T213	0	306	0	0
T219	0	250	0	0
T221	0	71	0	0
T222	0	159	0	0
T271	0	74	0	0
T272	0	177	0	0
T273	0	218	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	5073	0	0
T7	0	91	0	0
T11	0	333	0	0
T12	0	85	0	0
T109	7775	40	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	1	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	53	0	0
T174	0	10	0	0
T175	3480	0	0	0
T213	0	463	0	0
T219	0	160	0	0
T221	0	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	5425	0	0
T7	0	61	0	0
T11	0	265	0	0
T12	0	101	0	0
T109	7775	14	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	9	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	18	0	0
T174	0	9	0	0
T175	3480	0	0	0
T213	0	365	0	0
T274	0	9	0	0
T275	0	39	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	4597	0	0
T7	0	51	0	0
T11	0	266	0	0
T12	0	142	0	0
T109	7775	43	0	0
T110	3373	0	0	0
T111	3446	0	0	0
T112	3630	0	0	0
T167	6208	4	0	0
T168	6723	0	0	0
T169	7444	0	0	0
T170	10133	0	0	0
T171	11726	13	0	0
T174	0	3	0	0
T175	3480	0	0	0
T213	0	427	0	0
T219	0	327	0	0
T221	0	63	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2115905771	4279	0	0
T7	0	75	0	0
T11	0	292	0	0
T12	0	161	0	0
T170	10133	0	0	0
T171	11726	30	0	0
T172	9342	0	0	0
T174	0	3	0	0
T175	3480	0	0	0
T176	4132	0	0	0
T177	3520	0	0	0
T209	4186	0	0	0
T210	3873	0	0	0
T213	0	360	0	0
T219	0	358	0	0
T221	0	53	0	0
T222	0	189	0	0
T270	3748	0	0	0
T271	0	43	0	0
T276	3450	0	0	0