Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.92	71.76	78.57		95.24	72.22	81.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.76	71.86	77.42	72.11	95.24	76.56	85.37

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.98	97.18	88.57	97.19		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_otp_ctrl_ecc_reg	87.71	100.00	66.67	71.90		100.00	100.00
u_prim_count	100.00			100.00
u_prim_mubi8_sender_read_lock_pre	79.17	37.50				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	79.17	37.50				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		131	94	71.76
CONT_ASSIGN	182	1	1	100.00
ALWAYS	190	111	77	69.37
CONT_ASSIGN	633	1	0	0.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	652	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	678	1	1	100.00
CONT_ASSIGN	721	1	0	0.00
CONT_ASSIGN	741	1	0	0.00
ALWAYS	748	3	3	100.00
ALWAYS	751	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
190	1	1
193	1	1
196	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
217	1	1
218	1	1
221	1	1
222	1	1
224	1	1
229	1	1
230	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
			MISSING_ELSE
249	1	1
250	1	1
253	1	1
258	1	1
259	1	1
262	1	1
263		unreachable
265	1	1
266	1	1
273	1	1
274	1	1
			MISSING_ELSE
277	1	1
278	1	1
			MISSING_ELSE
289	0	1
290	0	1
291	0	1
292	0	1
293	0	1
294		unreachable
			==> MISSING_ELSE
302	0	1
303	0	1
304	0	1
305	0	1
306		unreachable
307		unreachable
308		unreachable
			==> MISSING_ELSE
315	1	1
316	1	1
317		unreachable
322	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
334	1	1
339	1	1
340		unreachable
			MISSING_ELSE
342	1	1
343	1	1
			MISSING_ELSE
353	1	1
356	1	1
360	1	1
362		unreachable
363		unreachable
364		unreachable
367		unreachable
368		unreachable
370		unreachable
375	1	1
379	1	1
380	1	1
381	1	1
384	1	1
385	1	1
388	1	1
389	1	1
391	1	1
399	1	1
400	1	1
			MISSING_ELSE
403	1	1
404	1	1
406	1	1
			MISSING_ELSE
415	1	1
416		unreachable
417		unreachable
418		unreachable
421		unreachable
422		unreachable
423		unreachable
424		unreachable
425		unreachable
			==> MISSING_ELSE
430		unreachable
431		unreachable
432		unreachable
			==> MISSING_ELSE
441	1	1
442	1	1
443	1	1
			==> MISSING_ELSE
453	0	1
454	0	1
455	0	1
456	0	1
457	0	1
458		unreachable
			==> MISSING_ELSE
465	0	1
466	0	1
467	0	1
468		unreachable
			==> MISSING_ELSE
478	0	1
479	0	1
480	0	1
481		unreachable
483		unreachable
487		unreachable
488		unreachable
489		unreachable
491		unreachable
492		unreachable
496		unreachable
497		unreachable
			==> MISSING_ELSE
501		unreachable
502		unreachable
			==> MISSING_ELSE
			==> MISSING_ELSE
514	0	1
515	0	1
516	0	1
517	0	1
518		unreachable
			==> MISSING_ELSE
526	0	1
527	0	1
528	0	1
529	0	1
530		unreachable
			==> MISSING_ELSE
540	0	1
541	0	1
542	0	1
545		unreachable
546		unreachable
549		unreachable
550		unreachable
554		unreachable
558		unreachable
559		unreachable
561		unreachable
			==> MISSING_ELSE
570	1	1
571	1	1
572	1	1
			MISSING_ELSE
576	1	1
577	1	1
593	1	1
594	0	1
595	0	1
596	0	1
			==> MISSING_ELSE
			MISSING_ELSE
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
			MISSING_ELSE
			MISSING_ELSE
633	0	1
638	1	1
639	1	1
643	1	1
650	1	1
652	1	1
673	1	1
676	1	1
678	1	1
721	0	1
741	0	1
748	3	3
751	1	1
752	1	1
754	1	1
756	1	1
757	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Total	Covered	Percent
Conditions	28	22	78.57
Logical	28	22	78.57
Non-Logical	0	0
Event	0	0

 LINE       253
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T40,T41
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       258
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T42,T43

 LINE       293
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       356
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T45
0	1	Covered	T5,T6,T7
1	0	Unreachable

 LINE       362
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       362
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       362
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       379
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       399
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T32,T46,T47

 LINE       424
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       431
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       483
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       545
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       545
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       545
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       571
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T17,T18,T19

 LINE       595
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       603
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T5

 LINE       633
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11110101000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       633
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       652
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       652
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       676
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	16	15	93.75
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyReadSt	325	Covered	T14
CnstyReadWaitSt	343	Covered	T14
ErrorSt	277	Covered	T14
IdleSt	363	Covered	T14
InitDescrSt	263	Excluded
InitDescrWaitSt	294	Excluded
InitSt	230	Covered	T14
InitWaitSt	240	Covered	T14
IntegDigClrSt	259	Covered	T14
IntegDigFinSt	489	Excluded
IntegDigPadSt	491	Excluded
IntegDigSt	432	Excluded
IntegDigWaitSt	530	Excluded
IntegScrSt	425	Excluded
IntegScrWaitSt	458	Excluded
ResetSt	228	Covered	T14

transitions	Line No.	Covered	Tests
CnstyReadSt->CnstyReadWaitSt	343	Covered	T14
CnstyReadSt->ErrorSt	594	Covered	T14
CnstyReadWaitSt->CnstyReadSt	384	Covered	T14
CnstyReadWaitSt->ErrorSt	367	Covered	T14
CnstyReadWaitSt->IdleSt	363	Covered	T14
IdleSt->CnstyReadSt	325	Covered	T14
IdleSt->ErrorSt	594	Covered	T14
IdleSt->IntegDigClrSt	317	Excluded
InitDescrSt->ErrorSt	594	Excluded
InitDescrSt->InitDescrWaitSt	294	Excluded
InitDescrWaitSt->ErrorSt	594	Excluded
InitDescrWaitSt->InitSt	306	Excluded
InitSt->ErrorSt	594	Covered	T14
InitSt->InitWaitSt	240	Covered	T14
InitWaitSt->ErrorSt	277	Covered	T14
InitWaitSt->InitDescrSt	263	Excluded
InitWaitSt->InitSt	265	Covered	T14
InitWaitSt->IntegDigClrSt	259	Covered	T14
IntegDigClrSt->ErrorSt	594	Not Covered
IntegDigClrSt->IdleSt	441	Covered	T14
IntegDigClrSt->IntegDigSt	432	Excluded
IntegDigClrSt->IntegScrSt	425	Excluded
IntegDigFinSt->ErrorSt	594	Excluded
IntegDigFinSt->IntegDigWaitSt	530	Excluded
IntegDigPadSt->ErrorSt	594	Excluded
IntegDigPadSt->IntegDigFinSt	518	Excluded
IntegDigSt->ErrorSt	594	Excluded
IntegDigSt->IntegDigFinSt	489	Excluded
IntegDigSt->IntegDigPadSt	491	Excluded
IntegDigSt->IntegScrSt	502	Excluded
IntegDigWaitSt->ErrorSt	558	Excluded
IntegDigWaitSt->IdleSt	546	Excluded
IntegScrSt->ErrorSt	594	Excluded
IntegScrSt->IntegScrWaitSt	458	Excluded
IntegScrWaitSt->ErrorSt	594	Excluded
IntegScrWaitSt->IntegDigSt	468	Excluded
ResetSt->ErrorSt	594	Covered	T14
ResetSt->InitSt	230	Covered	T14

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	368	Covered	T14
FsmStateError	572	Covered	T14
MacroEccCorrError	274	Covered	T14
NoError	571	Covered	T14

transitions	Line No.	Covered	Tests
CheckFailError->FsmStateError	604	Excluded
CheckFailError->MacroEccCorrError	274	Excluded
FsmStateError->CheckFailError	368	Excluded
FsmStateError->MacroEccCorrError	274	Excluded
MacroEccCorrError->CheckFailError	368	Covered	T14
MacroEccCorrError->FsmStateError	604	Covered	T14
NoError->CheckFailError	368	Covered	T14
NoError->FsmStateError	572	Covered	T14
NoError->MacroEccCorrError	274	Covered	T14

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Line No.	Total	Covered	Percent
Branches		54	39	72.22
TERNARY	633	1	1	100.00
TERNARY	652	2	1	50.00
TERNARY	676	2	2	100.00
CASE	224	40	27	67.50
IF	593	2	1	50.00
IF	600	3	3	100.00
IF	748	2	2	100.00
IF	751	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	633	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Excluded
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	652	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	676	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	case (state_q)
-2-:	229	if (init_req_i)
-3-:	239	if (otp_gnt_i)
-4-:	249	if (otp_rvalid_i)
-5-:	253	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	258	if ((cnt == LastScrmblBlock))
-7-:	262	if (1'b0)
-8-:	273	if ((otp_err_e'(otp_err_i) != NoError))
-9-:	293	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	305	if (scrmbl_valid_i)
-11-:	315	if (integ_chk_req_i)
-12-:	316	if (1'b0)
-13-:	324	if (cnsty_chk_req_i)
-14-:	339	if (1'b0)
-15-:	342	if (otp_gnt_i)
-16-:	353	if (otp_rvalid_i)
-17-:	356	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-18-:	360	if (1'b0)
-19-:	362	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	375	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	379	if ((cnt == LastScrmblBlock))
-22-:	399	if ((otp_err_e'(otp_err_i) != NoError))
-23-:	415	if (1'b0)
-24-:	422	if (1'b0)
-25-:	424	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	431	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	442	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	457	if (scrmbl_ready_i)
-29-:	467	if (scrmbl_valid_i)
-30-:	480	if (scrmbl_ready_i)
-31-:	483	if ((cnt == PenultimateScrmblBlock))
-32-:	487	if (cnt[0])
-33-:	496	if (cnt[0])
-34-:	501	if (1'b0)
-35-:	517	if (scrmbl_ready_i)
-36-:	529	if (scrmbl_ready_i)
-37-:	542	if (scrmbl_valid_i)
-38-:	545	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	549	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	571	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T42,T43
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T40,T41
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T50,T73,T74
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T46,T47
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T45
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T7
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T18,T19
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	593	if (ecc_err)
-2-:	595	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Excluded
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	603	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	748	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	751	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	27	81.82
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	27	81.82

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2113347341	2112599801	0	0
BypassEnable0_A	2113347341	0	0	0
BypassEnable1_A	2113347341	0	0	0
CnstyChkAckKnown_A	2113347341	2112599801	0	0
DataKnown_A	2113347341	2112599801	0	0
DigestKnown_A	2113347341	2112599801	0	0
DigestOffsetMustBeRepresentable_A	1074	1074	0	0
EccErrorState_A	2113347341	0	0	0
ErrorKnown_A	2113347341	2112599801	0	0
InitDoneKnown_A	2113347341	2112599801	0	0
InitReadLocksPartition_A	2113347341	511358902	0	0
InitWriteLocksPartition_A	2113347341	511358902	0	0
IntegChkAckKnown_A	2113347341	2112599801	0	0
OffsetMustBeBlockAligned_A	1074	1074	0	0
OtpAddrKnown_A	2113347341	2112599801	0	0
OtpCmdKnown_A	2113347341	2112599801	0	0
OtpErrorState_A	2113347341	13	0	0
OtpReqKnown_A	2113347341	2112599801	0	0
OtpSizeKnown_A	2113347341	2112599801	0	0
OtpWdataKnown_A	2113347341	2112599801	0	0
ReadLockImpliesDigest_A	2113347341	0	0	0
ReadLockPropagation_A	2113347341	2112599801	0	0
ScrambledImpliesDigest_A	2113347341	0	0	0
ScrmblCmdKnown_A	2113347341	2112599801	0	0
ScrmblDataKnown_A	2113071478	2112323938	0	0
ScrmblModeKnown_A	2113347341	2112599801	0	0
ScrmblMtxReqKnown_A	2113347341	2112599801	0	0
ScrmblSelKnown_A	2113347341	2112599801	0	0
ScrmblValidKnown_A	2113347341	2112599801	0	0
SizeMustBeBlockAligned_A	1074	1074	0	0
WriteLockImpliesDigest_A	2113347341	0	0	0
WriteLockPropagation_A	2113347341	2112599801	0	0
u_state_regs_A	2113347341	2112599801	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

BypassEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

BypassEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

CnstyChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	511358902	0	0
T1	11113	4148	0	0
T2	3878	708	0	0
T3	13890	5233	0	0
T4	299830	4141	0	0
T5	53537	10223	0	0
T6	41089	7242	0	0
T7	107806	240995	0	0
T8	19001	3590	0	0
T9	31345	23406	0	0
T10	47178	7893	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	511358902	0	0
T1	11113	4148	0	0
T2	3878	708	0	0
T3	13890	5233	0	0
T4	299830	4141	0	0
T5	53537	10223	0	0
T6	41089	7242	0	0
T7	107806	240995	0	0
T8	19001	3590	0	0
T9	31345	23406	0	0
T10	47178	7893	0	0

IntegChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	13	0	0
T39	13233	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	14864	0	0	0
T63	13563	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	18511	0	0	0
T81	13095	0	0	0
T82	21527	0	0	0
T83	15230	0	0	0
T84	21853	0	0	0
T85	204292	0	0	0
T86	28365	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ReadLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrambledImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113071478	2112323938	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074	1074	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WriteLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	0	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2113347341	2112599801	0	0
T1	11113	10881	0	0
T2	3878	3809	0	0
T3	13890	13613	0	0
T4	299830	299829	0	0
T5	53537	52287	0	0
T6	41089	40282	0	0
T7	107806	107803	0	0
T8	19001	18472	0	0
T9	31345	31191	0	0
T10	47178	46411	0	0