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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1335	1335	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	2147483647	185020299	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1335	1335	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	2147483647	51401183	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1335	1335	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	2147483647	77978426	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1335	1335	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	2147483647	74939081	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1335	1335	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	2147483647	107041873	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1335	1335	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1335	1335	0	0
tb.dut.u_reg_core.wePulse	0	0	2147483647	3008477	0	0
tb.dut.u_scrmbl_mtx.CheckHotOne_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A	0	0	1160	1160	0	0
tb.dut.u_scrmbl_mtx.GrantKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.IdxKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A	0	0	2147483647	42542877	0	0
tb.dut.u_scrmbl_mtx.ValidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A	0	0	1160	1160	0	0
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A	0	0	1160	1160	0	0
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A	0	0	1160	1160	0	0
tb.dut.u_tlul_adapter_sram.TlOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_A	0	0	2147483647	77961150	0	0
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.WeOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite	0	0	1160	1160	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty	0	0	2147483647	88220	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull	0	0	2147483647	88220	0	0
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A	0	0	1160	1160	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A	0	0	2147483647	78459538	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	2147483647	78459538	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A	0	0	1160	1160	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck	0	0	1160	1160	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A	0	0	2147483647	224179	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	2147483647	224179	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A	0	0	2147483647	586608	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	2147483647	586608	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1160	1160	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A	0	0	1160	1160	0	0
tb.dut.u_tlul_lc_gate.u_state_regs_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1160	1160	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1160	1160	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_arb.RoundRobin_A	0	0	2147483647	0	0	1160
tb.dut.u_otp_arb.RoundRobin_A	0	0	2147483647	0	0	1160
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A	0	0	2147483647	0	0	1160
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	2147483647	0	0	1160
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3480
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3480
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3480
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3480
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3480
tb.dut.u_scrmbl_mtx.RoundRobin_A	0	0	2147483647	0	0	1160

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	699	699	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	196	196	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	198	198	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	130	130	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	18	18	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	105	105	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	95	95	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	3898	3898	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	6744	6744	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	2058818	2058818	1249
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	310	310	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	73	73	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	82	82	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	61	61	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	5	5	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	49	49	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	29	29	1
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	1527	1527	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	2960	2960	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	61571	61571	82

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	699	699	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	196	196	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	198	198	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	130	130	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	18	18	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	105	105	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	95	95	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	3898	3898	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	6744	6744	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	2058818	2058818	1249
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	310	310	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	73	73	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	82	82	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	61	61	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	5	5	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	49	49	1
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	29	29	1
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	1527	1527	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	2960	2960	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	61571	61571	82