Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.44 92.61 91.44 92.39 92.39 93.55 96.53 95.19


Total tests in report: 1335
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
45.91 45.91 68.07 68.07 56.38 56.38 61.94 61.94 0.00 0.00 64.71 64.71 45.32 45.32 24.98 24.98 /workspace/coverage/default/6.otp_ctrl_stress_all.4226072709
77.83 31.91 89.74 21.67 78.09 21.72 69.70 7.76 92.39 92.39 86.31 21.60 91.25 45.93 37.30 12.32 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3308219356
81.49 3.66 89.80 0.06 79.53 1.44 75.24 5.54 92.39 0.00 86.63 0.32 91.40 0.15 55.44 18.14 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3184667966
84.92 3.43 90.10 0.30 81.22 1.68 87.55 12.31 92.39 0.00 87.54 0.91 91.48 0.08 64.14 8.69 /workspace/coverage/default/23.otp_ctrl_stress_all.1789144304
86.66 1.75 90.27 0.17 83.93 2.71 87.66 0.11 92.39 0.00 87.91 0.37 92.16 0.68 72.32 8.19 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1998340847
87.72 1.05 90.57 0.30 86.16 2.23 88.03 0.37 92.39 0.00 89.20 1.28 92.38 0.23 75.27 2.95 /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2879874315
88.45 0.73 90.72 0.15 86.73 0.57 88.42 0.39 92.39 0.00 90.59 1.39 94.65 2.26 75.61 0.34 /workspace/coverage/default/0.otp_ctrl_sec_cm.3488862331
89.05 0.60 90.78 0.06 86.94 0.22 89.57 1.15 92.39 0.00 90.70 0.11 94.72 0.08 78.23 2.62 /workspace/coverage/default/28.otp_ctrl_stress_all.2652197537
89.57 0.53 90.82 0.04 87.40 0.46 89.59 0.01 92.39 0.00 90.91 0.21 94.72 0.00 81.18 2.95 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2499975323
90.01 0.44 90.82 0.00 87.62 0.22 89.69 0.10 92.39 0.00 90.91 0.00 95.17 0.45 83.46 2.28 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3383607593
90.31 0.30 90.82 0.00 87.68 0.05 90.70 1.01 92.39 0.00 90.91 0.00 95.17 0.00 84.47 1.01 /workspace/coverage/default/47.otp_ctrl_stress_all.446668709
90.59 0.28 90.90 0.08 88.14 0.46 90.81 0.11 92.39 0.00 91.12 0.21 95.17 0.00 85.57 1.10 /workspace/coverage/default/45.otp_ctrl_check_fail.1211440421
90.81 0.23 90.90 0.00 88.17 0.03 90.81 0.00 92.39 0.00 91.18 0.05 95.32 0.15 86.92 1.35 /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2684718281
90.99 0.17 91.07 0.17 88.33 0.16 90.89 0.08 92.39 0.00 91.50 0.32 95.55 0.23 87.17 0.25 /workspace/coverage/default/184.otp_ctrl_init_fail.719163231
91.15 0.16 91.07 0.00 88.33 0.00 91.02 0.13 92.39 0.00 91.50 0.00 95.55 0.00 88.19 1.01 /workspace/coverage/default/3.otp_ctrl_stress_all.2483302027
91.30 0.15 91.07 0.00 88.38 0.05 91.02 0.00 92.39 0.00 91.50 0.00 95.55 0.00 89.20 1.01 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.438516667
91.44 0.14 91.07 0.00 88.84 0.46 91.22 0.20 92.39 0.00 91.66 0.16 95.55 0.00 89.37 0.17 /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.1682520
91.58 0.13 91.14 0.08 89.17 0.33 91.23 0.01 92.39 0.00 91.76 0.11 95.63 0.08 89.70 0.34 /workspace/coverage/default/5.otp_ctrl_macro_errs.1426567102
91.70 0.12 91.25 0.11 89.44 0.27 91.33 0.11 92.39 0.00 92.03 0.27 95.63 0.00 89.79 0.08 /workspace/coverage/default/140.otp_ctrl_init_fail.1055186986
91.80 0.11 91.25 0.00 89.44 0.00 91.33 0.00 92.39 0.00 92.03 0.00 96.30 0.68 89.87 0.08 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2859975726
91.91 0.11 91.39 0.13 89.58 0.14 91.33 0.00 92.39 0.00 92.19 0.16 96.38 0.08 90.13 0.25 /workspace/coverage/default/41.otp_ctrl_check_fail.3808122185
92.01 0.10 91.39 0.00 89.63 0.05 91.39 0.05 92.39 0.00 92.19 0.00 96.38 0.00 90.72 0.59 /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3309104992
92.10 0.09 91.39 0.00 89.63 0.00 91.42 0.03 92.39 0.00 92.19 0.00 96.38 0.00 91.31 0.59 /workspace/coverage/default/26.otp_ctrl_stress_all.3250044176
92.19 0.09 91.50 0.11 89.71 0.08 91.55 0.13 92.39 0.00 92.41 0.21 96.38 0.00 91.39 0.08 /workspace/coverage/default/174.otp_ctrl_init_fail.3351655099
92.27 0.08 91.71 0.21 89.98 0.27 91.55 0.00 92.39 0.00 92.41 0.00 96.38 0.00 91.48 0.08 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1340947512
92.35 0.08 91.75 0.04 90.07 0.08 91.55 0.00 92.39 0.00 92.51 0.11 96.38 0.00 91.81 0.34 /workspace/coverage/default/10.otp_ctrl_check_fail.1594531577
92.42 0.07 91.88 0.13 90.15 0.08 91.55 0.00 92.39 0.00 92.67 0.16 96.38 0.00 91.90 0.08 /workspace/coverage/default/28.otp_ctrl_check_fail.1012929272
92.48 0.06 91.88 0.00 90.15 0.00 91.56 0.01 92.39 0.00 92.67 0.00 96.38 0.00 92.32 0.42 /workspace/coverage/default/13.otp_ctrl_regwen.2033283770
92.54 0.06 91.94 0.06 90.23 0.08 91.62 0.06 92.39 0.00 92.78 0.11 96.38 0.00 92.41 0.08 /workspace/coverage/default/59.otp_ctrl_init_fail.1073712759
92.59 0.06 91.94 0.00 90.28 0.05 91.62 0.00 92.39 0.00 92.78 0.00 96.38 0.00 92.74 0.34 /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1807213670
92.65 0.05 91.99 0.06 90.31 0.03 91.62 0.00 92.39 0.00 92.83 0.05 96.46 0.08 92.91 0.17 /workspace/coverage/default/26.otp_ctrl_macro_errs.3176557450
92.69 0.05 92.33 0.34 90.31 0.00 91.62 0.00 92.39 0.00 92.83 0.00 96.46 0.00 92.91 0.00 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2190755077
92.74 0.05 92.33 0.00 90.31 0.00 91.62 0.00 92.39 0.00 92.83 0.00 96.46 0.00 93.25 0.34 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2297506683
92.79 0.04 92.33 0.00 90.36 0.05 91.62 0.00 92.39 0.00 92.83 0.00 96.46 0.00 93.50 0.25 /workspace/coverage/default/40.otp_ctrl_stress_all.1998534914
92.83 0.04 92.39 0.06 90.39 0.03 91.62 0.00 92.39 0.00 92.89 0.05 96.46 0.00 93.67 0.17 /workspace/coverage/default/37.otp_ctrl_check_fail.2953931420
92.87 0.04 92.45 0.06 90.42 0.03 91.69 0.06 92.39 0.00 92.94 0.05 96.46 0.00 93.76 0.08 /workspace/coverage/default/49.otp_ctrl_init_fail.1858055333
92.91 0.04 92.45 0.00 90.69 0.27 91.69 0.01 92.39 0.00 92.94 0.00 96.46 0.00 93.76 0.00 /workspace/coverage/default/1.otp_ctrl_alert_test.822733154
92.95 0.04 92.45 0.00 90.69 0.00 91.69 0.00 92.39 0.00 92.94 0.00 96.46 0.00 94.01 0.25 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3066923550
92.98 0.04 92.50 0.06 90.74 0.05 91.69 0.00 92.39 0.00 92.99 0.05 96.46 0.00 94.09 0.08 /workspace/coverage/default/233.otp_ctrl_init_fail.1843411306
93.01 0.03 92.56 0.06 90.77 0.03 91.69 0.00 92.39 0.00 93.05 0.05 96.46 0.00 94.18 0.08 /workspace/coverage/default/105.otp_ctrl_init_fail.4111887559
93.05 0.03 92.62 0.06 90.80 0.03 91.69 0.00 92.39 0.00 93.10 0.05 96.46 0.00 94.26 0.08 /workspace/coverage/default/266.otp_ctrl_init_fail.2956743189
93.07 0.03 92.62 0.00 90.80 0.00 91.72 0.03 92.39 0.00 93.10 0.00 96.46 0.00 94.43 0.17 /workspace/coverage/default/20.otp_ctrl_regwen.3123467084
93.10 0.03 92.62 0.00 90.83 0.03 91.72 0.00 92.39 0.00 93.10 0.00 96.46 0.00 94.60 0.17 /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2792090750
93.13 0.02 92.62 0.00 90.83 0.00 91.72 0.00 92.39 0.00 93.10 0.00 96.46 0.00 94.77 0.17 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1636918729
93.15 0.02 92.62 0.00 90.83 0.00 91.72 0.00 92.39 0.00 93.10 0.00 96.46 0.00 94.94 0.17 /workspace/coverage/default/37.otp_ctrl_regwen.3092769408
93.17 0.02 92.66 0.04 90.85 0.03 91.76 0.04 92.39 0.00 93.16 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/221.otp_ctrl_init_fail.2151081227
93.20 0.02 92.69 0.04 90.88 0.03 91.81 0.04 92.39 0.00 93.21 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/242.otp_ctrl_init_fail.4004252768
93.22 0.02 92.75 0.06 90.91 0.03 91.82 0.01 92.39 0.00 93.26 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/271.otp_ctrl_init_fail.770554382
93.24 0.02 92.75 0.00 90.91 0.00 91.96 0.14 92.39 0.00 93.26 0.00 96.46 0.00 94.94 0.00 /workspace/coverage/default/22.otp_ctrl_init_fail.2789047437
93.26 0.02 92.75 0.00 90.91 0.00 92.09 0.13 92.39 0.00 93.26 0.00 96.46 0.00 94.94 0.00 /workspace/coverage/default/69.otp_ctrl_init_fail.977254408
93.27 0.02 92.79 0.04 90.93 0.03 92.09 0.00 92.39 0.00 93.32 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/101.otp_ctrl_init_fail.925361182
93.29 0.02 92.83 0.04 90.96 0.03 92.09 0.00 92.39 0.00 93.37 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/102.otp_ctrl_init_fail.1497741327
93.31 0.02 92.86 0.04 90.99 0.03 92.09 0.00 92.39 0.00 93.42 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/104.otp_ctrl_init_fail.1137417361
93.32 0.02 92.86 0.00 91.07 0.08 92.13 0.04 92.39 0.00 93.42 0.00 96.46 0.00 94.94 0.00 /workspace/coverage/default/14.otp_ctrl_check_fail.3986311420
93.34 0.02 92.86 0.00 91.18 0.11 92.13 0.00 92.39 0.00 93.42 0.00 96.46 0.00 94.94 0.00 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3512072059
93.35 0.01 92.86 0.00 91.18 0.00 92.13 0.00 92.39 0.00 93.42 0.00 96.46 0.00 95.02 0.08 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2926603124
93.36 0.01 92.86 0.00 91.18 0.00 92.13 0.00 92.39 0.00 93.42 0.00 96.46 0.00 95.11 0.08 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1890306692
93.38 0.01 92.86 0.00 91.18 0.00 92.13 0.00 92.39 0.00 93.42 0.00 96.46 0.00 95.19 0.08 /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.649138562
93.39 0.01 92.86 0.00 91.18 0.00 92.13 0.00 92.39 0.00 93.42 0.00 96.53 0.08 95.19 0.00 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2054484139
93.40 0.01 92.88 0.02 91.18 0.00 92.13 0.00 92.39 0.00 93.48 0.05 96.53 0.00 95.19 0.00 /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1626323230
93.41 0.01 92.88 0.00 91.18 0.00 92.19 0.06 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/45.otp_ctrl_stress_all.1809090550
93.41 0.01 92.88 0.00 91.23 0.05 92.19 0.00 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/22.otp_ctrl_check_fail.1929933659
93.42 0.01 92.90 0.02 91.26 0.03 92.19 0.00 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1456391730
93.43 0.01 92.90 0.00 91.26 0.00 92.22 0.04 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/8.otp_ctrl_parallel_key_req.1382830542
93.43 0.01 92.90 0.00 91.26 0.00 92.25 0.03 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/209.otp_ctrl_init_fail.2257657742
93.43 0.01 92.90 0.00 91.26 0.00 92.28 0.03 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/274.otp_ctrl_init_fail.197753290
93.44 0.01 92.90 0.00 91.26 0.00 92.31 0.03 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/47.otp_ctrl_init_fail.3442372659
93.44 0.01 92.90 0.00 91.29 0.03 92.31 0.00 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/12.otp_ctrl_macro_errs.2179405516
93.45 0.01 92.90 0.00 91.31 0.03 92.31 0.00 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.438013917
93.45 0.01 92.90 0.00 91.31 0.00 92.33 0.02 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2490513683
93.45 0.01 92.92 0.02 91.31 0.00 92.33 0.00 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/0.otp_ctrl_test_access.1882762492
93.45 0.01 92.94 0.02 91.31 0.00 92.33 0.00 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/7.otp_ctrl_test_access.3372850000
93.46 0.01 92.94 0.00 91.31 0.00 92.34 0.01 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/191.otp_ctrl_init_fail.3674898132
93.46 0.01 92.94 0.00 91.31 0.00 92.36 0.01 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/24.otp_ctrl_init_fail.3856992024
93.46 0.01 92.94 0.00 91.31 0.00 92.37 0.01 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/280.otp_ctrl_init_fail.3908181909
93.46 0.01 92.94 0.00 91.31 0.00 92.38 0.01 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/132.otp_ctrl_init_fail.674477419
93.46 0.01 92.94 0.00 91.31 0.00 92.39 0.01 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/147.otp_ctrl_init_fail.1502766691
93.46 0.01 92.94 0.00 91.31 0.00 92.39 0.01 92.39 0.00 93.48 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/192.otp_ctrl_init_fail.1242999892

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2542334221
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1943879547
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.991315309
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.997482595
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1543773732
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1937537042
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2138063306
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2336942490
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.20351686
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3550356101
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.694032762
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.628868254
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3130069740
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2036727199
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2630332317
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1907049708
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3560985853
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4278100657
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.29405411
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1897600518
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1158525219
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.985242495
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3224140847
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3087897690
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2714883248
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2789338569
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2128351141
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2916346461
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2420496614
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1107606155
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.203326932
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.384504758
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.156902980
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3875739356
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.135511980
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3752906030
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3852974645
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3945485827
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.576451467
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.927753841
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2472375604
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1779199475
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2079581435
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.15078361
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1608029760
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.804652864
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2624447677
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2898496778
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1986966721
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1480916804
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.76592641
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1570874200
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.55213193
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4200880245
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1700904639
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1409623989
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4207425789
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1340709978
/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.819973755
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1044302886
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1172106772
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3477774752
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.841258377
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/workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.890141060
/workspace/coverage/default/94.otp_ctrl_init_fail.4056783551
/workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.347247063
/workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.259929994
/workspace/coverage/default/95.otp_ctrl_init_fail.3386623221
/workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2886273062
/workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.3459791376
/workspace/coverage/default/96.otp_ctrl_init_fail.944167179
/workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3471199844
/workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3868594160
/workspace/coverage/default/97.otp_ctrl_init_fail.3774104788
/workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.787599673
/workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.2761215517
/workspace/coverage/default/98.otp_ctrl_init_fail.2986501920
/workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3436895234
/workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1478730563
/workspace/coverage/default/99.otp_ctrl_init_fail.1275700094
/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.2333761726
/workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.624120730



Total test records in report: 1335
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T65 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3308219356 Jan 07 01:42:26 PM PST 24 Jan 07 01:42:47 PM PST 24 45084530 ps
T98 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2499975323 Jan 07 01:43:29 PM PST 24 Jan 07 01:43:50 PM PST 24 131857190 ps
T99 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.804652864 Jan 07 01:42:42 PM PST 24 Jan 07 01:43:03 PM PST 24 135389630 ps
T177 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1998340847 Jan 07 01:43:14 PM PST 24 Jan 07 01:43:32 PM PST 24 166486229 ps
T101 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3285055206 Jan 07 01:43:35 PM PST 24 Jan 07 01:43:54 PM PST 24 42240114 ps
T100 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4207425789 Jan 07 01:43:33 PM PST 24 Jan 07 01:43:54 PM PST 24 69392852 ps
T178 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3560985853 Jan 07 01:43:17 PM PST 24 Jan 07 01:43:36 PM PST 24 64029334 ps
T102 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1906361500 Jan 07 01:43:43 PM PST 24 Jan 07 01:43:59 PM PST 24 593697257 ps
T103 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3184667966 Jan 07 01:43:05 PM PST 24 Jan 07 01:43:27 PM PST 24 639159083 ps
T104 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1107606155 Jan 07 01:43:27 PM PST 24 Jan 07 01:43:49 PM PST 24 108809002 ps
T180 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2297506683 Jan 07 01:43:13 PM PST 24 Jan 07 01:43:30 PM PST 24 538816397 ps
T187 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.15078361 Jan 07 01:42:22 PM PST 24 Jan 07 01:42:49 PM PST 24 2329109477 ps
T188 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1636918729 Jan 07 01:44:01 PM PST 24 Jan 07 01:44:10 PM PST 24 78448337 ps
T202 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2621536395 Jan 07 01:43:07 PM PST 24 Jan 07 01:43:29 PM PST 24 307267936 ps
T233 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1762585672 Jan 07 01:43:14 PM PST 24 Jan 07 01:43:29 PM PST 24 69960418 ps
T269 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.965113199 Jan 07 01:42:34 PM PST 24 Jan 07 01:42:55 PM PST 24 35383851 ps
T221 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.90882722 Jan 07 01:43:29 PM PST 24 Jan 07 01:43:49 PM PST 24 146240942 ps
T270 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.934227790 Jan 07 01:43:48 PM PST 24 Jan 07 01:44:02 PM PST 24 533726764 ps
T271 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3759356388 Jan 07 01:43:35 PM PST 24 Jan 07 01:43:54 PM PST 24 38286901 ps
T272 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3746614813 Jan 07 01:43:08 PM PST 24 Jan 07 01:43:21 PM PST 24 77896695 ps
T311 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1435329086 Jan 07 01:42:20 PM PST 24 Jan 07 01:42:37 PM PST 24 500769698 ps
T223 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1779199475 Jan 07 01:42:39 PM PST 24 Jan 07 01:43:02 PM PST 24 95943513 ps
T224 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3852974645 Jan 07 01:42:17 PM PST 24 Jan 07 01:42:34 PM PST 24 47781833 ps
T222 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3383607593 Jan 07 01:42:28 PM PST 24 Jan 07 01:42:51 PM PST 24 1930792296 ps
T179 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.896100823 Jan 07 01:42:33 PM PST 24 Jan 07 01:42:50 PM PST 24 740624842 ps
T181 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1409623989 Jan 07 01:42:32 PM PST 24 Jan 07 01:42:50 PM PST 24 76153810 ps
T232 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2859975726 Jan 07 01:42:09 PM PST 24 Jan 07 01:42:21 PM PST 24 159324912 ps
T206 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4200880245 Jan 07 01:43:40 PM PST 24 Jan 07 01:43:59 PM PST 24 108952427 ps
T182 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2775332398 Jan 07 01:42:31 PM PST 24 Jan 07 01:42:51 PM PST 24 1098809270 ps
T279 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2333077502 Jan 07 01:43:54 PM PST 24 Jan 07 01:44:05 PM PST 24 127445060 ps
T183 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1986966721 Jan 07 01:43:04 PM PST 24 Jan 07 01:43:21 PM PST 24 134266842 ps
T280 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2976174301 Jan 07 01:43:19 PM PST 24 Jan 07 01:43:37 PM PST 24 141120665 ps
T184 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1340947512 Jan 07 01:42:20 PM PST 24 Jan 07 01:42:42 PM PST 24 177098848 ps
T185 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3224140847 Jan 07 01:43:38 PM PST 24 Jan 07 01:43:58 PM PST 24 91480574 ps
T105 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1456391730 Jan 07 01:43:18 PM PST 24 Jan 07 01:43:35 PM PST 24 98576131 ps
T286 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.862067655 Jan 07 01:43:15 PM PST 24 Jan 07 01:43:31 PM PST 24 587709668 ps
T273 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1020412632 Jan 07 01:42:38 PM PST 24 Jan 07 01:43:07 PM PST 24 414315915 ps
T201 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1480916804 Jan 07 01:43:06 PM PST 24 Jan 07 01:43:38 PM PST 24 4667483796 ps
T229 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.438516667 Jan 07 01:42:12 PM PST 24 Jan 07 01:42:50 PM PST 24 19127846545 ps
T234 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1907049708 Jan 07 01:43:42 PM PST 24 Jan 07 01:43:58 PM PST 24 40814707 ps
T372 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.1925544150 Jan 07 01:43:06 PM PST 24 Jan 07 01:43:20 PM PST 24 75894585 ps
T186 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3085661390 Jan 07 01:42:29 PM PST 24 Jan 07 01:42:49 PM PST 24 336475575 ps
T235 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1474921371 Jan 07 01:42:14 PM PST 24 Jan 07 01:42:26 PM PST 24 745397583 ps
T226 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1685321414 Jan 07 01:42:35 PM PST 24 Jan 07 01:43:00 PM PST 24 141800285 ps
T371 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2997908219 Jan 07 01:42:41 PM PST 24 Jan 07 01:43:15 PM PST 24 390474501 ps
T236 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.203326932 Jan 07 01:43:19 PM PST 24 Jan 07 01:43:36 PM PST 24 44704058 ps
T237 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1570874200 Jan 07 01:43:31 PM PST 24 Jan 07 01:43:52 PM PST 24 40387497 ps
T315 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3550356101 Jan 07 01:43:09 PM PST 24 Jan 07 01:43:30 PM PST 24 633078718 ps
T373 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1158525219 Jan 07 01:43:39 PM PST 24 Jan 07 01:43:56 PM PST 24 52878187 ps
T238 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.307051606 Jan 07 01:42:36 PM PST 24 Jan 07 01:43:00 PM PST 24 221140564 ps
T312 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3066923550 Jan 07 01:42:15 PM PST 24 Jan 07 01:42:40 PM PST 24 1307500544 ps
T274 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3195390611 Jan 07 01:43:05 PM PST 24 Jan 07 01:43:22 PM PST 24 1536915868 ps
T239 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1897600518 Jan 07 01:43:15 PM PST 24 Jan 07 01:43:31 PM PST 24 42124996 ps
T240 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3711886999 Jan 07 01:42:27 PM PST 24 Jan 07 01:42:47 PM PST 24 71208363 ps
T241 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1241066474 Jan 07 01:42:35 PM PST 24 Jan 07 01:42:57 PM PST 24 334678244 ps
T282 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3687727487 Jan 07 01:43:21 PM PST 24 Jan 07 01:43:38 PM PST 24 143574267 ps
T283 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1250576187 Jan 07 01:43:24 PM PST 24 Jan 07 01:43:42 PM PST 24 40325112 ps
T225 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3477774752 Jan 07 01:42:38 PM PST 24 Jan 07 01:43:02 PM PST 24 364771196 ps
T284 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.313403750 Jan 07 01:42:39 PM PST 24 Jan 07 01:43:02 PM PST 24 86673940 ps
T242 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3626467970 Jan 07 01:42:11 PM PST 24 Jan 07 01:42:21 PM PST 24 522300212 ps
T374 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1565908893 Jan 07 01:42:14 PM PST 24 Jan 07 01:42:24 PM PST 24 75621586 ps
T375 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2036727199 Jan 07 01:43:15 PM PST 24 Jan 07 01:43:31 PM PST 24 40576401 ps
T230 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1234745279 Jan 07 01:43:07 PM PST 24 Jan 07 01:43:28 PM PST 24 2463702625 ps
T376 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.1410621063 Jan 07 01:42:27 PM PST 24 Jan 07 01:42:47 PM PST 24 36149427 ps
T243 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.135511980 Jan 07 01:43:01 PM PST 24 Jan 07 01:43:17 PM PST 24 71429610 ps
T244 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.56370271 Jan 07 01:42:39 PM PST 24 Jan 07 01:43:07 PM PST 24 129015569 ps
T252 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.927753841 Jan 07 01:42:17 PM PST 24 Jan 07 01:42:35 PM PST 24 333946837 ps
T253 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.831092960 Jan 07 01:42:31 PM PST 24 Jan 07 01:42:49 PM PST 24 287768765 ps
T254 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2961472806 Jan 07 01:43:07 PM PST 24 Jan 07 01:43:20 PM PST 24 66250016 ps
T231 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3969561555 Jan 07 01:42:15 PM PST 24 Jan 07 01:42:37 PM PST 24 2599500912 ps
T227 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3512072059 Jan 07 01:43:09 PM PST 24 Jan 07 01:43:29 PM PST 24 590364718 ps
T245 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.198906412 Jan 07 01:42:37 PM PST 24 Jan 07 01:42:59 PM PST 24 615268260 ps
T255 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.835753878 Jan 07 01:43:33 PM PST 24 Jan 07 01:43:54 PM PST 24 131153145 ps
T256 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.20351686 Jan 07 01:43:17 PM PST 24 Jan 07 01:43:34 PM PST 24 105466692 ps
T257 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1890306692 Jan 07 01:43:30 PM PST 24 Jan 07 01:44:08 PM PST 24 4578146830 ps
T281 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3094042248 Jan 07 01:43:19 PM PST 24 Jan 07 01:43:37 PM PST 24 249593636 ps
T228 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1044302886 Jan 07 01:43:58 PM PST 24 Jan 07 01:44:13 PM PST 24 173748084 ps
T301 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2887161295 Jan 07 01:43:07 PM PST 24 Jan 07 01:43:23 PM PST 24 362192086 ps
T377 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2277566026 Jan 07 01:43:25 PM PST 24 Jan 07 01:43:43 PM PST 24 66412060 ps
T275 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1608029760 Jan 07 01:43:17 PM PST 24 Jan 07 01:43:34 PM PST 24 287212397 ps
T378 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.4048518966 Jan 07 01:43:17 PM PST 24 Jan 07 01:43:33 PM PST 24 71569169 ps
T379 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3170958646 Jan 07 01:43:23 PM PST 24 Jan 07 01:43:42 PM PST 24 566674782 ps
T380 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1474468080 Jan 07 01:42:41 PM PST 24 Jan 07 01:43:02 PM PST 24 71223436 ps
T276 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.76592641 Jan 07 01:43:25 PM PST 24 Jan 07 01:43:51 PM PST 24 190887916 ps
T381 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3448440664 Jan 07 01:43:34 PM PST 24 Jan 07 01:43:54 PM PST 24 86291861 ps
T382 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.1854884050 Jan 07 01:43:40 PM PST 24 Jan 07 01:43:57 PM PST 24 134714030 ps
T246 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2542334221 Jan 07 01:43:42 PM PST 24 Jan 07 01:44:00 PM PST 24 270917998 ps
T302 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2594754945 Jan 07 01:42:45 PM PST 24 Jan 07 01:43:09 PM PST 24 115655358 ps
T383 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2624447677 Jan 07 01:43:07 PM PST 24 Jan 07 01:43:20 PM PST 24 74491457 ps
T247 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2942420146 Jan 07 01:43:30 PM PST 24 Jan 07 01:43:51 PM PST 24 144959613 ps
T384 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.694032762 Jan 07 01:43:20 PM PST 24 Jan 07 01:43:38 PM PST 24 93440915 ps
T385 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1662221769 Jan 07 01:43:08 PM PST 24 Jan 07 01:43:22 PM PST 24 40383084 ps
T318 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.4278100657 Jan 07 01:43:20 PM PST 24 Jan 07 01:43:55 PM PST 24 4430775849 ps
T248 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.841258377 Jan 07 01:42:39 PM PST 24 Jan 07 01:43:03 PM PST 24 154985464 ps
T251 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3945641535 Jan 07 01:42:32 PM PST 24 Jan 07 01:42:49 PM PST 24 40038999 ps
T277 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1419968785 Jan 07 01:42:41 PM PST 24 Jan 07 01:43:04 PM PST 24 446714257 ps
T386 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3875739356 Jan 07 01:42:30 PM PST 24 Jan 07 01:42:49 PM PST 24 258092262 ps
T387 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3535676479 Jan 07 01:42:38 PM PST 24 Jan 07 01:43:00 PM PST 24 61871381 ps
T388 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.730465572 Jan 07 01:43:09 PM PST 24 Jan 07 01:43:23 PM PST 24 55538607 ps
T389 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2729839605 Jan 07 01:42:28 PM PST 24 Jan 07 01:42:47 PM PST 24 76916464 ps
T390 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.156902980 Jan 07 01:43:17 PM PST 24 Jan 07 01:43:35 PM PST 24 200462910 ps
T316 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1172106772 Jan 07 01:43:45 PM PST 24 Jan 07 01:44:15 PM PST 24 4742362845 ps
T391 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.55213193 Jan 07 01:43:12 PM PST 24 Jan 07 01:43:26 PM PST 24 569598812 ps
T303 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.997482595 Jan 07 01:43:15 PM PST 24 Jan 07 01:43:32 PM PST 24 369093484 ps
T392 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3087897690 Jan 07 01:43:19 PM PST 24 Jan 07 01:43:43 PM PST 24 644311796 ps
T393 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3375084163 Jan 07 01:43:27 PM PST 24 Jan 07 01:44:06 PM PST 24 1611648171 ps
T394 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2789338569 Jan 07 01:43:17 PM PST 24 Jan 07 01:43:34 PM PST 24 38967252 ps
T313 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2637950236 Jan 07 01:42:12 PM PST 24 Jan 07 01:42:40 PM PST 24 4678207555 ps
T395 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1380661398 Jan 07 01:42:30 PM PST 24 Jan 07 01:42:49 PM PST 24 107521020 ps
T396 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2079581435 Jan 07 01:42:11 PM PST 24 Jan 07 01:42:23 PM PST 24 364158688 ps
T397 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3475249065 Jan 07 01:42:17 PM PST 24 Jan 07 01:42:34 PM PST 24 35019637 ps
T314 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.576451467 Jan 07 01:43:45 PM PST 24 Jan 07 01:44:08 PM PST 24 1401657656 ps
T398 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2472375604 Jan 07 01:43:03 PM PST 24 Jan 07 01:43:18 PM PST 24 551974538 ps
T399 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3915236288 Jan 07 01:42:26 PM PST 24 Jan 07 01:42:46 PM PST 24 142881572 ps
T400 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.674702499 Jan 07 01:43:11 PM PST 24 Jan 07 01:43:27 PM PST 24 141918186 ps
T317 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2812991435 Jan 07 01:43:04 PM PST 24 Jan 07 01:43:36 PM PST 24 3249935024 ps
T401 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.791754444 Jan 07 01:42:25 PM PST 24 Jan 07 01:42:46 PM PST 24 134413301 ps
T402 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.614981804 Jan 07 01:43:18 PM PST 24 Jan 07 01:43:34 PM PST 24 99758617 ps
T403 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1610686711 Jan 07 01:42:37 PM PST 24 Jan 07 01:43:00 PM PST 24 62214376 ps
T404 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.1290636799 Jan 07 01:42:33 PM PST 24 Jan 07 01:42:50 PM PST 24 83436403 ps
T405 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2610824329 Jan 07 01:42:31 PM PST 24 Jan 07 01:43:05 PM PST 24 1768581346 ps
T406 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1543773732 Jan 07 01:43:10 PM PST 24 Jan 07 01:43:25 PM PST 24 78017286 ps
T407 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.4065202522 Jan 07 01:43:27 PM PST 24 Jan 07 01:43:48 PM PST 24 129961043 ps
T408 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1943879547 Jan 07 01:43:19 PM PST 24 Jan 07 01:43:43 PM PST 24 1362548333 ps
T409 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2917953833 Jan 07 01:42:17 PM PST 24 Jan 07 01:42:34 PM PST 24 520939028 ps
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