Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50407	1			T1	45		T8	244		T22	200
access_err	83051	1			T1	2		T3	167		T5	113
write_blank_err	406	1			T6	2		T11	1		T22	7
ecc_uncorr_err	72534	1			T6	447		T10	13		T11	216
ecc_corr_err	1249	1			T12	2		T78	12		T90	10
no_err	390347	1			T1	61		T3	715		T5	369

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	43610	1			T1	4		T3	130		T5	36
secret2	60479	1			T3	120		T5	70		T6	142
secret1	88815	1			T1	6		T3	64		T5	98
secret0	117454	1			T3	128		T5	46		T6	1048
hw_cfg	67614	1			T1	90		T3	78		T5	56
owner_sw_cfg	65717	1			T1	4		T3	118		T5	70
creator_sw_cfg	67427	1			T1	4		T3	132		T5	50
vendor_test	86878	1			T3	112		T5	56		T6	128

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	2032	1			T194	224		T304	241		T167	75
fsm_err	secret2	2541	1			T81	6		T250	166		T305	524
fsm_err	secret1	4267	1			T73	64		T81	2		T306	47
fsm_err	secret0	5401	1			T81	381		T307	87		T192	98
fsm_err	hw_cfg	7517	1			T1	45		T175	4		T157	359
fsm_err	owner_sw_cfg	4128	1			T90	72		T203	40		T308	164
fsm_err	creator_sw_cfg	4492	1			T8	244		T74	55		T91	37
fsm_err	vendor_test	20029	1			T22	200		T89	408		T36	92
access_err	lc_or_oob	19770	1			T1	2		T3	65		T5	18
access_err	secret2	13860	1			T3	36		T5	10		T6	48
access_err	secret1	7121	1			T5	25		T6	3		T7	9
access_err	secret0	5723	1			T5	10		T6	1		T7	16
access_err	hw_cfg	3179	1			T5	6		T6	1		T7	11
access_err	owner_sw_cfg	12566	1			T3	18		T5	25		T6	27
access_err	creator_sw_cfg	12620	1			T3	20		T5	14		T6	30
access_err	vendor_test	8212	1			T3	28		T5	5		T6	35
write_blank_err	secret2	15	1			T22	1		T309	1		T167	2
write_blank_err	secret1	52	1			T11	1		T12	1		T91	1
write_blank_err	secret0	92	1			T6	1		T12	2		T109	1
write_blank_err	hw_cfg	18	1			T22	1		T110	1		T310	1
write_blank_err	owner_sw_cfg	103	1			T6	1		T22	4		T12	1
write_blank_err	creator_sw_cfg	85	1			T92	1		T189	1		T295	3
write_blank_err	vendor_test	41	1			T22	1		T12	1		T203	1
ecc_uncorr_err	secret2	6203	1			T22	508		T309	255		T106	74
ecc_uncorr_err	secret1	20031	1			T10	13		T11	216		T12	301
ecc_uncorr_err	secret0	35728	1			T6	447		T12	498		T109	462
ecc_uncorr_err	hw_cfg	5653	1			T22	455		T110	253		T310	521
ecc_uncorr_err	owner_sw_cfg	1806	1			T92	52		T116	64		T107	35
ecc_uncorr_err	creator_sw_cfg	3113	1			T116	52		T291	60		T106	189
ecc_corr_err	secret2	112	1			T78	3		T36	2		T60	9
ecc_corr_err	secret1	144	1			T78	1		T90	2		T36	1
ecc_corr_err	secret0	203	1			T12	1		T78	4		T90	2
ecc_corr_err	hw_cfg	279	1			T36	8		T80	2		T19	2
ecc_corr_err	owner_sw_cfg	128	1			T78	1		T36	1		T116	1
ecc_corr_err	creator_sw_cfg	138	1			T90	6		T36	1		T60	1
ecc_corr_err	vendor_test	245	1			T12	1		T78	3		T36	5
no_err	lc_or_oob	21808	1			T1	2		T3	65		T5	18
no_err	secret2	37748	1			T3	84		T5	60		T6	94
no_err	secret1	57200	1			T1	6		T3	64		T5	73
no_err	secret0	70307	1			T3	128		T5	36		T6	599
no_err	hw_cfg	50968	1			T1	45		T3	78		T5	50
no_err	owner_sw_cfg	46986	1			T1	4		T3	100		T5	45
no_err	creator_sw_cfg	46979	1			T1	4		T3	112		T5	36
no_err	vendor_test	58351	1			T3	84		T5	51		T6	93

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded