Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::power_on_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
creator_sw_lock	2	0	2	100.00	100	1	1	2
hw_cfg_lock	2	0	2	100.00	100	1	1	2
lc_esc	2	0	2	100.00	100	1	1	2
owner_sw_lock	2	0	2	100.00	100	1	1	2
secret0_lock	2	0	2	100.00	100	1	1	2
secret1_lock	2	0	2	100.00	100	1	1	2
secret2_lock	2	0	2	100.00	100	1	1	2
vendor_sw_lock	2	0	2	100.00	100	1	1	2

Summary for Variable creator_sw_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for creator_sw_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7407

1

T98

2

T177

2

T101

2

auto[1]

5422

1

T5

10

T7

19

T8

70

---

Summary for Variable hw_cfg_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_cfg_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7734

1

T98

2

T177

2

T101

2

auto[1]

5095

1

T1

2

T5

8

T7

17

---

Summary for Variable lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12765

1

T98

2

T177

2

T101

2

auto[1]

64

1

T89

1

T172

1

T369

1

---

Summary for Variable owner_sw_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for owner_sw_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7777

1

T98

2

T177

2

T101

2

auto[1]

5052

1

T5

10

T7

19

T8

55

---

Summary for Variable secret0_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret0_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7691

1

T98

2

T177

2

T101

2

auto[1]

5138

1

T5

10

T7

19

T8

58

---

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7657

1

T98

2

T177

2

T101

2

auto[1]

5172

1

T5

6

T7

13

T8

62

---

Summary for Variable secret2_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret2_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8988

1

T98

2

T177

2

T101

2

auto[1]

3841

1

T7

17

T8

53

T22

61

---

Summary for Variable vendor_sw_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for vendor_sw_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11150

1

T98

2

T177

2

T101

2

auto[1]

1679

1

T5

4

T8

8

T22

41