Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_prog_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_lc_esc	2	0	2	100.00	100	1	1	0
lc_prog_req_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_prog_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23500

1

T1

216

T3

2

T4

9

auto[1]

812

1

T1

6

T4

5

T6

2

---

Summary for Variable lc_prog_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23360

1

T1

214

T3

2

T4

5

auto[1]

952

1

T1

8

T4

9

T6

1

---

Summary for Variable lc_prog_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lc_prog_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

24278

1

T1

222

T3

2

T4

14

lc_esc_on

34

1

T14

1

T13

1

T357

1

---

Summary for Variable lc_prog_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22700

1

T1

214

T3

2

T4

10

auto[1]

1612

1

T1

8

T4

4

T6

2

---

Summary for Variable lc_prog_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12969

1

T1

122

T3

1

T4

7

auto[1]

11343

1

T1

100

T3

1

T4

7

---

Summary for Variable lc_prog_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22841

1

T1

211

T3

2

T4

13

auto[1]

1471

1

T1

11

T4

1

T6

2

---

Summary for Variable lc_prog_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22913

1

T1

211

T3

2

T4

14

auto[1]

1399

1

T1

11

T6

3

T11

4