Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.28 92.55 91.52 92.48 91.27 93.44 96.53 95.19


Total tests in report: 1337
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
48.41 48.41 68.18 68.18 57.57 57.57 72.83 72.83 0.00 0.00 65.13 65.13 45.40 45.40 29.79 29.79 /workspace/coverage/default/41.otp_ctrl_stress_all.2753504398
81.32 32.91 89.10 20.92 77.47 19.90 81.59 8.76 91.27 91.27 82.03 16.90 91.10 45.70 56.71 26.92 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.4262611353
84.58 3.26 90.19 1.10 83.69 6.22 86.38 4.79 91.27 0.00 87.43 5.40 91.18 0.08 61.94 5.23 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4015073005
85.98 1.40 90.46 0.27 83.93 0.24 89.21 2.83 91.27 0.00 87.97 0.53 91.25 0.08 67.76 5.82 /workspace/coverage/default/7.otp_ctrl_stress_all.1119149590
87.18 1.21 90.46 0.00 83.93 0.00 89.22 0.01 91.27 0.00 87.97 0.00 91.33 0.08 76.12 8.35 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2246633960
88.04 0.85 90.65 0.19 86.21 2.28 89.55 0.33 91.27 0.00 89.25 1.28 91.70 0.38 77.64 1.52 /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1366380584
88.77 0.73 90.80 0.15 86.78 0.57 89.95 0.40 91.27 0.00 90.64 1.39 93.97 2.26 77.97 0.34 /workspace/coverage/default/4.otp_ctrl_sec_cm.2821622957
89.34 0.57 90.93 0.13 87.30 0.52 89.97 0.01 91.27 0.00 90.86 0.21 94.12 0.15 80.93 2.95 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.984032689
89.77 0.43 91.12 0.19 87.79 0.49 90.03 0.06 91.27 0.00 91.18 0.32 94.12 0.00 82.87 1.94 /workspace/coverage/default/24.otp_ctrl_check_fail.2702411428
90.14 0.37 91.12 0.00 87.92 0.14 90.83 0.80 91.27 0.00 91.23 0.05 94.12 0.00 84.47 1.60 /workspace/coverage/default/48.otp_ctrl_stress_all.3502308731
90.41 0.27 91.12 0.00 88.08 0.16 90.93 0.10 91.27 0.00 91.23 0.00 94.42 0.30 85.82 1.35 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2511399225
90.67 0.26 91.12 0.00 88.14 0.05 90.93 0.00 91.27 0.00 91.23 0.00 94.42 0.00 87.59 1.77 /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2938695436
90.87 0.20 91.12 0.00 88.19 0.05 91.42 0.49 91.27 0.00 91.23 0.00 94.42 0.00 88.44 0.84 /workspace/coverage/default/38.otp_ctrl_stress_all.3008638538
91.04 0.17 91.12 0.00 88.19 0.00 91.42 0.00 91.27 0.00 91.23 0.00 95.48 1.06 88.61 0.17 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.171110091
91.22 0.17 91.29 0.17 88.36 0.16 91.50 0.08 91.27 0.00 91.55 0.32 95.70 0.23 88.86 0.25 /workspace/coverage/default/4.otp_ctrl_init_fail.2929181223
91.39 0.17 91.35 0.06 88.87 0.52 91.55 0.05 91.27 0.00 91.60 0.05 95.78 0.08 89.28 0.42 /workspace/coverage/default/30.otp_ctrl_macro_errs.4193745915
91.55 0.17 91.44 0.09 89.33 0.46 91.86 0.31 91.27 0.00 91.82 0.21 95.78 0.00 89.37 0.08 /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.3808239773
91.70 0.15 91.44 0.00 89.41 0.08 91.86 0.00 91.27 0.00 91.82 0.00 96.08 0.30 90.04 0.68 /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.3526959072
91.83 0.13 91.44 0.00 89.44 0.03 91.87 0.01 91.27 0.00 91.82 0.00 96.08 0.00 90.89 0.84 /workspace/coverage/default/36.otp_ctrl_stress_all.918936570
91.95 0.12 91.60 0.15 89.58 0.14 91.87 0.00 91.27 0.00 92.03 0.21 96.15 0.08 91.14 0.25 /workspace/coverage/default/0.otp_ctrl_check_fail.1246458063
92.03 0.08 91.73 0.13 89.69 0.11 91.87 0.00 91.27 0.00 92.30 0.27 96.15 0.00 91.22 0.08 /workspace/coverage/default/214.otp_ctrl_init_fail.505474690
92.11 0.08 91.77 0.04 89.82 0.14 91.87 0.00 91.27 0.00 92.41 0.11 96.15 0.00 91.48 0.25 /workspace/coverage/default/38.otp_ctrl_check_fail.4250870047
92.18 0.07 91.82 0.06 89.96 0.14 91.95 0.08 91.27 0.00 92.51 0.11 96.15 0.00 91.56 0.08 /workspace/coverage/default/121.otp_ctrl_init_fail.3375369573
92.24 0.06 91.88 0.06 90.01 0.05 91.97 0.02 91.27 0.00 92.57 0.05 96.23 0.08 91.73 0.17 /workspace/coverage/default/23.otp_ctrl_macro_errs.273534066
92.30 0.06 91.88 0.00 90.01 0.00 91.97 0.00 91.27 0.00 92.57 0.00 96.23 0.00 92.15 0.42 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2272865193
92.36 0.06 91.88 0.00 90.01 0.00 91.97 0.00 91.27 0.00 92.57 0.00 96.23 0.00 92.57 0.42 /workspace/coverage/default/42.otp_ctrl_regwen.2569003364
92.41 0.06 91.88 0.00 90.07 0.05 91.97 0.00 91.27 0.00 92.57 0.00 96.23 0.00 92.91 0.34 /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.3426059755
92.47 0.05 91.88 0.00 90.12 0.05 91.97 0.00 91.27 0.00 92.57 0.00 96.38 0.15 93.08 0.17 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.250429427
92.52 0.05 91.94 0.06 90.17 0.05 92.10 0.13 91.27 0.00 92.67 0.11 96.38 0.00 93.08 0.00 /workspace/coverage/default/260.otp_ctrl_init_fail.2711465294
92.56 0.05 91.94 0.00 90.17 0.00 92.10 0.01 91.27 0.00 92.67 0.00 96.38 0.00 93.42 0.34 /workspace/coverage/default/29.otp_ctrl_stress_all.3457733378
92.61 0.05 92.28 0.34 90.17 0.00 92.10 0.00 91.27 0.00 92.67 0.00 96.38 0.00 93.42 0.00 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2729102865
92.66 0.05 92.33 0.06 90.23 0.05 92.10 0.00 91.27 0.00 92.73 0.05 96.38 0.00 93.59 0.17 /workspace/coverage/default/48.otp_ctrl_check_fail.1706231277
92.70 0.04 92.33 0.00 90.50 0.27 92.10 0.00 91.27 0.00 92.73 0.00 96.38 0.00 93.59 0.00 /workspace/coverage/default/11.otp_ctrl_alert_test.2423067766
92.74 0.04 92.33 0.00 90.50 0.00 92.10 0.00 91.27 0.00 92.73 0.00 96.38 0.00 93.84 0.25 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.201463536
92.77 0.04 92.39 0.06 90.53 0.03 92.13 0.03 91.27 0.00 92.78 0.05 96.38 0.00 93.92 0.08 /workspace/coverage/default/160.otp_ctrl_init_fail.3434126383
92.81 0.04 92.45 0.06 90.55 0.03 92.16 0.03 91.27 0.00 92.83 0.05 96.38 0.00 94.01 0.08 /workspace/coverage/default/41.otp_ctrl_init_fail.2656524842
92.84 0.03 92.50 0.06 90.61 0.05 92.18 0.02 91.27 0.00 92.94 0.11 96.38 0.00 94.01 0.00 /workspace/coverage/default/94.otp_ctrl_init_fail.3161258825
92.87 0.03 92.56 0.06 90.64 0.03 92.19 0.01 91.27 0.00 92.99 0.05 96.38 0.00 94.09 0.08 /workspace/coverage/default/84.otp_ctrl_init_fail.4270748991
92.91 0.03 92.62 0.06 90.69 0.05 92.19 0.00 91.27 0.00 93.10 0.11 96.38 0.00 94.09 0.00 /workspace/coverage/default/108.otp_ctrl_init_fail.3614227829
92.94 0.03 92.64 0.02 90.74 0.05 92.19 0.00 91.27 0.00 93.16 0.05 96.38 0.00 94.18 0.08 /workspace/coverage/default/26.otp_ctrl_check_fail.257852719
92.96 0.03 92.64 0.00 90.77 0.03 92.19 0.00 91.27 0.00 93.16 0.00 96.38 0.00 94.35 0.17 /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3627345920
92.99 0.02 92.64 0.00 90.77 0.00 92.19 0.00 91.27 0.00 93.16 0.00 96.38 0.00 94.51 0.17 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3865084086
93.01 0.02 92.64 0.00 90.77 0.00 92.19 0.00 91.27 0.00 93.16 0.00 96.38 0.00 94.68 0.17 /workspace/coverage/default/14.otp_ctrl_regwen.2980880261
93.04 0.02 92.64 0.00 90.77 0.00 92.19 0.00 91.27 0.00 93.16 0.00 96.38 0.00 94.85 0.17 /workspace/coverage/default/17.otp_ctrl_regwen.892575848
93.06 0.02 92.64 0.00 90.77 0.00 92.19 0.00 91.27 0.00 93.16 0.00 96.46 0.08 94.94 0.08 /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3230596308
93.08 0.02 92.67 0.04 90.83 0.05 92.19 0.00 91.27 0.00 93.21 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/180.otp_ctrl_init_fail.759666901
93.10 0.02 92.73 0.06 90.85 0.03 92.19 0.00 91.27 0.00 93.26 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/210.otp_ctrl_init_fail.2416848419
93.12 0.02 92.77 0.04 90.88 0.03 92.20 0.01 91.27 0.00 93.32 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/126.otp_ctrl_init_fail.3425485226
93.13 0.02 92.81 0.04 90.91 0.03 92.20 0.00 91.27 0.00 93.37 0.05 96.46 0.00 94.94 0.00 /workspace/coverage/default/102.otp_ctrl_init_fail.1313105160
93.15 0.01 92.81 0.00 90.91 0.00 92.30 0.10 91.27 0.00 93.37 0.00 96.46 0.00 94.94 0.00 /workspace/coverage/default/293.otp_ctrl_init_fail.1244813585
93.16 0.01 92.81 0.00 90.91 0.00 92.31 0.01 91.27 0.00 93.37 0.00 96.46 0.00 95.02 0.08 /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.796676427
93.17 0.01 92.81 0.00 90.99 0.08 92.31 0.01 91.27 0.00 93.37 0.00 96.46 0.00 95.02 0.00 /workspace/coverage/default/36.otp_ctrl_check_fail.4266251468
93.19 0.01 92.81 0.00 90.99 0.00 92.31 0.00 91.27 0.00 93.37 0.00 96.46 0.00 95.11 0.08 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3520460438
93.20 0.01 92.81 0.00 90.99 0.00 92.31 0.00 91.27 0.00 93.37 0.00 96.46 0.00 95.19 0.08 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2307460940
93.21 0.01 92.81 0.00 91.07 0.08 92.31 0.00 91.27 0.00 93.37 0.00 96.46 0.00 95.19 0.00 /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.611266492
93.22 0.01 92.81 0.00 91.07 0.00 92.31 0.00 91.27 0.00 93.37 0.00 96.53 0.08 95.19 0.00 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1792720895
93.23 0.01 92.83 0.02 91.12 0.05 92.31 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3377469922
93.24 0.01 92.83 0.00 91.18 0.05 92.31 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/14.otp_ctrl_check_fail.4149279280
93.25 0.01 92.83 0.00 91.23 0.05 92.31 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/17.otp_ctrl_stress_all.1501850420
93.25 0.01 92.83 0.00 91.23 0.00 92.35 0.04 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/116.otp_ctrl_init_fail.2700860640
93.26 0.01 92.83 0.00 91.23 0.00 92.39 0.04 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/241.otp_ctrl_init_fail.917328492
93.26 0.01 92.86 0.04 91.23 0.00 92.39 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/3.otp_ctrl_sec_cm.3601364876
93.27 0.01 92.86 0.00 91.23 0.00 92.42 0.03 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/202.otp_ctrl_init_fail.1141435784
93.27 0.01 92.86 0.00 91.23 0.00 92.45 0.03 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/44.otp_ctrl_stress_all.2753763753
93.28 0.01 92.86 0.00 91.26 0.03 92.45 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.280868292
93.28 0.01 92.86 0.00 91.29 0.03 92.45 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.811434535
93.28 0.01 92.86 0.00 91.31 0.03 92.45 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.262967061
93.29 0.01 92.86 0.00 91.34 0.03 92.45 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/10.otp_ctrl_dai_errs.3353867087
93.29 0.01 92.86 0.00 91.37 0.03 92.45 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/171.otp_ctrl_init_fail.1218360080
93.30 0.01 92.86 0.00 91.40 0.03 92.45 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.2615112221
93.30 0.01 92.88 0.02 91.40 0.00 92.45 0.00 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.769624346
93.30 0.01 92.88 0.00 91.40 0.00 92.46 0.01 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/236.otp_ctrl_init_fail.1508003565
93.30 0.01 92.88 0.00 91.40 0.00 92.47 0.01 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/114.otp_ctrl_init_fail.1078949250
93.30 0.01 92.88 0.00 91.40 0.00 92.48 0.01 91.27 0.00 93.37 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/150.otp_ctrl_init_fail.1650954294

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2001085733
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3564925728
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1740957050
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1340930185
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.4227168452
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2395531088
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1412504589
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1028824224
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1750697973
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.410451828
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1843763641
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.545275996
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.280106050
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.826447629
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.402624610
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3088513475
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4134640946
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3072888847
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2365582844
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3002791938
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.4145746308
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2630562266
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.289639880
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.608357735
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3760382477
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.61763015
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.815879034
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.446672047
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1003206629
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3317841479
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1826059416
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.845920197
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2781521327
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4288545349
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2556985816
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3819254541
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4140678575
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1029840489
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2579014140
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1760963476
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2355491487
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2614786863
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1984838089
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.152527094
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.596109260
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3043457724
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3043310944
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2909508502
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3440249267
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2067417664
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4133513865
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.4145086282
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2646166890
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2777847726
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.769063925
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2020515108
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2261652065
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.3873466575
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3349932680
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.750858480
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1671095355
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3855052868
/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3662945084
/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1661887615
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2627778814
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.4274944598
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1225952603
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.851310838
/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3086719977
/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3711454343
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3616384441
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/workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.1656251481
/workspace/coverage/default/95.otp_ctrl_init_fail.2979845224
/workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.1954479323
/workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.538843406
/workspace/coverage/default/96.otp_ctrl_init_fail.3372972363
/workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.4162972962
/workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2506562084
/workspace/coverage/default/97.otp_ctrl_init_fail.2101489896
/workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.4130920011
/workspace/coverage/default/98.otp_ctrl_init_fail.2040310221
/workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1647133331
/workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.2615206606
/workspace/coverage/default/99.otp_ctrl_init_fail.1254543653
/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.4172456969
/workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3830802004



Total test records in report: 1337
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T18 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.4262611353 Jan 10 01:23:38 PM PST 24 Jan 10 01:23:50 PM PST 24 190031536 ps
T97 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2001085733 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:45 PM PST 24 180383568 ps
T98 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.770779046 Jan 10 01:23:45 PM PST 24 Jan 10 01:23:57 PM PST 24 155940533 ps
T99 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1750697973 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:50 PM PST 24 1138721183 ps
T104 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.3564925728 Jan 10 01:23:38 PM PST 24 Jan 10 01:23:49 PM PST 24 87180646 ps
T100 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1551870708 Jan 10 01:23:53 PM PST 24 Jan 10 01:24:03 PM PST 24 135247247 ps
T101 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3520460438 Jan 10 01:23:31 PM PST 24 Jan 10 01:23:38 PM PST 24 582923000 ps
T102 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3120561612 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:44 PM PST 24 77798841 ps
T103 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.984032689 Jan 10 01:23:44 PM PST 24 Jan 10 01:23:55 PM PST 24 57018196 ps
T105 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.4015073005 Jan 10 01:23:34 PM PST 24 Jan 10 01:23:48 PM PST 24 2165494400 ps
T106 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.410451828 Jan 10 01:23:17 PM PST 24 Jan 10 01:23:40 PM PST 24 448725341 ps
T194 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2212774320 Jan 10 01:23:35 PM PST 24 Jan 10 01:23:41 PM PST 24 48809159 ps
T154 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.847956692 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:03 PM PST 24 276900241 ps
T224 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.1842953653 Jan 10 01:23:43 PM PST 24 Jan 10 01:23:54 PM PST 24 129444445 ps
T107 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3523190075 Jan 10 01:23:36 PM PST 24 Jan 10 01:23:43 PM PST 24 172758358 ps
T155 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.3457240444 Jan 10 01:23:50 PM PST 24 Jan 10 01:24:03 PM PST 24 217145103 ps
T206 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3366620324 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:02 PM PST 24 648852674 ps
T196 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.250429427 Jan 10 01:23:52 PM PST 24 Jan 10 01:24:03 PM PST 24 109207083 ps
T207 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.171110091 Jan 10 01:23:23 PM PST 24 Jan 10 01:23:35 PM PST 24 40237060 ps
T209 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2653064903 Jan 10 01:23:40 PM PST 24 Jan 10 01:23:49 PM PST 24 854344638 ps
T156 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3373343127 Jan 10 01:23:54 PM PST 24 Jan 10 01:24:06 PM PST 24 719367686 ps
T296 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.239884382 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:02 PM PST 24 68001145 ps
T362 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2118275028 Jan 10 01:23:50 PM PST 24 Jan 10 01:24:01 PM PST 24 517820397 ps
T157 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.1028824224 Jan 10 01:23:23 PM PST 24 Jan 10 01:23:37 PM PST 24 119401209 ps
T158 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1029840489 Jan 10 01:23:36 PM PST 24 Jan 10 01:23:43 PM PST 24 110815886 ps
T245 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2246633960 Jan 10 01:23:24 PM PST 24 Jan 10 01:23:39 PM PST 24 425342328 ps
T238 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.891287727 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:47 PM PST 24 45316767 ps
T176 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2511399225 Jan 10 01:23:20 PM PST 24 Jan 10 01:23:51 PM PST 24 3334173810 ps
T177 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.57929525 Jan 10 01:23:24 PM PST 24 Jan 10 01:23:51 PM PST 24 1262903089 ps
T159 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.545275996 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:49 PM PST 24 196785011 ps
T239 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1760963476 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:45 PM PST 24 39367986 ps
T240 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.588105107 Jan 10 01:23:34 PM PST 24 Jan 10 01:23:40 PM PST 24 45150324 ps
T210 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2119711896 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:53 PM PST 24 428720151 ps
T208 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.769063925 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:59 PM PST 24 1370911399 ps
T160 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4140678575 Jan 10 01:23:36 PM PST 24 Jan 10 01:23:45 PM PST 24 311350822 ps
T161 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2437295873 Jan 10 01:23:35 PM PST 24 Jan 10 01:23:42 PM PST 24 69513213 ps
T227 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2578687263 Jan 10 01:23:45 PM PST 24 Jan 10 01:23:56 PM PST 24 147088616 ps
T228 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2187441206 Jan 10 01:23:55 PM PST 24 Jan 10 01:24:05 PM PST 24 52257542 ps
T229 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.70364529 Jan 10 01:23:25 PM PST 24 Jan 10 01:23:36 PM PST 24 37979965 ps
T230 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1304132270 Jan 10 01:23:43 PM PST 24 Jan 10 01:23:54 PM PST 24 561324895 ps
T297 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2259856927 Jan 10 01:23:55 PM PST 24 Jan 10 01:24:06 PM PST 24 557413425 ps
T241 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2261652065 Jan 10 01:23:46 PM PST 24 Jan 10 01:23:58 PM PST 24 38193445 ps
T162 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2909508502 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:57 PM PST 24 162115817 ps
T211 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2482289032 Jan 10 01:23:22 PM PST 24 Jan 10 01:23:35 PM PST 24 43637318 ps
T212 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.912702524 Jan 10 01:23:24 PM PST 24 Jan 10 01:23:35 PM PST 24 43718445 ps
T197 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3616384441 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:07 PM PST 24 312915817 ps
T363 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.2395531088 Jan 10 01:23:33 PM PST 24 Jan 10 01:23:39 PM PST 24 499764116 ps
T246 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3500303694 Jan 10 01:23:52 PM PST 24 Jan 10 01:24:05 PM PST 24 357601492 ps
T195 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2272865193 Jan 10 01:23:35 PM PST 24 Jan 10 01:23:57 PM PST 24 2277202736 ps
T255 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.501383146 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:49 PM PST 24 997453878 ps
T204 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.3377469922 Jan 10 01:23:25 PM PST 24 Jan 10 01:23:38 PM PST 24 204533348 ps
T247 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.524579479 Jan 10 01:23:36 PM PST 24 Jan 10 01:23:47 PM PST 24 3515229975 ps
T256 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2348218406 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:01 PM PST 24 48168995 ps
T257 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.750858480 Jan 10 01:23:45 PM PST 24 Jan 10 01:24:13 PM PST 24 1302582586 ps
T364 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.255884600 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:51 PM PST 24 504723710 ps
T365 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2778917792 Jan 10 01:23:44 PM PST 24 Jan 10 01:23:55 PM PST 24 135537392 ps
T199 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.602795616 Jan 10 01:23:22 PM PST 24 Jan 10 01:23:39 PM PST 24 594023502 ps
T248 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2020515108 Jan 10 01:23:40 PM PST 24 Jan 10 01:23:49 PM PST 24 964165132 ps
T263 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3086719977 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:02 PM PST 24 74104256 ps
T264 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.852928317 Jan 10 01:23:25 PM PST 24 Jan 10 01:23:36 PM PST 24 72048014 ps
T213 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.567806478 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:45 PM PST 24 37381123 ps
T231 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3865084086 Jan 10 01:23:23 PM PST 24 Jan 10 01:23:52 PM PST 24 1253852036 ps
T366 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.201463536 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:01 PM PST 24 80682236 ps
T367 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.289639880 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:48 PM PST 24 243796199 ps
T368 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3043457724 Jan 10 01:23:38 PM PST 24 Jan 10 01:23:46 PM PST 24 136636834 ps
T200 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2288219744 Jan 10 01:23:34 PM PST 24 Jan 10 01:23:40 PM PST 24 167131297 ps
T108 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1740957050 Jan 10 01:23:38 PM PST 24 Jan 10 01:23:46 PM PST 24 90965752 ps
T298 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.4274944598 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:09 PM PST 24 603498527 ps
T242 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1661887615 Jan 10 01:23:49 PM PST 24 Jan 10 01:24:01 PM PST 24 226743228 ps
T369 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3936354792 Jan 10 01:23:54 PM PST 24 Jan 10 01:24:04 PM PST 24 73138501 ps
T201 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.3009430516 Jan 10 01:23:50 PM PST 24 Jan 10 01:24:03 PM PST 24 1055978746 ps
T370 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.725537920 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:44 PM PST 24 133193804 ps
T371 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.268631551 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:02 PM PST 24 40278380 ps
T299 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2307460940 Jan 10 01:23:42 PM PST 24 Jan 10 01:24:20 PM PST 24 19140101758 ps
T372 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1003206629 Jan 10 01:23:41 PM PST 24 Jan 10 01:23:50 PM PST 24 583468336 ps
T243 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3088513475 Jan 10 01:23:36 PM PST 24 Jan 10 01:23:44 PM PST 24 98835890 ps
T244 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3819254541 Jan 10 01:23:38 PM PST 24 Jan 10 01:23:46 PM PST 24 120177131 ps
T373 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4285943170 Jan 10 01:23:55 PM PST 24 Jan 10 01:24:06 PM PST 24 67623310 ps
T249 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2646166890 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:52 PM PST 24 85243694 ps
T374 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3374781399 Jan 10 01:23:46 PM PST 24 Jan 10 01:23:57 PM PST 24 51446851 ps
T375 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.4288545349 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:48 PM PST 24 41846231 ps
T376 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.402624610 Jan 10 01:23:21 PM PST 24 Jan 10 01:23:34 PM PST 24 37001932 ps
T377 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2556985816 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:45 PM PST 24 111314367 ps
T198 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2627778814 Jan 10 01:23:45 PM PST 24 Jan 10 01:24:02 PM PST 24 271280994 ps
T378 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3760382477 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:51 PM PST 24 518404259 ps
T214 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.446672047 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:51 PM PST 24 59267533 ps
T250 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2203454912 Jan 10 01:23:43 PM PST 24 Jan 10 01:23:54 PM PST 24 219720955 ps
T379 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.807960564 Jan 10 01:23:34 PM PST 24 Jan 10 01:23:39 PM PST 24 59774406 ps
T380 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3595838247 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:45 PM PST 24 37989776 ps
T381 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.608357735 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:44 PM PST 24 49713043 ps
T382 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3783444660 Jan 10 01:23:38 PM PST 24 Jan 10 01:23:47 PM PST 24 68404101 ps
T300 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1984838089 Jan 10 01:23:38 PM PST 24 Jan 10 01:24:06 PM PST 24 4704325131 ps
T383 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.647228419 Jan 10 01:23:40 PM PST 24 Jan 10 01:23:49 PM PST 24 529963962 ps
T384 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3224192165 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:47 PM PST 24 40438497 ps
T251 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3317841479 Jan 10 01:23:41 PM PST 24 Jan 10 01:23:51 PM PST 24 97177163 ps
T385 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.4049213303 Jan 10 01:23:41 PM PST 24 Jan 10 01:23:49 PM PST 24 141355159 ps
T386 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.815879034 Jan 10 01:23:43 PM PST 24 Jan 10 01:24:05 PM PST 24 2405990229 ps
T387 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.139438597 Jan 10 01:23:45 PM PST 24 Jan 10 01:23:56 PM PST 24 41013836 ps
T388 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3103973048 Jan 10 01:23:38 PM PST 24 Jan 10 01:23:47 PM PST 24 110376657 ps
T215 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.4133513865 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:48 PM PST 24 88439708 ps
T389 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3243494603 Jan 10 01:23:23 PM PST 24 Jan 10 01:23:36 PM PST 24 149765769 ps
T202 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.262967061 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:10 PM PST 24 1237399589 ps
T390 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1412504589 Jan 10 01:23:22 PM PST 24 Jan 10 01:23:35 PM PST 24 233113617 ps
T391 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1671095355 Jan 10 01:23:50 PM PST 24 Jan 10 01:24:02 PM PST 24 144852394 ps
T392 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.280868292 Jan 10 01:23:42 PM PST 24 Jan 10 01:23:55 PM PST 24 2243838171 ps
T393 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.4257530722 Jan 10 01:23:24 PM PST 24 Jan 10 01:23:35 PM PST 24 43690386 ps
T394 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3368822765 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:02 PM PST 24 563053951 ps
T395 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3349932680 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:54 PM PST 24 2373195869 ps
T396 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.4145086282 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:44 PM PST 24 38876912 ps
T397 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2122806353 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:02 PM PST 24 146426136 ps
T398 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1592103872 Jan 10 01:23:51 PM PST 24 Jan 10 01:24:11 PM PST 24 2261401576 ps
T399 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.61763015 Jan 10 01:23:50 PM PST 24 Jan 10 01:24:01 PM PST 24 206258662 ps
T400 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3885374732 Jan 10 01:23:55 PM PST 24 Jan 10 01:24:05 PM PST 24 136539960 ps
T401 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2704536039 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:48 PM PST 24 41744911 ps
T216 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1792720895 Jan 10 01:23:12 PM PST 24 Jan 10 01:23:31 PM PST 24 41051638 ps
T402 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.152527094 Jan 10 01:23:36 PM PST 24 Jan 10 01:23:43 PM PST 24 94612548 ps
T403 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3653637851 Jan 10 01:23:37 PM PST 24 Jan 10 01:23:46 PM PST 24 192270727 ps
T404 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2355491487 Jan 10 01:23:43 PM PST 24 Jan 10 01:23:53 PM PST 24 177558132 ps
T109 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1843763641 Jan 10 01:23:26 PM PST 24 Jan 10 01:23:37 PM PST 24 381383357 ps
T217 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.851310838 Jan 10 01:23:54 PM PST 24 Jan 10 01:24:05 PM PST 24 43189371 ps
T302 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2127596026 Jan 10 01:23:45 PM PST 24 Jan 10 01:24:15 PM PST 24 3652847900 ps
T361 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2365582844 Jan 10 01:23:39 PM PST 24 Jan 10 01:23:49 PM PST 24 200691337 ps
T405 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1752190459 Jan 10 01:23:52 PM PST 24 Jan 10 01:24:02 PM PST 24 40878209 ps
T406 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.4227168452 Jan 10 01:23:36 PM PST 24 Jan 10 01:23:41 PM PST 24 41024497 ps
T407 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1951227448 Jan 10 01:23:50 PM PST 24 Jan 10 01:24:03 PM PST 24 106439513 ps
T301 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.4095642326 Jan 10 01:23:50 PM PST 24 Jan 10 01:24:19 PM PST 24 2446232433 ps
T408 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2067417664 Jan 10 01:23:48 PM PST 24 Jan 10 01:24:01 PM PST 24 1064514949 ps
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