Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	52956	1			T4	192		T11	105		T57	6
access_err	82015	1			T1	1341		T2	13		T4	25
write_blank_err	423	1			T1	2		T2	3		T11	3
ecc_uncorr_err	69565	1			T1	688		T2	440		T10	3
ecc_corr_err	1260	1			T10	5		T15	23		T112	3
no_err	387502	1			T1	4245		T2	556		T3	168

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	42858	1			T1	478		T4	14		T6	18
secret2	66396	1			T1	750		T2	22		T3	24
secret1	78839	1			T1	1594		T2	18		T3	28
secret0	110820	1			T1	498		T2	894		T3	22
hw_cfg	78232	1			T1	958		T2	16		T3	16
owner_sw_cfg	59178	1			T1	740		T2	26		T3	38
creator_sw_cfg	68345	1			T1	578		T2	16		T3	24
vendor_test	89053	1			T1	680		T2	20		T3	16

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	2409	1			T153	265		T273	65		T285	159
fsm_err	secret2	4037	1			T286	207		T287	1		T288	161
fsm_err	secret1	6214	1			T11	105		T33	501		T289	49
fsm_err	secret0	5347	1			T16	211		T290	9		T291	180
fsm_err	hw_cfg	6047	1			T90	276		T169	154		T292	272
fsm_err	owner_sw_cfg	2167	1			T15	20		T293	20		T111	37
fsm_err	creator_sw_cfg	5151	1			T4	192		T91	282		T112	94
fsm_err	vendor_test	21584	1			T57	6		T13	629		T89	323
access_err	lc_or_oob	19019	1			T1	239		T4	7		T6	9
access_err	secret2	13859	1			T1	244		T2	11		T4	8
access_err	secret1	7154	1			T1	161		T6	3		T10	3
access_err	secret0	5634	1			T1	127		T4	4		T6	1
access_err	hw_cfg	3217	1			T1	54		T6	7		T10	2
access_err	owner_sw_cfg	12191	1			T1	206		T6	15		T11	58
access_err	creator_sw_cfg	12811	1			T1	181		T2	2		T4	5
access_err	vendor_test	8130	1			T1	129		T4	1		T6	7
write_blank_err	secret2	20	1			T280	1		T294	1		T295	1
write_blank_err	secret1	30	1			T1	1		T13	1		T279	1
write_blank_err	secret0	89	1			T2	1		T85	1		T114	1
write_blank_err	hw_cfg	34	1			T1	1		T11	1		T170	1
write_blank_err	owner_sw_cfg	81	1			T12	1		T170	1		T120	1
write_blank_err	creator_sw_cfg	140	1			T2	2		T11	2		T278	4
write_blank_err	vendor_test	29	1			T170	1		T278	2		T120	1
ecc_uncorr_err	secret2	7049	1			T115	73		T280	362		T295	591
ecc_uncorr_err	secret1	13276	1			T1	486		T15	60		T13	92
ecc_uncorr_err	secret0	32501	1			T2	440		T15	35		T113	64
ecc_uncorr_err	hw_cfg	12680	1			T1	202		T11	593		T15	12
ecc_uncorr_err	owner_sw_cfg	1210	1			T15	42		T125	92		T111	37
ecc_uncorr_err	creator_sw_cfg	2849	1			T10	3		T15	88		T112	57
ecc_corr_err	secret2	111	1			T15	1		T54	2		T36	1
ecc_corr_err	secret1	180	1			T10	1		T29	2		T276	16
ecc_corr_err	secret0	197	1			T15	1		T120	1		T54	4
ecc_corr_err	hw_cfg	288	1			T15	12		T112	1		T120	3
ecc_corr_err	owner_sw_cfg	93	1			T10	2		T54	7		T36	1
ecc_corr_err	creator_sw_cfg	163	1			T15	2		T54	3		T29	2
ecc_corr_err	vendor_test	228	1			T10	2		T15	7		T112	2
no_err	lc_or_oob	21430	1			T1	239		T4	7		T6	9
no_err	secret2	41320	1			T1	506		T2	11		T3	24
no_err	secret1	51985	1			T1	946		T2	18		T3	28
no_err	secret0	67052	1			T1	371		T2	453		T3	22
no_err	hw_cfg	55966	1			T1	701		T2	16		T3	16
no_err	owner_sw_cfg	43436	1			T1	534		T2	26		T3	38
no_err	creator_sw_cfg	47231	1			T1	397		T2	12		T3	24
no_err	vendor_test	59082	1			T1	551		T2	20		T3	16

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded