Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	53222	1			T2	14		T4	62		T7	74
access_err	83291	1			T1	459		T2	7		T3	11
write_blank_err	441	1			T8	3		T130	1		T35	11
ecc_uncorr_err	71250	1			T2	79		T4	116		T8	322
ecc_corr_err	1366	1			T2	14		T4	11		T57	11
no_err	382900	1			T1	875		T2	184		T3	77

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	45879	1			T1	168		T2	10		T3	8
secret2	74285	1			T1	138		T2	42		T3	12
secret1	92103	1			T1	144		T2	46		T3	10
secret0	107528	1			T1	176		T2	50		T3	8
hw_cfg	63807	1			T1	162		T2	26		T3	18
owner_sw_cfg	68185	1			T1	202		T2	32		T3	22
creator_sw_cfg	63650	1			T1	210		T2	34		T3	6
vendor_test	77033	1			T1	134		T2	58		T3	4

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	3421	1			T12	48		T303	442		T304	20
fsm_err	secret2	5589	1			T90	149		T17	137		T201	322
fsm_err	secret1	7215	1			T131	98		T111	53		T68	188
fsm_err	secret0	5575	1			T94	77		T202	518		T34	219
fsm_err	hw_cfg	5605	1			T176	77		T305	65		T180	27
fsm_err	owner_sw_cfg	5400	1			T127	117		T182	63		T95	24
fsm_err	creator_sw_cfg	4335	1			T4	62		T7	74		T17	186
fsm_err	vendor_test	16082	1			T2	14		T11	498		T57	74
access_err	lc_or_oob	19517	1			T1	84		T2	5		T3	4
access_err	secret2	14263	1			T1	60		T4	5		T8	13
access_err	secret1	7426	1			T1	43		T15	2		T57	26
access_err	secret0	5641	1			T1	55		T7	2		T8	1
access_err	hw_cfg	3443	1			T1	30		T57	7		T35	11
access_err	owner_sw_cfg	12305	1			T1	64		T3	7		T8	7
access_err	creator_sw_cfg	12508	1			T1	89		T8	1		T11	2
access_err	vendor_test	8188	1			T1	34		T2	2		T11	7
write_blank_err	secret2	22	1			T68	1		T306	1		T307	1
write_blank_err	secret1	48	1			T8	1		T35	2		T13	1
write_blank_err	secret0	80	1			T130	1		T35	3		T13	1
write_blank_err	hw_cfg	19	1			T94	1		T95	1		T13	1
write_blank_err	owner_sw_cfg	121	1			T8	2		T35	5		T290	2
write_blank_err	creator_sw_cfg	119	1			T35	1		T13	1		T87	1
write_blank_err	vendor_test	32	1			T300	1		T306	1		T308	1
ecc_uncorr_err	secret2	9984	1			T2	14		T68	596		T128	123
ecc_uncorr_err	secret1	18717	1			T2	12		T4	69		T8	322
ecc_uncorr_err	secret0	31227	1			T2	17		T130	449		T127	96
ecc_uncorr_err	hw_cfg	6403	1			T2	8		T127	113		T94	363
ecc_uncorr_err	owner_sw_cfg	2582	1			T2	12		T127	54		T128	66
ecc_uncorr_err	creator_sw_cfg	2337	1			T2	16		T4	47		T127	44
ecc_corr_err	secret2	117	1			T2	2		T127	1		T113	3
ecc_corr_err	secret1	195	1			T2	2		T4	2		T113	1
ecc_corr_err	secret0	197	1			T2	3		T4	1		T57	1
ecc_corr_err	hw_cfg	266	1			T2	2		T57	2		T127	1
ecc_corr_err	owner_sw_cfg	152	1			T2	3		T57	3		T127	1
ecc_corr_err	creator_sw_cfg	171	1			T4	4		T57	3		T127	3
ecc_corr_err	vendor_test	268	1			T2	2		T4	4		T57	2
no_err	lc_or_oob	22941	1			T1	84		T2	5		T3	4
no_err	secret2	44310	1			T1	78		T2	26		T3	12
no_err	secret1	58502	1			T1	101		T2	32		T3	10
no_err	secret0	64808	1			T1	121		T2	30		T3	8
no_err	hw_cfg	48071	1			T1	132		T2	16		T3	18
no_err	owner_sw_cfg	47625	1			T1	138		T2	17		T3	15
no_err	creator_sw_cfg	44180	1			T1	121		T2	18		T3	6
no_err	vendor_test	52463	1			T1	100		T2	40		T3	4

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded