Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.51 92.55 91.52 92.59 92.68 93.44 96.53 95.27


Total tests in report: 1330
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
42.30 42.30 66.33 66.33 54.70 54.70 48.38 48.38 0.00 0.00 62.03 62.03 45.32 45.32 19.32 19.32 /workspace/coverage/default/18.otp_ctrl_test_access.169030430
71.05 28.75 85.39 19.06 69.03 14.33 54.11 5.73 92.68 92.68 77.01 14.97 89.44 44.12 29.70 10.38 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2621945673
77.73 6.68 88.13 2.74 78.80 9.77 57.49 3.38 92.68 0.00 84.22 7.22 91.70 2.26 51.05 21.35 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.909307981
82.47 4.74 88.30 0.17 80.13 1.33 77.08 19.59 92.68 0.00 84.87 0.64 91.86 0.15 62.36 11.31 /workspace/coverage/default/48.otp_ctrl_stress_all.2162332757
84.68 2.21 88.36 0.06 81.05 0.92 81.38 4.30 92.68 0.00 85.03 0.16 92.46 0.60 71.81 9.45 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1685663464
86.29 1.61 90.18 1.82 82.79 1.74 82.57 1.19 92.68 0.00 87.59 2.57 92.53 0.08 75.70 3.88 /workspace/coverage/default/35.otp_ctrl_macro_errs.210554529
87.41 1.12 90.21 0.04 83.22 0.43 86.44 3.87 92.68 0.00 87.97 0.37 92.53 0.00 78.82 3.12 /workspace/coverage/default/28.otp_ctrl_stress_all.2625862762
88.30 0.89 90.38 0.17 85.42 2.20 86.44 0.00 92.68 0.00 88.98 1.02 92.76 0.23 81.43 2.62 /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.957147177
89.05 0.75 90.54 0.15 86.02 0.60 86.84 0.40 92.68 0.00 90.37 1.39 95.02 2.26 81.86 0.42 /workspace/coverage/default/0.otp_ctrl_sec_cm.1658058926
89.71 0.67 90.82 0.28 87.81 1.79 86.93 0.08 92.68 0.00 90.53 0.16 95.25 0.23 83.97 2.11 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2003396252
90.34 0.62 90.82 0.00 87.87 0.05 89.05 2.12 92.68 0.00 90.53 0.00 95.25 0.00 86.16 2.19 /workspace/coverage/default/5.otp_ctrl_stress_all.189008415
90.71 0.38 91.07 0.25 88.19 0.33 89.86 0.81 92.68 0.00 91.02 0.48 95.25 0.00 86.92 0.76 /workspace/coverage/default/29.otp_ctrl_stress_all.2920680884
90.94 0.23 91.07 0.00 88.19 0.00 89.86 0.00 92.68 0.00 91.02 0.00 95.25 0.00 88.52 1.60 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.661273560
91.13 0.19 91.07 0.00 88.25 0.05 90.26 0.40 92.68 0.00 91.02 0.00 95.25 0.00 89.37 0.84 /workspace/coverage/default/45.otp_ctrl_stress_all.2609015499
91.30 0.18 91.12 0.06 88.74 0.49 90.57 0.31 92.68 0.00 91.07 0.05 95.32 0.08 89.62 0.25 /workspace/coverage/default/6.otp_ctrl_macro_errs.1210274934
91.48 0.17 91.29 0.17 88.90 0.16 90.65 0.08 92.68 0.00 91.39 0.32 95.55 0.23 89.87 0.25 /workspace/coverage/default/102.otp_ctrl_init_fail.112062280
91.61 0.13 91.29 0.00 88.90 0.00 90.65 0.00 92.68 0.00 91.39 0.00 96.30 0.75 90.04 0.17 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.618221252
91.73 0.13 91.29 0.00 89.36 0.46 90.92 0.27 92.68 0.00 91.55 0.16 96.30 0.00 90.04 0.00 /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1204330891
91.86 0.12 91.29 0.00 89.55 0.19 91.13 0.21 92.68 0.00 91.66 0.11 96.30 0.00 90.38 0.34 /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2261783882
91.97 0.12 91.29 0.00 89.60 0.05 91.22 0.08 92.68 0.00 91.66 0.00 96.30 0.00 91.05 0.68 /workspace/coverage/default/42.otp_ctrl_stress_all.1599129257
92.08 0.10 91.37 0.08 89.71 0.11 91.44 0.23 92.68 0.00 91.82 0.16 96.38 0.08 91.14 0.08 /workspace/coverage/default/181.otp_ctrl_init_fail.903223961
92.17 0.10 91.44 0.08 89.82 0.11 91.58 0.13 92.68 0.00 91.93 0.11 96.38 0.00 91.39 0.25 /workspace/coverage/default/14.otp_ctrl_check_fail.86156529
92.26 0.09 91.54 0.09 90.01 0.19 91.61 0.03 92.68 0.00 92.14 0.21 96.38 0.00 91.48 0.08 /workspace/coverage/default/240.otp_ctrl_init_fail.1203761900
92.34 0.08 91.63 0.09 90.12 0.11 91.62 0.01 92.68 0.00 92.25 0.11 96.38 0.00 91.73 0.25 /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.615360454
92.42 0.07 91.97 0.34 90.12 0.00 91.62 0.00 92.68 0.00 92.25 0.00 96.38 0.00 91.90 0.17 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.367671197
92.48 0.06 92.05 0.08 90.15 0.03 91.76 0.15 92.68 0.00 92.35 0.11 96.38 0.00 91.98 0.08 /workspace/coverage/default/249.otp_ctrl_init_fail.3842569936
92.54 0.06 92.05 0.00 90.15 0.00 91.78 0.01 92.68 0.00 92.35 0.00 96.38 0.00 92.41 0.42 /workspace/coverage/default/41.otp_ctrl_regwen.1967652764
92.60 0.06 92.09 0.04 90.26 0.11 91.78 0.00 92.68 0.00 92.46 0.11 96.38 0.00 92.57 0.17 /workspace/coverage/default/35.otp_ctrl_check_fail.2061159639
92.66 0.06 92.13 0.04 90.34 0.08 91.80 0.02 92.68 0.00 92.57 0.11 96.38 0.00 92.74 0.17 /workspace/coverage/default/9.otp_ctrl_check_fail.339029822
92.72 0.06 92.18 0.06 90.45 0.11 91.80 0.00 92.68 0.00 92.62 0.05 96.38 0.00 92.91 0.17 /workspace/coverage/default/43.otp_ctrl_check_fail.106463328
92.77 0.05 92.24 0.06 90.50 0.05 91.96 0.16 92.68 0.00 92.73 0.11 96.38 0.00 92.91 0.00 /workspace/coverage/default/244.otp_ctrl_init_fail.1896132428
92.82 0.05 92.24 0.00 90.50 0.00 91.97 0.01 92.68 0.00 92.73 0.00 96.38 0.00 93.25 0.34 /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3790269421
92.86 0.04 92.24 0.00 90.50 0.00 92.03 0.06 92.68 0.00 92.73 0.00 96.38 0.00 93.50 0.25 /workspace/coverage/default/36.otp_ctrl_stress_all.1407925316
92.91 0.04 92.35 0.11 90.58 0.08 92.03 0.00 92.68 0.00 92.83 0.11 96.38 0.00 93.50 0.00 /workspace/coverage/default/33.otp_ctrl_check_fail.2580670396
92.95 0.04 92.35 0.00 90.85 0.27 92.03 0.00 92.68 0.00 92.83 0.00 96.38 0.00 93.50 0.00 /workspace/coverage/default/15.otp_ctrl_alert_test.1239451863
92.98 0.04 92.35 0.00 90.85 0.00 92.03 0.00 92.68 0.00 92.83 0.00 96.38 0.00 93.76 0.25 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2449040241
93.02 0.04 92.41 0.06 90.88 0.03 92.06 0.03 92.68 0.00 92.89 0.05 96.38 0.00 93.84 0.08 /workspace/coverage/default/158.otp_ctrl_init_fail.2156422278
93.05 0.03 92.47 0.06 90.91 0.03 92.06 0.01 92.68 0.00 92.94 0.05 96.38 0.00 93.92 0.08 /workspace/coverage/default/33.otp_ctrl_init_fail.475322791
93.08 0.03 92.52 0.06 90.93 0.03 92.07 0.01 92.68 0.00 92.99 0.05 96.38 0.00 94.01 0.08 /workspace/coverage/default/47.otp_ctrl_check_fail.174984473
93.12 0.03 92.58 0.06 90.96 0.03 92.07 0.00 92.68 0.00 93.05 0.05 96.38 0.00 94.09 0.08 /workspace/coverage/default/230.otp_ctrl_init_fail.1829567916
93.15 0.03 92.64 0.06 90.99 0.03 92.07 0.00 92.68 0.00 93.10 0.05 96.38 0.00 94.18 0.08 /workspace/coverage/default/31.otp_ctrl_init_fail.2096571055
93.18 0.03 92.69 0.06 91.04 0.05 92.07 0.01 92.68 0.00 93.21 0.11 96.38 0.00 94.18 0.00 /workspace/coverage/default/281.otp_ctrl_init_fail.2237411180
93.21 0.03 92.69 0.00 91.04 0.00 92.11 0.04 92.68 0.00 93.21 0.00 96.38 0.00 94.35 0.17 /workspace/coverage/default/18.otp_ctrl_regwen.1084262318
93.24 0.03 92.69 0.00 91.07 0.03 92.11 0.00 92.68 0.00 93.21 0.00 96.38 0.00 94.51 0.17 /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3905699184
93.26 0.03 92.69 0.00 91.07 0.00 92.13 0.02 92.68 0.00 93.21 0.00 96.38 0.00 94.68 0.17 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1695211166
93.29 0.02 92.69 0.00 91.07 0.00 92.13 0.00 92.68 0.00 93.21 0.00 96.38 0.00 94.85 0.17 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2270938912
93.31 0.02 92.69 0.00 91.07 0.00 92.13 0.00 92.68 0.00 93.21 0.00 96.38 0.00 95.02 0.17 /workspace/coverage/default/9.otp_ctrl_regwen.2480332226
93.33 0.02 92.69 0.00 91.07 0.00 92.28 0.15 92.68 0.00 93.21 0.00 96.38 0.00 95.02 0.00 /workspace/coverage/default/277.otp_ctrl_init_fail.139775541
93.35 0.02 92.73 0.04 91.10 0.03 92.29 0.01 92.68 0.00 93.26 0.05 96.38 0.00 95.02 0.00 /workspace/coverage/default/133.otp_ctrl_init_fail.2193029339
93.37 0.02 92.77 0.04 91.12 0.03 92.29 0.00 92.68 0.00 93.32 0.05 96.38 0.00 95.02 0.00 /workspace/coverage/default/118.otp_ctrl_init_fail.909464057
93.39 0.02 92.81 0.04 91.15 0.03 92.29 0.00 92.68 0.00 93.37 0.05 96.38 0.00 95.02 0.00 /workspace/coverage/default/135.otp_ctrl_init_fail.2666814070
93.40 0.01 92.81 0.00 91.15 0.00 92.30 0.01 92.68 0.00 93.37 0.00 96.38 0.00 95.11 0.08 /workspace/coverage/default/34.otp_ctrl_stress_all.3424921033
93.41 0.01 92.81 0.00 91.15 0.00 92.31 0.01 92.68 0.00 93.37 0.00 96.46 0.08 95.11 0.00 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3677117259
93.42 0.01 92.81 0.00 91.15 0.00 92.40 0.08 92.68 0.00 93.37 0.00 96.46 0.00 95.11 0.00 /workspace/coverage/default/236.otp_ctrl_init_fail.889706607
93.44 0.01 92.81 0.00 91.15 0.00 92.40 0.00 92.68 0.00 93.37 0.00 96.46 0.00 95.19 0.08 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3718280360
93.45 0.01 92.81 0.00 91.15 0.00 92.40 0.00 92.68 0.00 93.37 0.00 96.46 0.00 95.27 0.08 /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2738186590
93.46 0.01 92.81 0.00 91.23 0.08 92.40 0.00 92.68 0.00 93.37 0.00 96.46 0.00 95.27 0.00 /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.2943566764
93.47 0.01 92.81 0.00 91.23 0.00 92.40 0.00 92.68 0.00 93.37 0.00 96.53 0.08 95.27 0.00 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2998290360
93.48 0.01 92.83 0.02 91.29 0.05 92.40 0.00 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3469216039
93.49 0.01 92.83 0.00 91.31 0.03 92.42 0.03 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/112.otp_ctrl_init_fail.2863696878
93.49 0.01 92.83 0.00 91.31 0.00 92.47 0.04 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/252.otp_ctrl_init_fail.3897819607
93.50 0.01 92.83 0.00 91.34 0.03 92.48 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/47.otp_ctrl_stress_all.1997082551
93.51 0.01 92.86 0.04 91.34 0.00 92.48 0.00 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/3.otp_ctrl_sec_cm.372463871
93.51 0.01 92.86 0.00 91.37 0.03 92.49 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/24.otp_ctrl_stress_all.4028370006
93.51 0.01 92.86 0.00 91.37 0.00 92.52 0.03 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2613315204
93.52 0.01 92.86 0.00 91.40 0.03 92.52 0.00 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/0.otp_ctrl_stress_all.3380859319
93.52 0.01 92.88 0.02 91.40 0.00 92.52 0.00 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/24.otp_ctrl_test_access.2560625833
93.52 0.01 92.88 0.00 91.40 0.00 92.53 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/1.otp_ctrl_background_chks.2597199316
93.52 0.01 92.88 0.00 91.40 0.00 92.54 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/186.otp_ctrl_init_fail.3086892696
93.53 0.01 92.88 0.00 91.40 0.00 92.56 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/255.otp_ctrl_init_fail.2452496073
93.53 0.01 92.88 0.00 91.40 0.00 92.57 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/256.otp_ctrl_init_fail.3222666439
93.53 0.01 92.88 0.00 91.40 0.00 92.58 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/178.otp_ctrl_init_fail.3025054703
93.53 0.01 92.88 0.00 91.40 0.00 92.58 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.790191934
93.53 0.01 92.88 0.00 91.40 0.00 92.59 0.01 92.68 0.00 93.37 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.2142768468

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3646893037
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1726080819
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1502119038
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3774537762
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2678371214
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1527013196
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3303267205
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.686043644
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3810010248
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1136742639
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.883906819
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1015155145
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2491736528
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2147237433
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.347048106
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3069589441
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.517204739
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3189261713
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3432126918
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.4236317659
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3871755407
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1367142375
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2725387880
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.981117813
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1101259707
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2950011993
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3088462786
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4214824946
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1361328504
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3777210813
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.833091102
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1414295112
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3387995234
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2588643741
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1179528989
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.992186103
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.581092839
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3197589340
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3512775280
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1303792942
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.747206728
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3564728941
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1930017072
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1770234794
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1975372444
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1367869895
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.142085141
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1631518618
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3901433079
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1958403184
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1644964132
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3407523840
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.381891298
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3615140460
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.881909199
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2004027609
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.22148543
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1094193181
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2370748476
/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1486298650
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1829597183
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1211437433
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2658097641
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.516049885
/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2454907666
/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.790557504
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1129236332
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.305536935
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.684741890
/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3050234608
/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.848303155
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2872819050
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1502543833
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/workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.21214197
/workspace/coverage/default/99.otp_ctrl_init_fail.953061061
/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.1892540456
/workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2761518085



Total test records in report: 1330
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T18 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2621945673 Jan 14 01:14:14 PM PST 24 Jan 14 01:14:17 PM PST 24 75578091 ps
T114 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2725387880 Jan 14 01:14:18 PM PST 24 Jan 14 01:14:22 PM PST 24 52405658 ps
T115 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3130879709 Jan 14 01:14:26 PM PST 24 Jan 14 01:14:28 PM PST 24 54788296 ps
T116 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.909307981 Jan 14 01:14:09 PM PST 24 Jan 14 01:14:14 PM PST 24 223229943 ps
T117 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4214824946 Jan 14 01:14:17 PM PST 24 Jan 14 01:14:19 PM PST 24 109047612 ps
T119 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3088462786 Jan 14 01:14:14 PM PST 24 Jan 14 01:14:16 PM PST 24 142848418 ps
T183 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.31736110 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:16 PM PST 24 287322677 ps
T184 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2872819050 Jan 14 01:14:31 PM PST 24 Jan 14 01:14:36 PM PST 24 180222468 ps
T118 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.992186103 Jan 14 01:14:17 PM PST 24 Jan 14 01:14:20 PM PST 24 83984997 ps
T120 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3677117259 Jan 14 01:14:28 PM PST 24 Jan 14 01:14:31 PM PST 24 50418762 ps
T121 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1199933216 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:17 PM PST 24 402246922 ps
T122 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2613315204 Jan 14 01:14:02 PM PST 24 Jan 14 01:14:09 PM PST 24 127056619 ps
T123 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2944613123 Jan 14 01:14:09 PM PST 24 Jan 14 01:14:12 PM PST 24 65057324 ps
T185 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2150065925 Jan 14 01:14:06 PM PST 24 Jan 14 01:14:10 PM PST 24 87515989 ps
T186 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2003396252 Jan 14 01:14:06 PM PST 24 Jan 14 01:14:12 PM PST 24 127611384 ps
T187 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1101259707 Jan 14 01:14:17 PM PST 24 Jan 14 01:14:20 PM PST 24 268202062 ps
T242 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3901338065 Jan 14 01:14:27 PM PST 24 Jan 14 01:14:29 PM PST 24 45538324 ps
T208 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1685663464 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:52 PM PST 24 18314330077 ps
T243 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.130998653 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:15 PM PST 24 528216789 ps
T265 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3521444715 Jan 14 01:14:34 PM PST 24 Jan 14 01:14:36 PM PST 24 96548779 ps
T188 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.305536935 Jan 14 01:14:34 PM PST 24 Jan 14 01:14:37 PM PST 24 134412874 ps
T189 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3469216039 Jan 14 01:14:21 PM PST 24 Jan 14 01:14:24 PM PST 24 271897827 ps
T226 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1367142375 Jan 14 01:14:14 PM PST 24 Jan 14 01:14:17 PM PST 24 124929917 ps
T227 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2009332596 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:15 PM PST 24 146721281 ps
T228 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.517204739 Jan 14 01:14:08 PM PST 24 Jan 14 01:14:11 PM PST 24 127646483 ps
T229 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1414295112 Jan 14 01:14:18 PM PST 24 Jan 14 01:14:20 PM PST 24 74297080 ps
T190 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2066948519 Jan 14 01:14:18 PM PST 24 Jan 14 01:14:23 PM PST 24 194794245 ps
T191 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1015155145 Jan 14 01:14:07 PM PST 24 Jan 14 01:14:12 PM PST 24 1114185267 ps
T332 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1236114073 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:16 PM PST 24 125426005 ps
T261 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3327321113 Jan 14 01:14:08 PM PST 24 Jan 14 01:14:11 PM PST 24 105678888 ps
T285 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.3871755407 Jan 14 01:14:16 PM PST 24 Jan 14 01:14:18 PM PST 24 139921862 ps
T210 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.833091102 Jan 14 01:14:17 PM PST 24 Jan 14 01:14:21 PM PST 24 1137404797 ps
T230 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.618221252 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:15 PM PST 24 946851303 ps
T224 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1930017072 Jan 14 01:14:20 PM PST 24 Jan 14 01:14:28 PM PST 24 571473199 ps
T272 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.1695211166 Jan 14 01:14:26 PM PST 24 Jan 14 01:14:27 PM PST 24 37060515 ps
T273 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.217051129 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:15 PM PST 24 128071845 ps
T262 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2287898430 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:15 PM PST 24 93968390 ps
T274 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2147237433 Jan 14 01:14:04 PM PST 24 Jan 14 01:14:07 PM PST 24 45624365 ps
T275 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.661273560 Jan 14 01:14:32 PM PST 24 Jan 14 01:14:34 PM PST 24 35980343 ps
T276 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.2371045535 Jan 14 01:14:28 PM PST 24 Jan 14 01:14:30 PM PST 24 43342657 ps
T359 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.381891298 Jan 14 01:14:22 PM PST 24 Jan 14 01:14:24 PM PST 24 136966311 ps
T209 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1303792942 Jan 14 01:14:16 PM PST 24 Jan 14 01:14:26 PM PST 24 622793768 ps
T360 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2359553511 Jan 14 01:14:32 PM PST 24 Jan 14 01:14:34 PM PST 24 135669193 ps
T361 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.581092839 Jan 14 01:14:18 PM PST 24 Jan 14 01:14:21 PM PST 24 513295726 ps
T266 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.940492660 Jan 14 01:14:07 PM PST 24 Jan 14 01:14:12 PM PST 24 367710878 ps
T362 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.3408299812 Jan 14 01:14:26 PM PST 24 Jan 14 01:14:28 PM PST 24 46333301 ps
T231 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1367869895 Jan 14 01:14:21 PM PST 24 Jan 14 01:14:23 PM PST 24 128440010 ps
T263 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.22148543 Jan 14 01:14:32 PM PST 24 Jan 14 01:14:35 PM PST 24 130164752 ps
T302 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1829597183 Jan 14 01:14:33 PM PST 24 Jan 14 01:14:39 PM PST 24 1470784810 ps
T225 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1817203081 Jan 14 01:14:03 PM PST 24 Jan 14 01:14:12 PM PST 24 2530343118 ps
T211 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1746892579 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:28 PM PST 24 9588109243 ps
T363 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3387995234 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:17 PM PST 24 562128036 ps
T358 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2658097641 Jan 14 01:14:31 PM PST 24 Jan 14 01:14:35 PM PST 24 1095527614 ps
T232 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3323689129 Jan 14 01:14:06 PM PST 24 Jan 14 01:14:08 PM PST 24 44621743 ps
T364 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3151147729 Jan 14 01:14:19 PM PST 24 Jan 14 01:14:21 PM PST 24 106527624 ps
T264 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.747206728 Jan 14 01:14:22 PM PST 24 Jan 14 01:14:25 PM PST 24 157495101 ps
T365 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1084009401 Jan 14 01:14:09 PM PST 24 Jan 14 01:14:11 PM PST 24 39951799 ps
T366 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2370748476 Jan 14 01:14:25 PM PST 24 Jan 14 01:14:27 PM PST 24 551222719 ps
T124 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.883906819 Jan 14 01:14:03 PM PST 24 Jan 14 01:14:07 PM PST 24 64209049 ps
T267 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.790557504 Jan 14 01:14:33 PM PST 24 Jan 14 01:14:37 PM PST 24 328788522 ps
T233 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2950011993 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:17 PM PST 24 158076774 ps
T268 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.848303155 Jan 14 01:14:31 PM PST 24 Jan 14 01:14:35 PM PST 24 161528229 ps
T309 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3660839667 Jan 14 01:14:08 PM PST 24 Jan 14 01:14:18 PM PST 24 1224970351 ps
T367 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.877740465 Jan 14 01:14:05 PM PST 24 Jan 14 01:14:08 PM PST 24 66795389 ps
T234 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2491736528 Jan 14 01:14:01 PM PST 24 Jan 14 01:14:04 PM PST 24 140098642 ps
T368 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3291819670 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:18 PM PST 24 78622849 ps
T235 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2424377630 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:15 PM PST 24 75379231 ps
T369 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.881909199 Jan 14 01:14:28 PM PST 24 Jan 14 01:14:32 PM PST 24 209015466 ps
T370 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.2797019221 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:22 PM PST 24 429523235 ps
T371 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3512775280 Jan 14 01:14:17 PM PST 24 Jan 14 01:14:24 PM PST 24 314641358 ps
T372 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1361328504 Jan 14 01:14:16 PM PST 24 Jan 14 01:14:21 PM PST 24 1266953653 ps
T373 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3901433079 Jan 14 01:14:24 PM PST 24 Jan 14 01:14:27 PM PST 24 100210425 ps
T269 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1502119038 Jan 14 01:14:01 PM PST 24 Jan 14 01:14:04 PM PST 24 1000911801 ps
T374 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1690625921 Jan 14 01:14:32 PM PST 24 Jan 14 01:14:34 PM PST 24 39284837 ps
T270 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.516239092 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:15 PM PST 24 125733531 ps
T375 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.58255351 Jan 14 01:14:06 PM PST 24 Jan 14 01:14:08 PM PST 24 38089728 ps
T376 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1807721578 Jan 14 01:14:05 PM PST 24 Jan 14 01:14:08 PM PST 24 134379221 ps
T377 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1527013196 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:15 PM PST 24 39515352 ps
T378 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1486298650 Jan 14 01:14:28 PM PST 24 Jan 14 01:14:31 PM PST 24 147381936 ps
T379 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3814109385 Jan 14 01:14:35 PM PST 24 Jan 14 01:14:37 PM PST 24 53582664 ps
T380 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2172929071 Jan 14 01:14:32 PM PST 24 Jan 14 01:14:34 PM PST 24 131595282 ps
T236 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2588643741 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:19 PM PST 24 215948131 ps
T381 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.2305882437 Jan 14 01:14:14 PM PST 24 Jan 14 01:14:16 PM PST 24 137431857 ps
T382 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.755625420 Jan 14 01:14:34 PM PST 24 Jan 14 01:14:36 PM PST 24 82910273 ps
T383 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3235846260 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:14 PM PST 24 34775967 ps
T384 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1541966788 Jan 14 01:14:18 PM PST 24 Jan 14 01:14:20 PM PST 24 42462598 ps
T385 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.443095869 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:19 PM PST 24 1065900950 ps
T310 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3991064011 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:23 PM PST 24 621720744 ps
T386 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.916144073 Jan 14 01:14:28 PM PST 24 Jan 14 01:14:30 PM PST 24 550699724 ps
T387 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2755171183 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:17 PM PST 24 213605832 ps
T223 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1656610277 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:18 PM PST 24 980107067 ps
T388 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1921266403 Jan 14 01:14:34 PM PST 24 Jan 14 01:14:36 PM PST 24 125177944 ps
T389 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1425287163 Jan 14 01:14:12 PM PST 24 Jan 14 01:14:14 PM PST 24 80813601 ps
T390 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3432126918 Jan 14 01:14:17 PM PST 24 Jan 14 01:14:20 PM PST 24 198764263 ps
T125 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.220859829 Jan 14 01:14:07 PM PST 24 Jan 14 01:14:12 PM PST 24 972174533 ps
T391 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3069589441 Jan 14 01:14:02 PM PST 24 Jan 14 01:14:04 PM PST 24 131960955 ps
T392 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1644964132 Jan 14 01:14:33 PM PST 24 Jan 14 01:14:38 PM PST 24 1078116816 ps
T314 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1958403184 Jan 14 01:14:30 PM PST 24 Jan 14 01:14:41 PM PST 24 1727079991 ps
T393 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.142085141 Jan 14 01:14:24 PM PST 24 Jan 14 01:14:26 PM PST 24 147893952 ps
T394 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3407523840 Jan 14 01:14:27 PM PST 24 Jan 14 01:14:30 PM PST 24 71852177 ps
T395 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3608610131 Jan 14 01:14:35 PM PST 24 Jan 14 01:14:37 PM PST 24 38182066 ps
T311 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2449040241 Jan 14 01:14:01 PM PST 24 Jan 14 01:14:20 PM PST 24 9709448313 ps
T312 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3777210813 Jan 14 01:14:16 PM PST 24 Jan 14 01:14:39 PM PST 24 1576389873 ps
T316 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1501512293 Jan 14 01:14:10 PM PST 24 Jan 14 01:14:26 PM PST 24 2378637019 ps
T396 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2454907666 Jan 14 01:14:32 PM PST 24 Jan 14 01:14:34 PM PST 24 37418588 ps
T126 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2678832922 Jan 14 01:14:10 PM PST 24 Jan 14 01:14:12 PM PST 24 231193392 ps
T397 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.3930103383 Jan 14 01:14:38 PM PST 24 Jan 14 01:14:40 PM PST 24 45290556 ps
T398 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.4091517170 Jan 14 01:14:33 PM PST 24 Jan 14 01:14:34 PM PST 24 134779087 ps
T237 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3525299760 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:15 PM PST 24 75674114 ps
T399 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3050234608 Jan 14 01:14:25 PM PST 24 Jan 14 01:14:27 PM PST 24 41318400 ps
T315 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.3787205924 Jan 14 01:14:05 PM PST 24 Jan 14 01:14:49 PM PST 24 19245301762 ps
T400 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2311444928 Jan 14 01:14:14 PM PST 24 Jan 14 01:14:19 PM PST 24 177482661 ps
T401 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.4049643259 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:19 PM PST 24 234540123 ps
T402 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.4236317659 Jan 14 01:14:14 PM PST 24 Jan 14 01:14:16 PM PST 24 68579558 ps
T238 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3977345685 Jan 14 01:14:06 PM PST 24 Jan 14 01:14:09 PM PST 24 50039291 ps
T403 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3646893037 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:18 PM PST 24 260637258 ps
T404 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2389757452 Jan 14 01:14:31 PM PST 24 Jan 14 01:14:33 PM PST 24 41666209 ps
T239 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1136742639 Jan 14 01:14:02 PM PST 24 Jan 14 01:14:06 PM PST 24 148072653 ps
T405 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3564728941 Jan 14 01:14:21 PM PST 24 Jan 14 01:14:24 PM PST 24 81849897 ps
T406 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3567922056 Jan 14 01:14:18 PM PST 24 Jan 14 01:14:21 PM PST 24 133763046 ps
T240 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3025612947 Jan 14 01:14:15 PM PST 24 Jan 14 01:14:19 PM PST 24 82975119 ps
T244 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.898282260 Jan 14 01:14:34 PM PST 24 Jan 14 01:14:37 PM PST 24 537292369 ps
T245 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3440313257 Jan 14 01:14:13 PM PST 24 Jan 14 01:14:39 PM PST 24 18937517956 ps
T246 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1770234794 Jan 14 01:14:20 PM PST 24 Jan 14 01:14:50 PM PST 24 19175279905 ps
T247 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1557413791 Jan 14 01:14:07 PM PST 24 Jan 14 01:14:11 PM PST 24 75683524 ps
T248 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3615140460 Jan 14 01:14:22 PM PST 24 Jan 14 01:14:25 PM PST 24 78258321 ps
T249 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2678371214 Jan 14 01:14:02 PM PST 24 Jan 14 01:14:04 PM PST 24 533821121 ps
T250 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1920148394 Jan 14 01:14:05 PM PST 24 Jan 14 01:14:28 PM PST 24 4420403966 ps
T251 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1502543833 Jan 14 01:14:38 PM PST 24 Jan 14 01:14:47 PM PST 24 1408837416 ps
T252 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1079539141 Jan 14 01:14:11 PM PST 24 Jan 14 01:14:13 PM PST 24 37459957 ps
T1 /workspace/coverage/default/18.otp_ctrl_test_access.169030430 Jan 14 02:55:02 PM PST 24 Jan 14 02:55:23 PM PST 24 1266888313 ps
T2 /workspace/coverage/default/35.otp_ctrl_macro_errs.210554529 Jan 14 02:56:06 PM PST 24 Jan 14 02:56:36 PM PST 24 14240733615 ps
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