Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
keymgr_rd_en 2 0 2 100.00 100 1 1 2
secret2_lock 2 0 2 100.00 100 1 1 2


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::keymgr_o_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
keymgr_output_conditions 4 0 4 100.00 100 1 1 0


Summary for Variable keymgr_rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for keymgr_rd_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3887 1 T18 1 T115 1 T119 1
auto[1] 2453 1 T114 1 T273 1 T275 1



Summary for Variable secret2_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret2_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4377 1 T18 1 T114 1 T115 1
auto[1] 1963 1 T1 9 T2 1 T3 1



Summary for Cross keymgr_output_conditions

Samples crossed: keymgr_rd_en secret2_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for keymgr_output_conditions

Bins
keymgr_rd_ensecret2_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 2691 1 T18 1 T115 1 T119 1
auto[0] auto[1] 1196 1 T1 6 T2 1 T3 1
auto[1] auto[0] 1686 1 T114 1 T273 1 T275 1
auto[1] auto[1] 767 1 T1 3 T15 1 T35 4

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