Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	45610	1			T1	236		T11	213		T29	91
access_err	70929	1			T1	170		T4	167		T7	20
write_blank_err	422	1			T7	2		T94	1		T11	8
ecc_uncorr_err	78143	1			T7	451		T94	722		T11	345
ecc_corr_err	1384	1			T29	24		T117	6		T114	4
no_err	359364	1			T1	1315		T4	1031		T5	152

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	38513	1			T1	120		T4	102		T6	2
secret2	77170	1			T1	168		T4	180		T5	18
secret1	83530	1			T1	148		T4	176		T5	12
secret0	98670	1			T1	138		T4	138		T5	12
hw_cfg	63733	1			T1	110		T4	102		T5	24
owner_sw_cfg	57855	1			T1	207		T4	146		T5	38
creator_sw_cfg	59801	1			T1	686		T4	218		T5	28
vendor_test	76580	1			T1	144		T4	136		T5	20

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	2724	1			T12	94		T320	363		T321	65
fsm_err	secret2	5507	1			T209	315		T225	505		T322	33
fsm_err	secret1	4195	1			T97	225		T14	29		T169	168
fsm_err	secret0	2701	1			T11	18		T28	3		T323	188
fsm_err	hw_cfg	4931	1			T11	195		T206	204		T127	32
fsm_err	owner_sw_cfg	3351	1			T233	381		T118	25		T324	102
fsm_err	creator_sw_cfg	4368	1			T1	236		T316	395		T210	474
fsm_err	vendor_test	17833	1			T29	91		T125	323		T99	73
access_err	lc_or_oob	16530	1			T1	60		T4	51		T6	1
access_err	secret2	12074	1			T1	35		T4	48		T7	13
access_err	secret1	6042	1			T1	2		T53	31		T96	3
access_err	secret0	4887	1			T1	3		T4	2		T6	2
access_err	hw_cfg	2862	1			T11	2		T29	10		T101	1
access_err	owner_sw_cfg	10777	1			T1	25		T4	24		T6	2
access_err	creator_sw_cfg	10801	1			T1	23		T4	26		T7	6
access_err	vendor_test	6956	1			T1	22		T4	16		T7	1
write_blank_err	secret2	30	1			T94	1		T11	1		T317	1
write_blank_err	secret1	43	1			T7	1		T101	1		T15	1
write_blank_err	secret0	79	1			T86	2		T120	1		T221	1
write_blank_err	hw_cfg	24	1			T28	1		T325	1		T308	1
write_blank_err	owner_sw_cfg	87	1			T11	3		T28	1		T317	4
write_blank_err	creator_sw_cfg	129	1			T7	1		T101	10		T221	2
write_blank_err	vendor_test	30	1			T11	4		T316	1		T324	1
ecc_uncorr_err	secret2	13736	1			T94	722		T11	345		T117	40
ecc_uncorr_err	secret1	19502	1			T7	451		T101	311		T117	59
ecc_uncorr_err	secret0	30889	1			T86	629		T115	34		T120	434
ecc_uncorr_err	hw_cfg	9098	1			T114	13		T115	32		T28	270
ecc_uncorr_err	owner_sw_cfg	2299	1			T117	119		T115	89		T127	42
ecc_uncorr_err	creator_sw_cfg	2619	1			T115	40		T127	44		T116	62
ecc_corr_err	secret2	110	1			T115	1		T127	2		T65	2
ecc_corr_err	secret1	140	1			T29	2		T117	2		T42	4
ecc_corr_err	secret0	212	1			T29	5		T117	1		T114	1
ecc_corr_err	hw_cfg	342	1			T29	6		T117	3		T42	3
ecc_corr_err	owner_sw_cfg	144	1			T29	1		T42	1		T26	1
ecc_corr_err	creator_sw_cfg	163	1			T29	4		T114	1		T90	1
ecc_corr_err	vendor_test	273	1			T29	6		T114	2		T42	3
no_err	lc_or_oob	19259	1			T1	60		T4	51		T6	1
no_err	secret2	45713	1			T1	133		T4	132		T5	18
no_err	secret1	53608	1			T1	146		T4	176		T5	12
no_err	secret0	59902	1			T1	135		T4	136		T5	12
no_err	hw_cfg	46476	1			T1	110		T4	102		T5	24
no_err	owner_sw_cfg	41197	1			T1	182		T4	122		T5	38
no_err	creator_sw_cfg	41721	1			T1	427		T4	192		T5	28
no_err	vendor_test	51488	1			T1	122		T4	120		T5	20

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded