Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.25 92.63 91.00 92.41 91.55 93.33 96.53 95.27


Total tests in report: 1333
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
41.10 41.10 66.59 66.59 54.15 54.15 45.18 45.18 0.00 0.00 62.35 62.35 44.57 44.57 14.85 14.85 /workspace/coverage/default/7.otp_ctrl_background_chks.1163342500
76.17 35.07 88.32 21.73 77.12 22.96 58.35 13.17 91.55 91.55 84.22 21.87 89.74 45.17 43.88 29.03 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1913029737
78.97 2.80 89.55 1.23 80.78 3.66 61.20 2.85 91.55 0.00 87.11 2.89 89.82 0.08 52.74 8.86 /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1860163884
81.24 2.28 89.55 0.00 81.11 0.33 69.40 8.20 91.55 0.00 87.27 0.16 89.89 0.08 59.92 7.17 /workspace/coverage/default/36.otp_ctrl_stress_all.559040579
83.26 2.02 89.89 0.34 83.39 2.28 69.50 0.10 91.55 0.00 87.43 0.16 90.50 0.60 70.55 10.63 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.902787461
84.78 1.52 90.27 0.38 84.55 1.17 75.53 6.02 91.55 0.00 88.29 0.86 91.03 0.53 72.24 1.69 /workspace/coverage/default/4.otp_ctrl_background_chks.773270889
85.76 0.98 90.27 0.00 84.64 0.08 79.85 4.32 91.55 0.00 88.34 0.05 91.25 0.23 74.43 2.19 /workspace/coverage/default/19.otp_ctrl_test_access.1573358049
86.49 0.73 90.42 0.15 85.21 0.57 80.25 0.41 91.55 0.00 89.73 1.39 93.51 2.26 74.77 0.34 /workspace/coverage/default/0.otp_ctrl_sec_cm.971866994
87.20 0.70 90.42 0.00 85.21 0.00 84.77 4.51 91.55 0.00 89.73 0.00 93.51 0.00 75.19 0.42 /workspace/coverage/default/28.otp_ctrl_regwen.2468288848
87.86 0.67 90.46 0.04 86.16 0.95 84.91 0.15 91.55 0.00 90.16 0.43 93.67 0.15 78.14 2.95 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.728074028
88.47 0.61 90.46 0.00 86.32 0.16 86.71 1.80 91.55 0.00 90.16 0.00 93.67 0.00 80.42 2.28 /workspace/coverage/default/12.otp_ctrl_stress_all.2541396070
88.98 0.51 90.61 0.15 87.05 0.73 87.46 0.75 91.55 0.00 90.43 0.27 93.67 0.00 82.11 1.69 /workspace/coverage/default/28.otp_ctrl_check_fail.2183740888
89.42 0.44 91.05 0.44 87.49 0.43 87.46 0.00 91.55 0.00 90.80 0.37 94.57 0.90 83.04 0.93 /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.644125621
89.75 0.33 91.05 0.00 87.98 0.49 87.46 0.00 91.55 0.00 90.86 0.05 95.55 0.98 83.80 0.76 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2863463847
90.00 0.25 91.05 0.00 87.98 0.00 88.03 0.57 91.55 0.00 90.86 0.00 95.55 0.00 84.98 1.18 /workspace/coverage/default/46.otp_ctrl_stress_all.876837572
90.24 0.24 91.05 0.00 88.03 0.05 88.04 0.01 91.55 0.00 90.86 0.00 95.85 0.30 86.33 1.35 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.381853401
90.47 0.22 91.10 0.06 88.14 0.11 88.15 0.11 91.55 0.00 90.96 0.11 95.85 0.00 87.51 1.18 /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.1829593703
90.68 0.21 91.14 0.04 88.33 0.19 88.95 0.80 91.55 0.00 91.07 0.11 95.85 0.00 87.85 0.34 /workspace/coverage/default/18.otp_ctrl_check_fail.1467711217
90.85 0.18 91.14 0.00 88.68 0.35 88.95 0.00 91.55 0.00 91.28 0.21 95.85 0.00 88.52 0.68 /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.2975043425
91.03 0.17 91.31 0.17 88.84 0.16 89.04 0.08 91.55 0.00 91.60 0.32 96.08 0.23 88.78 0.25 /workspace/coverage/default/134.otp_ctrl_init_fail.3576395827
91.19 0.17 91.31 0.00 88.84 0.00 89.86 0.82 91.55 0.00 91.60 0.00 96.08 0.00 89.11 0.34 /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.4101157029
91.35 0.15 91.33 0.02 88.87 0.03 89.94 0.08 91.55 0.00 91.60 0.00 96.08 0.00 90.04 0.93 /workspace/coverage/default/11.otp_ctrl_stress_all.2465286234
91.50 0.15 91.46 0.13 89.22 0.35 90.10 0.16 91.55 0.00 91.93 0.32 96.08 0.00 90.13 0.08 /workspace/coverage/default/216.otp_ctrl_init_fail.3225922931
91.61 0.12 91.52 0.06 89.33 0.11 90.21 0.11 91.55 0.00 91.98 0.05 96.15 0.08 90.55 0.42 /workspace/coverage/default/19.otp_ctrl_macro_errs.2850732618
91.70 0.09 91.58 0.06 89.36 0.03 90.62 0.41 91.55 0.00 92.03 0.05 96.15 0.00 90.63 0.08 /workspace/coverage/default/81.otp_ctrl_init_fail.574126025
91.79 0.09 91.63 0.06 89.47 0.11 90.69 0.07 91.55 0.00 92.09 0.05 96.23 0.08 90.89 0.25 /workspace/coverage/default/15.otp_ctrl_check_fail.466646892
91.88 0.09 91.63 0.00 89.47 0.00 90.70 0.01 91.55 0.00 92.09 0.00 96.23 0.00 91.48 0.59 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.767426769
91.96 0.09 91.77 0.13 89.60 0.14 90.70 0.00 91.55 0.00 92.25 0.16 96.23 0.00 91.65 0.17 /workspace/coverage/default/48.otp_ctrl_check_fail.1403257008
92.04 0.08 91.86 0.09 89.69 0.08 90.82 0.12 91.55 0.00 92.41 0.16 96.23 0.00 91.73 0.08 /workspace/coverage/default/214.otp_ctrl_init_fail.690517368
92.11 0.07 91.90 0.04 89.79 0.11 90.82 0.00 91.55 0.00 92.51 0.11 96.23 0.00 91.98 0.25 /workspace/coverage/default/44.otp_ctrl_check_fail.3611951808
92.18 0.07 91.90 0.00 89.79 0.00 90.82 0.00 91.55 0.00 92.51 0.00 96.30 0.08 92.41 0.42 /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3857217939
92.25 0.07 91.90 0.00 89.79 0.00 90.88 0.06 91.55 0.00 92.51 0.00 96.30 0.00 92.83 0.42 /workspace/coverage/default/24.otp_ctrl_stress_all.3877584627
92.31 0.05 91.96 0.06 89.85 0.05 91.04 0.15 91.55 0.00 92.62 0.11 96.30 0.00 92.83 0.00 /workspace/coverage/default/234.otp_ctrl_init_fail.2125943872
92.35 0.05 92.30 0.34 89.85 0.00 91.04 0.00 91.55 0.00 92.62 0.00 96.30 0.00 92.83 0.00 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1549041213
92.40 0.05 92.30 0.00 89.85 0.00 91.04 0.00 91.55 0.00 92.62 0.00 96.30 0.00 93.16 0.34 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.607824933
92.45 0.05 92.35 0.06 89.88 0.03 91.15 0.11 91.55 0.00 92.67 0.05 96.30 0.00 93.25 0.08 /workspace/coverage/default/279.otp_ctrl_init_fail.4133551739
92.50 0.05 92.41 0.06 89.93 0.05 91.15 0.00 91.55 0.00 92.73 0.05 96.38 0.08 93.33 0.08 /workspace/coverage/default/42.otp_ctrl_macro_errs.3038062649
92.54 0.04 92.47 0.06 89.96 0.03 91.29 0.14 91.55 0.00 92.78 0.05 96.38 0.00 93.33 0.00 /workspace/coverage/default/42.otp_ctrl_init_fail.1957026431
92.58 0.04 92.47 0.00 90.23 0.27 91.29 0.00 91.55 0.00 92.78 0.00 96.38 0.00 93.33 0.00 /workspace/coverage/default/15.otp_ctrl_alert_test.1458796156
92.61 0.04 92.47 0.00 90.23 0.00 91.31 0.02 91.55 0.00 92.78 0.00 96.38 0.00 93.59 0.25 /workspace/coverage/default/41.otp_ctrl_stress_all.3776614408
92.65 0.04 92.50 0.04 90.26 0.03 91.38 0.07 91.55 0.00 92.83 0.05 96.38 0.00 93.67 0.08 /workspace/coverage/default/168.otp_ctrl_init_fail.3445569591
92.69 0.04 92.50 0.00 90.26 0.00 91.38 0.00 91.55 0.00 92.83 0.00 96.38 0.00 93.92 0.25 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1424397203
92.73 0.04 92.50 0.00 90.26 0.00 91.38 0.00 91.55 0.00 92.83 0.00 96.38 0.00 94.18 0.25 /workspace/coverage/default/33.otp_ctrl_regwen.238507938
92.76 0.04 92.50 0.00 90.26 0.00 91.38 0.00 91.55 0.00 92.83 0.00 96.38 0.00 94.43 0.25 /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2471109244
92.79 0.03 92.56 0.06 90.28 0.03 91.38 0.00 91.55 0.00 92.89 0.05 96.38 0.00 94.51 0.08 /workspace/coverage/default/111.otp_ctrl_init_fail.2006786920
92.82 0.03 92.62 0.06 90.31 0.03 91.38 0.00 91.55 0.00 92.94 0.05 96.38 0.00 94.60 0.08 /workspace/coverage/default/160.otp_ctrl_init_fail.4061821598
92.86 0.03 92.62 0.00 90.31 0.00 91.43 0.05 91.55 0.00 92.94 0.00 96.38 0.00 94.77 0.17 /workspace/coverage/default/19.otp_ctrl_stress_all.44520481
92.89 0.03 92.67 0.06 90.36 0.05 91.47 0.05 91.55 0.00 92.99 0.05 96.38 0.00 94.77 0.00 /workspace/coverage/default/12.otp_ctrl_check_fail.2485171738
92.91 0.03 92.69 0.02 90.39 0.03 91.47 0.00 91.55 0.00 93.05 0.05 96.38 0.00 94.85 0.08 /workspace/coverage/default/11.otp_ctrl_check_fail.760293595
92.93 0.02 92.73 0.04 90.42 0.03 91.51 0.04 91.55 0.00 93.10 0.05 96.38 0.00 94.85 0.00 /workspace/coverage/default/272.otp_ctrl_init_fail.1651972980
92.96 0.02 92.73 0.00 90.42 0.00 91.51 0.00 91.55 0.00 93.10 0.00 96.53 0.15 94.85 0.00 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1746672467
92.98 0.02 92.77 0.04 90.47 0.05 91.51 0.00 91.55 0.00 93.16 0.05 96.53 0.00 94.85 0.00 /workspace/coverage/default/166.otp_ctrl_init_fail.682428470
93.00 0.02 92.83 0.06 90.55 0.08 91.51 0.00 91.55 0.00 93.16 0.00 96.53 0.00 94.85 0.00 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3959810462
93.01 0.02 92.86 0.04 90.58 0.03 91.51 0.01 91.55 0.00 93.21 0.05 96.53 0.00 94.85 0.00 /workspace/coverage/default/117.otp_ctrl_init_fail.1310645894
93.03 0.02 92.86 0.00 90.58 0.00 91.63 0.12 91.55 0.00 93.21 0.00 96.53 0.00 94.85 0.00 /workspace/coverage/default/195.otp_ctrl_init_fail.296641353
93.05 0.02 92.86 0.00 90.58 0.00 91.75 0.12 91.55 0.00 93.21 0.00 96.53 0.00 94.85 0.00 /workspace/coverage/default/35.otp_ctrl_init_fail.1265828247
93.06 0.02 92.90 0.04 90.61 0.03 91.75 0.00 91.55 0.00 93.26 0.05 96.53 0.00 94.85 0.00 /workspace/coverage/default/100.otp_ctrl_init_fail.3369000727
93.08 0.02 92.90 0.00 90.66 0.05 91.81 0.06 91.55 0.00 93.26 0.00 96.53 0.00 94.85 0.00 /workspace/coverage/default/34.otp_ctrl_macro_errs.809876539
93.10 0.02 92.90 0.00 90.66 0.00 91.92 0.11 91.55 0.00 93.26 0.00 96.53 0.00 94.85 0.00 /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.3127420152
93.11 0.01 92.90 0.00 90.66 0.00 91.92 0.00 91.55 0.00 93.26 0.00 96.53 0.00 94.94 0.08 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.246899638
93.12 0.01 92.90 0.00 90.66 0.00 91.92 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.02 0.08 /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.1156789248
93.13 0.01 92.90 0.00 90.66 0.00 91.92 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.11 0.08 /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.2257824187
93.14 0.01 92.90 0.00 90.66 0.00 91.92 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.19 0.08 /workspace/coverage/default/15.otp_ctrl_regwen.2398721398
93.16 0.01 92.90 0.00 90.66 0.00 91.92 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.08 /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.1171710088
93.17 0.01 92.90 0.00 90.66 0.00 91.99 0.07 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/30.otp_ctrl_parallel_key_req.887397933
93.18 0.01 92.90 0.00 90.66 0.00 92.06 0.07 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/205.otp_ctrl_init_fail.3552150786
93.19 0.01 92.90 0.00 90.72 0.05 92.07 0.01 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/36.otp_ctrl_check_fail.2417122082
93.19 0.01 92.90 0.00 90.77 0.05 92.07 0.01 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/4.otp_ctrl_stress_all.2004775943
93.20 0.01 92.90 0.00 90.77 0.00 92.13 0.06 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/174.otp_ctrl_init_fail.2076825287
93.21 0.01 92.90 0.00 90.77 0.00 92.17 0.04 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/40.otp_ctrl_stress_all.978281775
93.21 0.01 92.90 0.00 90.77 0.00 92.21 0.04 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/5.otp_ctrl_init_fail.2805757441
93.22 0.01 92.90 0.00 90.77 0.00 92.25 0.04 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/26.otp_ctrl_check_fail.2885217152
93.22 0.01 92.90 0.00 90.77 0.00 92.28 0.03 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/141.otp_ctrl_init_fail.3379833466
93.23 0.01 92.90 0.00 90.80 0.03 92.28 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.370207953
93.23 0.01 92.90 0.00 90.83 0.03 92.28 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2315099353
93.24 0.01 92.90 0.00 90.85 0.03 92.28 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.4206515039
93.24 0.01 92.90 0.00 90.88 0.03 92.28 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.2324812841
93.24 0.01 92.90 0.00 90.88 0.00 92.30 0.02 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/22.otp_ctrl_smoke.3774086436
93.25 0.01 92.90 0.00 90.88 0.00 92.32 0.02 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/238.otp_ctrl_init_fail.3219908382
93.25 0.01 92.90 0.00 90.88 0.00 92.34 0.02 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/32.otp_ctrl_init_fail.2755465518
93.25 0.01 92.92 0.02 90.88 0.00 92.34 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/0.otp_ctrl_test_access.4167012401
93.25 0.01 92.94 0.02 90.88 0.00 92.34 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3218839050
93.26 0.01 92.96 0.02 90.88 0.00 92.34 0.00 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1012340604
93.26 0.01 92.96 0.00 90.88 0.00 92.36 0.02 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1079297459
93.26 0.01 92.96 0.00 90.88 0.00 92.37 0.01 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/12.otp_ctrl_regwen.1878892389
93.26 0.01 92.96 0.00 90.88 0.00 92.39 0.01 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/164.otp_ctrl_init_fail.3902760812
93.26 0.01 92.96 0.00 90.88 0.00 92.40 0.01 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/72.otp_ctrl_init_fail.1837945466
93.27 0.01 92.96 0.00 90.88 0.00 92.41 0.01 91.55 0.00 93.26 0.00 96.53 0.00 95.27 0.00 /workspace/coverage/default/1.otp_ctrl_background_chks.3766696715

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1055174032
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1569123919
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.4286025244
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3402162942
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3942978146
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.4164147903
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3065500287
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.131328204
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1264960802
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3750042492
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2396184513
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1770880753
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3124061056
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1528246752
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1418112441
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3751772718
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4215720851
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.695964111
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2324041088
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3081705136
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2556504116
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1521593231
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1096577512
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3878631125
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2115128773
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2548839039
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3623595165
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2115366126
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2042577421
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.715207154
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3337887445
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3585462123
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2729080084
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3546608463
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1103900186
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2776867369
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3934518168
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1746202657
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.457215298
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2557257480
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.4016548559
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/workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.2939477143
/workspace/coverage/default/9.otp_ctrl_test_access.2026584101
/workspace/coverage/default/90.otp_ctrl_init_fail.2949946457
/workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.1011289627
/workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.1511590101
/workspace/coverage/default/91.otp_ctrl_init_fail.4000133260
/workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.2178078375
/workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2497092790
/workspace/coverage/default/92.otp_ctrl_init_fail.222416182
/workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.2090193417
/workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.310553502
/workspace/coverage/default/93.otp_ctrl_init_fail.2501420967
/workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2906206473
/workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.370637489
/workspace/coverage/default/94.otp_ctrl_init_fail.3956843028
/workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.3917247688
/workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.4199496248
/workspace/coverage/default/95.otp_ctrl_init_fail.803128744
/workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.4173478380
/workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.20763087
/workspace/coverage/default/96.otp_ctrl_init_fail.2280492146
/workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.4220439319
/workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2890784903
/workspace/coverage/default/97.otp_ctrl_init_fail.1584281837
/workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.373932797
/workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3663191362
/workspace/coverage/default/98.otp_ctrl_init_fail.254099904
/workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2702313581
/workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.889839664
/workspace/coverage/default/99.otp_ctrl_init_fail.2450663787
/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.2688413356
/workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3656501222



Total test records in report: 1333
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T13 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1913029737 Jan 17 12:56:41 PM PST 24 Jan 17 12:56:52 PM PST 24 896157599 ps
T107 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2396184513 Jan 17 12:56:10 PM PST 24 Jan 17 12:56:21 PM PST 24 1290801673 ps
T108 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.103933359 Jan 17 12:56:46 PM PST 24 Jan 17 12:56:49 PM PST 24 276462018 ps
T183 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3337887445 Jan 17 12:56:44 PM PST 24 Jan 17 12:56:48 PM PST 24 80622692 ps
T184 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3896919370 Jan 17 12:56:57 PM PST 24 Jan 17 12:57:01 PM PST 24 118976609 ps
T185 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.3028694898 Jan 17 12:56:44 PM PST 24 Jan 17 12:56:49 PM PST 24 98271762 ps
T186 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1055174032 Jan 17 12:56:07 PM PST 24 Jan 17 12:56:10 PM PST 24 51341638 ps
T187 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1746672467 Jan 17 12:56:39 PM PST 24 Jan 17 12:56:43 PM PST 24 74644659 ps
T188 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1395706316 Jan 17 12:56:24 PM PST 24 Jan 17 12:56:33 PM PST 24 431266356 ps
T189 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2548839039 Jan 17 12:56:33 PM PST 24 Jan 17 12:56:41 PM PST 24 160436527 ps
T191 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2863463847 Jan 17 12:56:09 PM PST 24 Jan 17 12:56:13 PM PST 24 46569638 ps
T200 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.660504623 Jan 17 12:56:57 PM PST 24 Jan 17 12:57:14 PM PST 24 2267249132 ps
T201 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2315099353 Jan 17 12:56:36 PM PST 24 Jan 17 12:56:50 PM PST 24 1219809574 ps
T190 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3959810462 Jan 17 12:56:31 PM PST 24 Jan 17 12:56:35 PM PST 24 145231212 ps
T202 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1459854795 Jan 17 12:56:41 PM PST 24 Jan 17 12:56:44 PM PST 24 39607057 ps
T109 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.728074028 Jan 17 12:57:05 PM PST 24 Jan 17 12:57:07 PM PST 24 77287770 ps
T251 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3974508818 Jan 17 12:56:43 PM PST 24 Jan 17 12:56:46 PM PST 24 587433057 ps
T261 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2149944942 Jan 17 12:56:25 PM PST 24 Jan 17 12:56:27 PM PST 24 135464468 ps
T192 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3741388985 Jan 17 12:56:43 PM PST 24 Jan 17 12:56:47 PM PST 24 92366401 ps
T243 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.877840824 Jan 17 12:56:27 PM PST 24 Jan 17 12:56:37 PM PST 24 2588116693 ps
T252 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.802261717 Jan 17 12:56:44 PM PST 24 Jan 17 12:56:46 PM PST 24 126838213 ps
T253 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3450364332 Jan 17 12:56:26 PM PST 24 Jan 17 12:56:29 PM PST 24 142935826 ps
T110 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.801775749 Jan 17 12:57:02 PM PST 24 Jan 17 12:57:04 PM PST 24 129321768 ps
T111 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1881559724 Jan 17 12:56:15 PM PST 24 Jan 17 12:56:20 PM PST 24 614581049 ps
T254 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1654833670 Jan 17 12:56:57 PM PST 24 Jan 17 12:57:01 PM PST 24 655646399 ps
T249 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.381853401 Jan 17 12:56:20 PM PST 24 Jan 17 12:56:33 PM PST 24 2372078930 ps
T193 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.502567953 Jan 17 12:56:37 PM PST 24 Jan 17 12:56:45 PM PST 24 182605199 ps
T194 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1528246752 Jan 17 12:56:14 PM PST 24 Jan 17 12:56:18 PM PST 24 195783920 ps
T195 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.902787461 Jan 17 12:56:36 PM PST 24 Jan 17 12:56:49 PM PST 24 169948140 ps
T216 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.1038311371 Jan 17 12:56:27 PM PST 24 Jan 17 12:56:32 PM PST 24 584501782 ps
T255 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3265838870 Jan 17 12:56:56 PM PST 24 Jan 17 12:56:59 PM PST 24 121801431 ps
T217 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2879617238 Jan 17 12:56:56 PM PST 24 Jan 17 12:56:59 PM PST 24 572069284 ps
T256 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3121317603 Jan 17 12:56:58 PM PST 24 Jan 17 12:57:01 PM PST 24 659601643 ps
T218 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1056173682 Jan 17 12:56:59 PM PST 24 Jan 17 12:57:02 PM PST 24 38947518 ps
T295 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3694695725 Jan 17 12:57:01 PM PST 24 Jan 17 12:57:04 PM PST 24 37397236 ps
T296 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3927128923 Jan 17 12:56:25 PM PST 24 Jan 17 12:56:27 PM PST 24 43731515 ps
T297 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.4164147903 Jan 17 12:56:07 PM PST 24 Jan 17 12:56:09 PM PST 24 127567223 ps
T326 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2115128773 Jan 17 12:56:34 PM PST 24 Jan 17 12:56:43 PM PST 24 85522032 ps
T196 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2281784473 Jan 17 12:56:41 PM PST 24 Jan 17 12:56:46 PM PST 24 300275874 ps
T197 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2337505246 Jan 17 12:56:31 PM PST 24 Jan 17 12:56:37 PM PST 24 257022181 ps
T327 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.694536939 Jan 17 12:56:46 PM PST 24 Jan 17 12:56:48 PM PST 24 140867176 ps
T257 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3193977064 Jan 17 12:56:23 PM PST 24 Jan 17 12:56:27 PM PST 24 329076165 ps
T388 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1521593231 Jan 17 12:56:35 PM PST 24 Jan 17 12:56:43 PM PST 24 87845923 ps
T250 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3539604406 Jan 17 12:56:38 PM PST 24 Jan 17 12:56:58 PM PST 24 1130139525 ps
T258 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3934518168 Jan 17 12:56:46 PM PST 24 Jan 17 12:56:49 PM PST 24 646986456 ps
T389 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2299347614 Jan 17 12:56:55 PM PST 24 Jan 17 12:56:59 PM PST 24 88509909 ps
T198 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2557257480 Jan 17 12:56:50 PM PST 24 Jan 17 12:56:53 PM PST 24 122266267 ps
T328 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3010573050 Jan 17 12:56:58 PM PST 24 Jan 17 12:57:15 PM PST 24 1472145389 ps
T390 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.767426769 Jan 17 12:56:59 PM PST 24 Jan 17 12:57:01 PM PST 24 40941019 ps
T259 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3951381999 Jan 17 12:56:37 PM PST 24 Jan 17 12:56:43 PM PST 24 129625143 ps
T287 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1424397203 Jan 17 12:56:57 PM PST 24 Jan 17 12:57:07 PM PST 24 637698310 ps
T260 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3683903306 Jan 17 12:56:33 PM PST 24 Jan 17 12:56:41 PM PST 24 127044968 ps
T391 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.1307781756 Jan 17 12:56:59 PM PST 24 Jan 17 12:57:01 PM PST 24 65400968 ps
T392 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1086607979 Jan 17 12:56:56 PM PST 24 Jan 17 12:56:59 PM PST 24 71818486 ps
T199 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3325379975 Jan 17 12:56:42 PM PST 24 Jan 17 12:56:47 PM PST 24 218839543 ps
T393 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2809268320 Jan 17 12:56:21 PM PST 24 Jan 17 12:56:24 PM PST 24 517541510 ps
T394 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.695964111 Jan 17 12:56:09 PM PST 24 Jan 17 12:56:11 PM PST 24 67524937 ps
T262 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2336301819 Jan 17 12:56:22 PM PST 24 Jan 17 12:56:27 PM PST 24 115438327 ps
T395 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.715207154 Jan 17 12:56:36 PM PST 24 Jan 17 12:56:43 PM PST 24 39165363 ps
T396 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2400797467 Jan 17 12:57:01 PM PST 24 Jan 17 12:57:04 PM PST 24 568936968 ps
T397 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2527820173 Jan 17 12:56:58 PM PST 24 Jan 17 12:57:01 PM PST 24 528608549 ps
T398 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.703012509 Jan 17 12:56:57 PM PST 24 Jan 17 12:57:00 PM PST 24 579345849 ps
T263 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3694713763 Jan 17 12:56:58 PM PST 24 Jan 17 12:57:01 PM PST 24 40308234 ps
T399 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1956375454 Jan 17 12:56:55 PM PST 24 Jan 17 12:56:59 PM PST 24 133946014 ps
T400 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.7454003 Jan 17 12:56:59 PM PST 24 Jan 17 12:57:02 PM PST 24 41286638 ps
T401 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1823036763 Jan 17 12:56:56 PM PST 24 Jan 17 12:56:59 PM PST 24 38853118 ps
T402 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.406403174 Jan 17 12:56:59 PM PST 24 Jan 17 12:57:01 PM PST 24 43828380 ps
T403 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3673332345 Jan 17 12:56:57 PM PST 24 Jan 17 12:56:59 PM PST 24 138518717 ps
T264 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.482659797 Jan 17 12:56:19 PM PST 24 Jan 17 12:56:23 PM PST 24 151930649 ps
T270 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1980035824 Jan 17 12:56:31 PM PST 24 Jan 17 12:56:35 PM PST 24 136995132 ps
T271 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.131328204 Jan 17 12:56:08 PM PST 24 Jan 17 12:56:11 PM PST 24 38422251 ps
T112 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1676457764 Jan 17 12:56:41 PM PST 24 Jan 17 12:56:44 PM PST 24 260285077 ps
T245 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3355532077 Jan 17 12:56:54 PM PST 24 Jan 17 12:57:03 PM PST 24 160292051 ps
T272 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1906183475 Jan 17 12:56:33 PM PST 24 Jan 17 12:56:35 PM PST 24 41365685 ps
T273 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.701634812 Jan 17 12:57:03 PM PST 24 Jan 17 12:57:05 PM PST 24 69844482 ps
T244 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.430971487 Jan 17 12:56:31 PM PST 24 Jan 17 12:56:39 PM PST 24 194025622 ps
T274 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2959853491 Jan 17 12:56:44 PM PST 24 Jan 17 12:57:02 PM PST 24 1378908020 ps
T275 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.995937837 Jan 17 12:56:24 PM PST 24 Jan 17 12:56:26 PM PST 24 147038404 ps
T404 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1037654839 Jan 17 12:56:44 PM PST 24 Jan 17 12:56:46 PM PST 24 142416665 ps
T405 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2285894787 Jan 17 12:57:06 PM PST 24 Jan 17 12:57:09 PM PST 24 511133550 ps
T406 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2324041088 Jan 17 12:56:14 PM PST 24 Jan 17 12:56:17 PM PST 24 656824358 ps
T407 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.1837042510 Jan 17 12:56:59 PM PST 24 Jan 17 12:57:02 PM PST 24 40984396 ps
T408 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2672328365 Jan 17 12:56:42 PM PST 24 Jan 17 12:56:45 PM PST 24 235116071 ps
T248 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3585462123 Jan 17 12:56:39 PM PST 24 Jan 17 12:56:51 PM PST 24 3206358638 ps
T288 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.4016548559 Jan 17 12:56:46 PM PST 24 Jan 17 12:56:48 PM PST 24 43913874 ps
T409 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3322518877 Jan 17 12:56:34 PM PST 24 Jan 17 12:56:44 PM PST 24 890799032 ps
T410 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2776867369 Jan 17 12:56:44 PM PST 24 Jan 17 12:56:46 PM PST 24 117509426 ps
T411 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2416671317 Jan 17 12:56:44 PM PST 24 Jan 17 12:56:46 PM PST 24 71556247 ps
T412 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.221696731 Jan 17 12:57:01 PM PST 24 Jan 17 12:57:04 PM PST 24 44616405 ps
T329 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.457215298 Jan 17 12:56:44 PM PST 24 Jan 17 12:57:03 PM PST 24 2303399570 ps
T413 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.156953276 Jan 17 12:56:31 PM PST 24 Jan 17 12:56:35 PM PST 24 169420209 ps
T291 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.1569123919 Jan 17 12:56:08 PM PST 24 Jan 17 12:56:18 PM PST 24 3362711799 ps
T414 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3081705136 Jan 17 12:56:10 PM PST 24 Jan 17 12:56:14 PM PST 24 85368763 ps
T246 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.2968244538 Jan 17 12:56:15 PM PST 24 Jan 17 12:56:24 PM PST 24 295049156 ps
T415 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1096577512 Jan 17 12:56:37 PM PST 24 Jan 17 12:56:44 PM PST 24 82562343 ps
T386 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3073754962 Jan 17 12:56:54 PM PST 24 Jan 17 12:57:01 PM PST 24 395538336 ps
T416 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.3691270719 Jan 17 12:56:57 PM PST 24 Jan 17 12:56:59 PM PST 24 43748334 ps
T417 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2350827586 Jan 17 12:56:25 PM PST 24 Jan 17 12:56:27 PM PST 24 143603362 ps
T418 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.754009937 Jan 17 12:56:57 PM PST 24 Jan 17 12:56:59 PM PST 24 605057594 ps
T419 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1760259429 Jan 17 12:56:33 PM PST 24 Jan 17 12:56:43 PM PST 24 1094877880 ps
T420 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1100609375 Jan 17 12:56:20 PM PST 24 Jan 17 12:56:23 PM PST 24 484655786 ps
T421 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.2517787401 Jan 17 12:56:58 PM PST 24 Jan 17 12:57:00 PM PST 24 142724892 ps
T422 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3751772718 Jan 17 12:56:10 PM PST 24 Jan 17 12:56:12 PM PST 24 93976525 ps
T330 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.607824933 Jan 17 12:56:42 PM PST 24 Jan 17 12:57:18 PM PST 24 18308051789 ps
T333 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1438652009 Jan 17 12:56:42 PM PST 24 Jan 17 12:56:53 PM PST 24 676114523 ps
T113 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2908854121 Jan 17 12:56:23 PM PST 24 Jan 17 12:56:25 PM PST 24 65871653 ps
T423 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2114306385 Jan 17 12:56:57 PM PST 24 Jan 17 12:57:00 PM PST 24 287888579 ps
T424 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2556504116 Jan 17 12:56:35 PM PST 24 Jan 17 12:56:43 PM PST 24 70874713 ps
T247 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.370207953 Jan 17 12:56:36 PM PST 24 Jan 17 12:56:47 PM PST 24 140512980 ps
T425 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.988099277 Jan 17 12:56:24 PM PST 24 Jan 17 12:56:26 PM PST 24 127851706 ps
T426 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3065500287 Jan 17 12:56:09 PM PST 24 Jan 17 12:56:11 PM PST 24 37698099 ps
T265 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3942978146 Jan 17 12:56:11 PM PST 24 Jan 17 12:56:13 PM PST 24 138961771 ps
T300 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2830310268 Jan 17 12:56:59 PM PST 24 Jan 17 12:57:06 PM PST 24 173909625 ps
T268 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1770880753 Jan 17 12:56:09 PM PST 24 Jan 17 12:56:17 PM PST 24 504351754 ps
T301 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.1049188338 Jan 17 12:56:57 PM PST 24 Jan 17 12:56:59 PM PST 24 138005880 ps
T302 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2975259656 Jan 17 12:56:44 PM PST 24 Jan 17 12:56:46 PM PST 24 140535326 ps
T303 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2812807737 Jan 17 12:56:27 PM PST 24 Jan 17 12:56:30 PM PST 24 139463133 ps
T289 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.3370825020 Jan 17 12:56:47 PM PST 24 Jan 17 12:56:51 PM PST 24 175870880 ps
T304 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2105317654 Jan 17 12:56:24 PM PST 24 Jan 17 12:56:26 PM PST 24 40215403 ps
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