Summary for Variable keymgr_rd_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for keymgr_rd_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3738 |
1 |
|
|
T109 |
1 |
|
T192 |
1 |
|
T111 |
1 |
auto[1] |
2427 |
1 |
|
|
T185 |
1 |
|
T110 |
1 |
|
T193 |
1 |
Summary for Variable secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret2_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4473 |
1 |
|
|
T185 |
1 |
|
T109 |
1 |
|
T192 |
1 |
auto[1] |
1692 |
1 |
|
|
T5 |
2 |
|
T6 |
2 |
|
T34 |
1 |
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2715 |
1 |
|
|
T109 |
1 |
|
T192 |
1 |
|
T111 |
1 |
auto[0] |
auto[1] |
1023 |
1 |
|
|
T6 |
1 |
|
T34 |
1 |
|
T29 |
5 |
auto[1] |
auto[0] |
1758 |
1 |
|
|
T185 |
1 |
|
T110 |
1 |
|
T193 |
1 |
auto[1] |
auto[1] |
669 |
1 |
|
|
T5 |
2 |
|
T6 |
1 |
|
T29 |
4 |