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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1332	1332	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	2147483647	180590284	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1332	1332	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	2147483647	51564100	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1332	1332	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	2147483647	76230339	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1332	1332	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	2147483647	74851374	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1332	1332	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	2147483647	104359945	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1332	1332	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1332	1332	0	0
tb.dut.u_reg_core.wePulse	0	0	2147483647	3060522	0	0
tb.dut.u_scrmbl_mtx.CheckHotOne_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A	0	0	1157	1157	0	0
tb.dut.u_scrmbl_mtx.GrantKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.IdxKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A	0	0	2147483647	2147483647	0	0
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A	0	0	2147483647	39587326	0	0
tb.dut.u_scrmbl_mtx.ValidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A	0	0	1157	1157	0	0
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A	0	0	1157	1157	0	0
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A	0	0	1157	1157	0	0
tb.dut.u_tlul_adapter_sram.TlOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_A	0	0	2147483647	76216827	0	0
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.WeOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite	0	0	1157	1157	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty	0	0	2147483647	89374	0	0
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull	0	0	2147483647	89374	0	0
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A	0	0	1157	1157	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A	0	0	2147483647	76724586	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	2147483647	76724586	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A	0	0	1157	1157	0	0
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck	0	0	1157	1157	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A	0	0	2147483647	226258	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	2147483647	226258	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A	0	0	2147483647	597133	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	2147483647	597133	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1157	1157	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A	0	0	1157	1157	0	0
tb.dut.u_tlul_lc_gate.u_state_regs_A	0	0	2147483647	2147483647	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1157	1157	0	0
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1157	1157	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_arb.RoundRobin_A	0	0	2147483647	0	0	1157
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	2147483647	0	0	1157
tb.dut.u_otp_arb.RoundRobin_A	0	0	2147483647	0	0	1157
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A	0	0	2147483647	0	0	1157
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3471
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3471
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3471
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3471
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A	0	0	2147483647	2147483647	0	3471
tb.dut.u_scrmbl_mtx.RoundRobin_A	0	0	2147483647	0	0	1157

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	507	507	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	198	198	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	202	202	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	144	144	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	18	18	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	111	111	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	49	49	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	2475	2475	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	5548	5548	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1862559	1862559	1249
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	318	318	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	92	92	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	104	104	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	75	75	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	12	12	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	57	57	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	46	46	2
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	972	972	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	2524	2524	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	52592	52592	82

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	507	507	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	198	198	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	202	202	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	144	144	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	18	18	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	111	111	0
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	49	49	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	2475	2475	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	5548	5548	0
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1862559	1862559	1249
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	318	318	0
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	92	92	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	104	104	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	75	75	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	12	12	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	57	57	2
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	46	46	2
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	972	972	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	2524	2524	0
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	52592	52592	82