Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.42 92.63 91.48 92.48 92.11 93.49 96.53 95.19


Total tests in report: 1332
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
42.27 42.27 66.34 66.34 54.92 54.92 48.80 48.80 0.00 0.00 62.19 62.19 45.10 45.10 18.57 18.57 /workspace/coverage/default/4.otp_ctrl_test_access.3640111933
74.19 31.91 87.79 21.45 76.28 21.36 55.20 6.40 92.11 92.11 83.37 21.18 90.72 45.63 33.84 15.27 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1142168013
79.51 5.32 88.51 0.72 78.18 1.90 75.83 20.62 92.11 0.00 84.81 1.44 91.03 0.30 46.08 12.24 /workspace/coverage/default/10.otp_ctrl_stress_all.1687978870
83.54 4.03 88.68 0.17 80.05 1.88 82.06 6.23 92.11 0.00 85.29 0.48 91.33 0.30 65.23 19.16 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2953747885
84.95 1.42 90.23 1.55 83.21 3.15 82.17 0.11 92.11 0.00 88.18 2.89 91.86 0.53 66.92 1.69 /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.92144036
86.11 1.15 90.27 0.04 83.70 0.49 86.33 4.16 92.11 0.00 88.29 0.11 91.86 0.00 70.21 3.29 /workspace/coverage/default/48.otp_ctrl_stress_all.2419254262
87.20 1.09 90.40 0.13 85.82 2.12 86.76 0.43 92.11 0.00 88.93 0.64 92.38 0.53 74.01 3.80 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3196946925
88.04 0.84 90.54 0.13 86.33 0.52 86.77 0.01 92.11 0.00 89.14 0.21 92.46 0.08 78.90 4.89 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2011821588
88.77 0.73 90.71 0.17 86.90 0.57 87.17 0.39 92.11 0.00 90.53 1.39 94.72 2.26 79.24 0.34 /workspace/coverage/default/4.otp_ctrl_sec_cm.3125857121
89.20 0.43 90.90 0.19 87.50 0.60 87.90 0.73 92.11 0.00 90.86 0.32 94.72 0.00 80.42 1.18 /workspace/coverage/default/48.otp_ctrl_check_fail.1770300733
89.61 0.41 90.90 0.00 87.55 0.05 88.13 0.23 92.11 0.00 90.86 0.00 94.72 0.00 83.04 2.62 /workspace/coverage/default/25.otp_ctrl_stress_all.2397645267
89.92 0.31 90.90 0.00 87.83 0.27 88.85 0.72 92.11 0.00 91.02 0.16 94.72 0.00 84.05 1.01 /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.3087059952
90.20 0.27 90.90 0.00 88.02 0.19 88.87 0.02 92.11 0.00 91.02 0.00 94.72 0.00 85.74 1.69 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1001101652
90.46 0.27 90.90 0.00 88.21 0.19 88.87 0.00 92.11 0.00 91.28 0.27 94.87 0.15 87.00 1.27 /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1538763911
90.68 0.22 90.90 0.00 88.23 0.03 89.10 0.23 92.11 0.00 91.28 0.00 94.95 0.08 88.19 1.18 /workspace/coverage/default/16.otp_ctrl_stress_all.811777068
90.87 0.19 90.90 0.00 88.34 0.11 89.21 0.11 92.11 0.00 91.28 0.00 96.08 1.13 88.19 0.00 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2753576668
91.05 0.17 91.07 0.17 88.51 0.16 89.29 0.08 92.11 0.00 91.60 0.32 96.30 0.23 88.44 0.25 /workspace/coverage/default/208.otp_ctrl_init_fail.3376728609
91.21 0.17 91.07 0.00 88.51 0.00 90.20 0.90 92.11 0.00 91.60 0.00 96.30 0.00 88.69 0.25 /workspace/coverage/default/2.otp_ctrl_stress_all.121082466
91.35 0.14 91.35 0.28 89.02 0.52 90.20 0.00 92.11 0.00 91.60 0.00 96.30 0.00 88.86 0.17 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.833640191
91.48 0.13 91.35 0.00 89.54 0.52 90.44 0.24 92.11 0.00 91.76 0.16 96.30 0.00 88.86 0.00 /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3159736195
91.61 0.13 91.35 0.00 89.54 0.00 90.56 0.12 92.11 0.00 91.76 0.00 96.30 0.00 89.62 0.76 /workspace/coverage/default/5.otp_ctrl_stress_all.997999128
91.73 0.12 91.35 0.00 89.54 0.00 90.56 0.00 92.11 0.00 91.76 0.00 96.30 0.00 90.46 0.84 /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.239643507
91.84 0.12 91.41 0.06 89.67 0.14 90.92 0.36 92.11 0.00 91.87 0.11 96.38 0.08 90.55 0.08 /workspace/coverage/default/270.otp_ctrl_init_fail.2255433598
91.95 0.11 91.48 0.08 89.95 0.27 90.96 0.05 92.11 0.00 91.98 0.11 96.38 0.00 90.80 0.25 /workspace/coverage/default/46.otp_ctrl_check_fail.4023926601
92.04 0.09 91.60 0.11 90.08 0.14 91.04 0.08 92.11 0.00 92.19 0.21 96.38 0.00 90.89 0.08 /workspace/coverage/default/178.otp_ctrl_init_fail.4271241130
92.12 0.08 91.65 0.06 90.11 0.03 91.06 0.01 92.11 0.00 92.25 0.05 96.46 0.08 91.22 0.34 /workspace/coverage/default/22.otp_ctrl_macro_errs.1149506474
92.19 0.07 91.99 0.34 90.11 0.00 91.06 0.00 92.11 0.00 92.25 0.00 96.46 0.00 91.39 0.17 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.240438516
92.26 0.07 91.99 0.00 90.11 0.00 91.12 0.07 92.11 0.00 92.25 0.00 96.46 0.00 91.81 0.42 /workspace/coverage/default/1.otp_ctrl_regwen.3475440439
92.33 0.06 91.99 0.00 90.14 0.03 91.12 0.00 92.11 0.00 92.25 0.00 96.46 0.00 92.24 0.42 /workspace/coverage/default/3.otp_ctrl_stress_all.4018056685
92.39 0.06 92.07 0.08 90.22 0.08 91.12 0.00 92.11 0.00 92.35 0.11 96.46 0.00 92.41 0.17 /workspace/coverage/default/10.otp_ctrl_check_fail.4055659430
92.45 0.06 92.13 0.06 90.24 0.03 91.32 0.20 92.11 0.00 92.41 0.05 96.46 0.00 92.49 0.08 /workspace/coverage/default/230.otp_ctrl_init_fail.3408962209
92.50 0.05 92.20 0.08 90.30 0.05 91.37 0.05 92.11 0.00 92.51 0.11 96.46 0.00 92.57 0.08 /workspace/coverage/default/126.otp_ctrl_init_fail.758525011
92.56 0.05 92.24 0.04 90.35 0.05 91.37 0.00 92.11 0.00 92.62 0.11 96.46 0.00 92.74 0.17 /workspace/coverage/default/37.otp_ctrl_check_fail.3602947117
92.61 0.05 92.30 0.06 90.46 0.11 91.37 0.00 92.11 0.00 92.73 0.11 96.46 0.00 92.83 0.08 /workspace/coverage/default/1.otp_ctrl_init_fail.3157640151
92.66 0.05 92.30 0.00 90.46 0.00 91.39 0.01 92.11 0.00 92.73 0.00 96.46 0.00 93.16 0.34 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.4425111
92.71 0.05 92.37 0.08 90.57 0.11 91.39 0.00 92.11 0.00 92.89 0.16 96.46 0.00 93.16 0.00 /workspace/coverage/default/80.otp_ctrl_init_fail.1205288821
92.76 0.05 92.37 0.00 90.57 0.00 91.39 0.00 92.11 0.00 92.89 0.00 96.46 0.00 93.50 0.34 /workspace/coverage/default/32.otp_ctrl_regwen.3651996898
92.80 0.05 92.43 0.06 90.60 0.03 91.41 0.02 92.11 0.00 92.94 0.05 96.53 0.08 93.59 0.08 /workspace/coverage/default/43.otp_ctrl_macro_errs.1513141696
92.85 0.05 92.52 0.09 90.60 0.00 91.41 0.00 92.11 0.00 92.99 0.05 96.53 0.00 93.76 0.17 /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.4169997209
92.89 0.04 92.58 0.06 90.62 0.03 91.49 0.08 92.11 0.00 93.05 0.05 96.53 0.00 93.84 0.08 /workspace/coverage/default/239.otp_ctrl_init_fail.2890144713
92.93 0.04 92.58 0.00 90.90 0.27 91.50 0.01 92.11 0.00 93.05 0.00 96.53 0.00 93.84 0.00 /workspace/coverage/default/11.otp_ctrl_alert_test.1732001647
92.97 0.04 92.58 0.00 90.90 0.00 91.68 0.18 92.11 0.00 93.05 0.00 96.53 0.00 93.92 0.08 /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3478777151
93.00 0.04 92.58 0.00 90.90 0.00 91.68 0.00 92.11 0.00 93.05 0.00 96.53 0.00 94.18 0.25 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4205925484
93.03 0.03 92.64 0.06 90.92 0.03 91.68 0.00 92.11 0.00 93.10 0.05 96.53 0.00 94.26 0.08 /workspace/coverage/default/225.otp_ctrl_init_fail.1520690099
93.06 0.03 92.69 0.06 90.98 0.05 91.72 0.04 92.11 0.00 93.16 0.05 96.53 0.00 94.26 0.00 /workspace/coverage/default/42.otp_ctrl_check_fail.1362645241
93.09 0.03 92.69 0.00 90.98 0.00 91.74 0.02 92.11 0.00 93.16 0.00 96.53 0.00 94.43 0.17 /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.3786998521
93.11 0.02 92.69 0.00 90.98 0.00 91.74 0.00 92.11 0.00 93.16 0.00 96.53 0.00 94.60 0.17 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3271665264
93.14 0.02 92.69 0.00 90.98 0.00 91.74 0.00 92.11 0.00 93.16 0.00 96.53 0.00 94.77 0.17 /workspace/coverage/default/28.otp_ctrl_stress_all.35579811
93.16 0.02 92.75 0.06 91.01 0.03 91.76 0.03 92.11 0.00 93.21 0.05 96.53 0.00 94.77 0.00 /workspace/coverage/default/27.otp_ctrl_init_fail.769436860
93.18 0.02 92.79 0.04 91.06 0.05 91.76 0.00 92.11 0.00 93.26 0.05 96.53 0.00 94.77 0.00 /workspace/coverage/default/118.otp_ctrl_init_fail.1634501900
93.20 0.02 92.83 0.04 91.11 0.05 91.76 0.00 92.11 0.00 93.32 0.05 96.53 0.00 94.77 0.00 /workspace/coverage/default/284.otp_ctrl_init_fail.3946535455
93.22 0.02 92.86 0.04 91.14 0.03 91.79 0.02 92.11 0.00 93.37 0.05 96.53 0.00 94.77 0.00 /workspace/coverage/default/133.otp_ctrl_init_fail.1383348970
93.24 0.02 92.86 0.00 91.14 0.00 91.84 0.06 92.11 0.00 93.37 0.00 96.53 0.00 94.85 0.08 /workspace/coverage/default/41.otp_ctrl_stress_all.3105039911
93.26 0.02 92.86 0.00 91.14 0.00 91.97 0.13 92.11 0.00 93.37 0.00 96.53 0.00 94.85 0.00 /workspace/coverage/default/123.otp_ctrl_init_fail.2072146140
93.28 0.02 92.90 0.04 91.17 0.03 91.97 0.00 92.11 0.00 93.42 0.05 96.53 0.00 94.85 0.00 /workspace/coverage/default/101.otp_ctrl_init_fail.1117190268
93.30 0.02 92.90 0.00 91.17 0.00 92.08 0.11 92.11 0.00 93.42 0.00 96.53 0.00 94.85 0.00 /workspace/coverage/default/199.otp_ctrl_init_fail.2421724659
93.31 0.02 92.90 0.00 91.20 0.03 92.08 0.00 92.11 0.00 93.42 0.00 96.53 0.00 94.94 0.08 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2072072452
93.32 0.01 92.90 0.00 91.20 0.00 92.09 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.02 0.08 /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2701150599
93.34 0.01 92.90 0.00 91.20 0.00 92.09 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.11 0.08 /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2547234046
93.35 0.01 92.90 0.00 91.25 0.05 92.12 0.03 92.11 0.00 93.42 0.00 96.53 0.00 95.11 0.00 /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.4203998590
93.36 0.01 92.90 0.00 91.25 0.00 92.21 0.08 92.11 0.00 93.42 0.00 96.53 0.00 95.11 0.00 /workspace/coverage/default/100.otp_ctrl_init_fail.484110240
93.37 0.01 92.90 0.00 91.25 0.00 92.21 0.00 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.08 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.894308842
93.38 0.01 92.90 0.00 91.25 0.00 92.26 0.06 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/19.otp_ctrl_init_fail.2636524153
93.39 0.01 92.90 0.00 91.30 0.05 92.26 0.00 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/43.otp_ctrl_stress_all.2883033479
93.39 0.01 92.94 0.04 91.30 0.00 92.26 0.00 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/0.otp_ctrl_sec_cm.3905892500
93.40 0.01 92.94 0.00 91.30 0.00 92.30 0.04 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/19.otp_ctrl_parallel_key_req.3284082530
93.40 0.01 92.94 0.00 91.33 0.03 92.30 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/35.otp_ctrl_check_fail.209927309
93.41 0.01 92.94 0.00 91.33 0.00 92.33 0.03 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/71.otp_ctrl_init_fail.3195823556
93.41 0.01 92.94 0.00 91.36 0.03 92.33 0.00 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.4069706608
93.42 0.01 92.94 0.00 91.36 0.00 92.35 0.02 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1262821443
93.42 0.01 92.94 0.00 91.36 0.00 92.38 0.02 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/149.otp_ctrl_init_fail.1775814601
93.42 0.01 92.96 0.02 91.36 0.00 92.38 0.00 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/14.otp_ctrl_test_access.277019196
93.42 0.01 92.96 0.00 91.36 0.00 92.39 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/109.otp_ctrl_init_fail.670132378
93.43 0.01 92.96 0.00 91.36 0.00 92.40 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/11.otp_ctrl_init_fail.350746939
93.43 0.01 92.96 0.00 91.36 0.00 92.42 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/155.otp_ctrl_init_fail.2090143518
93.43 0.01 92.96 0.00 91.36 0.00 92.43 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/34.otp_ctrl_init_fail.2957367322
93.43 0.01 92.96 0.00 91.36 0.00 92.45 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/44.otp_ctrl_dai_lock.35911579
93.43 0.01 92.96 0.00 91.36 0.00 92.46 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/93.otp_ctrl_init_fail.1741187210
93.43 0.01 92.96 0.00 91.36 0.00 92.47 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/0.otp_ctrl_init_fail.1530430239
93.44 0.01 92.96 0.00 91.36 0.00 92.47 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/241.otp_ctrl_init_fail.1282980318
93.44 0.01 92.96 0.00 91.36 0.00 92.48 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/78.otp_ctrl_init_fail.2998281448
93.44 0.01 92.96 0.00 91.36 0.00 92.48 0.01 92.11 0.00 93.42 0.00 96.53 0.00 95.19 0.00 /workspace/coverage/default/17.otp_ctrl_regwen.1916186743

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1324810731
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.830697455
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1567645721
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3300073105
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1101607495
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.203074263
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1083833594
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3435740737
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3658852211
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2632694549
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.280108398
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4122600581
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1043433390
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2398176766
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1913616327
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1427895916
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.118525640
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.823793116
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4004050099
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2097782669
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1999485163
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2523826231
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4251678036
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.144612296
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2856819548
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3325734458
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3393488379
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3845740329
/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.580047399
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3971340773
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.89166238
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4266614960
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1510970646
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2332628769
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1740820455
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2555600903
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.866396178
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1309700567
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3683324973
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1036400854
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.4264727559
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2109596506
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2630048034
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1099319972
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3968173145
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2316051740
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1133729092
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3190513652
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1541658801
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3235732610
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3672037422
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3486101934
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.6105137
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3186470925
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1697538387
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/workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.4221553908
/workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.1842690381
/workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1534789433
/workspace/coverage/default/94.otp_ctrl_init_fail.3055156624
/workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.54432460
/workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.3596940999
/workspace/coverage/default/95.otp_ctrl_init_fail.3220444305
/workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.959882315
/workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.793493892
/workspace/coverage/default/96.otp_ctrl_init_fail.1606601685
/workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1690017418
/workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1969859820
/workspace/coverage/default/97.otp_ctrl_init_fail.2511427106
/workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.4043471689
/workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3929674057
/workspace/coverage/default/98.otp_ctrl_init_fail.1011805262
/workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.262980120
/workspace/coverage/default/99.otp_ctrl_init_fail.1933403623
/workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.97589992
/workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.4139105023



Total test records in report: 1332
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T16 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1142168013 Jan 21 07:32:49 PM PST 24 Jan 21 07:33:00 PM PST 24 630312972 ps
T109 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.4074622483 Jan 21 07:32:20 PM PST 24 Jan 21 07:32:28 PM PST 24 176575468 ps
T110 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3196946925 Jan 21 07:32:32 PM PST 24 Jan 21 07:32:42 PM PST 24 68062588 ps
T114 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1036400854 Jan 21 07:32:36 PM PST 24 Jan 21 07:32:45 PM PST 24 86366293 ps
T111 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.4425111 Jan 21 07:33:05 PM PST 24 Jan 21 07:33:09 PM PST 24 147720128 ps
T112 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2011821588 Jan 21 07:32:24 PM PST 24 Jan 21 07:32:31 PM PST 24 124093255 ps
T113 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.930973148 Jan 21 07:33:06 PM PST 24 Jan 21 07:33:09 PM PST 24 40283668 ps
T181 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2024606395 Jan 21 07:32:58 PM PST 24 Jan 21 07:33:07 PM PST 24 92787185 ps
T182 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.203074263 Jan 21 07:32:01 PM PST 24 Jan 21 07:32:04 PM PST 24 38614895 ps
T183 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.4038850455 Jan 21 07:32:30 PM PST 24 Jan 21 07:32:41 PM PST 24 974206407 ps
T115 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4266614960 Jan 21 07:32:49 PM PST 24 Jan 21 07:33:11 PM PST 24 9921354646 ps
T193 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2727198903 Jan 21 07:33:00 PM PST 24 Jan 21 07:33:07 PM PST 24 71781778 ps
T283 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3191740477 Jan 21 07:32:11 PM PST 24 Jan 21 07:32:14 PM PST 24 66263906 ps
T210 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4009721541 Jan 21 07:32:15 PM PST 24 Jan 21 07:32:28 PM PST 24 470873437 ps
T184 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3751055444 Jan 21 07:32:12 PM PST 24 Jan 21 07:32:17 PM PST 24 955024861 ps
T247 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2742225292 Jan 21 07:32:26 PM PST 24 Jan 21 07:32:36 PM PST 24 921895784 ps
T284 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.342016333 Jan 21 07:33:08 PM PST 24 Jan 21 07:33:13 PM PST 24 70654072 ps
T248 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3658852211 Jan 21 07:32:00 PM PST 24 Jan 21 07:32:05 PM PST 24 173224262 ps
T249 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1249946391 Jan 21 07:32:55 PM PST 24 Jan 21 07:33:05 PM PST 24 94393058 ps
T185 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3683324973 Jan 21 07:32:48 PM PST 24 Jan 21 07:33:00 PM PST 24 185052329 ps
T387 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.165957096 Jan 21 07:32:18 PM PST 24 Jan 21 07:32:27 PM PST 24 131078681 ps
T297 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.647015349 Jan 21 07:33:07 PM PST 24 Jan 21 07:33:10 PM PST 24 37934197 ps
T386 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2856819548 Jan 21 07:32:30 PM PST 24 Jan 21 07:32:40 PM PST 24 95643598 ps
T211 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2953747885 Jan 21 07:32:21 PM PST 24 Jan 21 07:32:45 PM PST 24 4679173680 ps
T388 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1190108215 Jan 21 07:33:10 PM PST 24 Jan 21 07:33:15 PM PST 24 543995745 ps
T186 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2646774267 Jan 21 07:32:32 PM PST 24 Jan 21 07:32:42 PM PST 24 138092479 ps
T187 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.833640191 Jan 21 07:32:31 PM PST 24 Jan 21 07:32:44 PM PST 24 373158817 ps
T287 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4004050099 Jan 21 07:32:01 PM PST 24 Jan 21 07:32:04 PM PST 24 516098608 ps
T116 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.504057413 Jan 21 07:32:14 PM PST 24 Jan 21 07:32:22 PM PST 24 85520979 ps
T117 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2398176766 Jan 21 07:32:01 PM PST 24 Jan 21 07:32:05 PM PST 24 236258949 ps
T253 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.925374882 Jan 21 07:32:23 PM PST 24 Jan 21 07:32:31 PM PST 24 80929743 ps
T254 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.6105137 Jan 21 07:32:46 PM PST 24 Jan 21 07:32:57 PM PST 24 43622834 ps
T217 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.342913915 Jan 21 07:32:30 PM PST 24 Jan 21 07:32:55 PM PST 24 1182690076 ps
T241 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2408519134 Jan 21 08:12:53 PM PST 24 Jan 21 08:13:06 PM PST 24 9512830137 ps
T255 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1101607495 Jan 21 07:32:02 PM PST 24 Jan 21 07:32:05 PM PST 24 110352153 ps
T256 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.876604812 Jan 21 08:10:26 PM PST 24 Jan 21 08:10:30 PM PST 24 146219486 ps
T188 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3486101934 Jan 21 07:32:44 PM PST 24 Jan 21 07:32:57 PM PST 24 123202820 ps
T260 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1740820455 Jan 21 07:32:38 PM PST 24 Jan 21 07:32:46 PM PST 24 76629054 ps
T245 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2254144440 Jan 21 07:32:20 PM PST 24 Jan 21 07:32:50 PM PST 24 4773537849 ps
T261 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3106993863 Jan 21 07:33:07 PM PST 24 Jan 21 07:33:10 PM PST 24 81196953 ps
T250 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1001101652 Jan 21 07:32:31 PM PST 24 Jan 21 07:32:56 PM PST 24 19446831518 ps
T246 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2574305131 Jan 21 08:54:01 PM PST 24 Jan 21 08:54:55 PM PST 24 18318318912 ps
T252 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1309700567 Jan 21 07:32:34 PM PST 24 Jan 21 07:33:02 PM PST 24 4624615499 ps
T257 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3188525779 Jan 21 07:32:32 PM PST 24 Jan 21 07:32:41 PM PST 24 42929785 ps
T262 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.69273334 Jan 21 07:32:56 PM PST 24 Jan 21 07:33:06 PM PST 24 533981868 ps
T189 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3059622652 Jan 21 07:32:28 PM PST 24 Jan 21 07:32:40 PM PST 24 132401714 ps
T190 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.4112797647 Jan 21 07:32:44 PM PST 24 Jan 21 07:32:58 PM PST 24 84551580 ps
T275 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1229479795 Jan 21 07:33:06 PM PST 24 Jan 21 07:33:09 PM PST 24 53723390 ps
T258 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2753576668 Jan 21 07:32:23 PM PST 24 Jan 21 07:32:32 PM PST 24 78774082 ps
T270 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1911204173 Jan 21 07:32:32 PM PST 24 Jan 21 07:32:41 PM PST 24 61732283 ps
T191 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3906973562 Jan 21 07:32:32 PM PST 24 Jan 21 07:32:44 PM PST 24 250994603 ps
T259 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4122600581 Jan 21 07:32:05 PM PST 24 Jan 21 07:32:10 PM PST 24 1155836865 ps
T276 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.651198032 Jan 21 07:32:15 PM PST 24 Jan 21 07:32:23 PM PST 24 73848678 ps
T389 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.118525640 Jan 21 07:32:03 PM PST 24 Jan 21 07:32:07 PM PST 24 43161243 ps
T390 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1636070279 Jan 21 08:27:06 PM PST 24 Jan 21 08:27:09 PM PST 24 148421181 ps
T279 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2631585976 Jan 21 07:32:55 PM PST 24 Jan 21 07:33:06 PM PST 24 66835647 ps
T391 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1083833594 Jan 21 07:32:02 PM PST 24 Jan 21 07:32:05 PM PST 24 37636126 ps
T280 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1126531995 Jan 21 07:32:55 PM PST 24 Jan 21 07:33:06 PM PST 24 248476572 ps
T192 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2630048034 Jan 21 07:32:36 PM PST 24 Jan 21 07:32:49 PM PST 24 233515258 ps
T392 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2703665204 Jan 21 07:33:05 PM PST 24 Jan 21 07:33:09 PM PST 24 106374735 ps
T242 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1510970646 Jan 21 07:32:36 PM PST 24 Jan 21 07:32:48 PM PST 24 1623358786 ps
T385 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1541658801 Jan 21 07:32:47 PM PST 24 Jan 21 07:32:59 PM PST 24 292596232 ps
T393 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2571891198 Jan 21 07:33:08 PM PST 24 Jan 21 07:33:13 PM PST 24 154191677 ps
T263 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.4093876014 Jan 21 07:32:13 PM PST 24 Jan 21 07:32:20 PM PST 24 75437024 ps
T394 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2555600903 Jan 21 07:32:37 PM PST 24 Jan 21 07:32:46 PM PST 24 143703782 ps
T281 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.997191273 Jan 21 07:32:53 PM PST 24 Jan 21 07:33:02 PM PST 24 258850764 ps
T291 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2316051740 Jan 21 07:32:37 PM PST 24 Jan 21 07:32:46 PM PST 24 518610361 ps
T251 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.4267753509 Jan 21 07:32:15 PM PST 24 Jan 21 07:32:27 PM PST 24 140606858 ps
T292 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3845740329 Jan 21 07:32:35 PM PST 24 Jan 21 07:32:45 PM PST 24 40258178 ps
T244 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2072072452 Jan 21 07:32:47 PM PST 24 Jan 21 07:32:59 PM PST 24 93873970 ps
T282 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.995649920 Jan 21 07:32:30 PM PST 24 Jan 21 07:32:48 PM PST 24 661547910 ps
T395 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.573496911 Jan 21 07:32:55 PM PST 24 Jan 21 07:33:05 PM PST 24 74808785 ps
T243 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1635100347 Jan 21 07:32:28 PM PST 24 Jan 21 07:32:40 PM PST 24 1118605244 ps
T288 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.280108398 Jan 21 07:31:58 PM PST 24 Jan 21 07:32:21 PM PST 24 2438785305 ps
T325 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2463481183 Jan 21 07:32:57 PM PST 24 Jan 21 07:33:15 PM PST 24 1733332159 ps
T396 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.674763332 Jan 21 07:33:07 PM PST 24 Jan 21 07:33:10 PM PST 24 547261635 ps
T397 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2872332501 Jan 21 07:32:51 PM PST 24 Jan 21 07:33:00 PM PST 24 174212271 ps
T398 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3186470925 Jan 21 07:32:47 PM PST 24 Jan 21 07:32:57 PM PST 24 72982231 ps
T399 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.41540984 Jan 21 07:32:24 PM PST 24 Jan 21 07:32:31 PM PST 24 88269114 ps
T400 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.812216925 Jan 21 08:10:23 PM PST 24 Jan 21 08:10:29 PM PST 24 195159404 ps
T401 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.4264727559 Jan 21 07:32:38 PM PST 24 Jan 21 07:32:46 PM PST 24 550243704 ps
T402 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3549593401 Jan 21 07:32:57 PM PST 24 Jan 21 07:33:06 PM PST 24 137349801 ps
T403 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.844102837 Jan 21 07:32:28 PM PST 24 Jan 21 07:32:40 PM PST 24 106274403 ps
T404 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1563094934 Jan 21 07:33:05 PM PST 24 Jan 21 07:33:08 PM PST 24 111077698 ps
T285 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3817058150 Jan 21 07:32:47 PM PST 24 Jan 21 07:32:58 PM PST 24 134463534 ps
T405 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2496648731 Jan 21 07:32:11 PM PST 24 Jan 21 07:32:15 PM PST 24 299336568 ps
T406 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4251678036 Jan 21 07:32:48 PM PST 24 Jan 21 07:33:02 PM PST 24 207879250 ps
T407 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1224407871 Jan 21 07:32:30 PM PST 24 Jan 21 07:32:41 PM PST 24 140146577 ps
T408 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1261072905 Jan 21 07:32:23 PM PST 24 Jan 21 07:32:33 PM PST 24 58300503 ps
T286 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3300073105 Jan 21 07:32:03 PM PST 24 Jan 21 07:32:09 PM PST 24 219539318 ps
T409 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3277135822 Jan 21 07:32:07 PM PST 24 Jan 21 07:32:16 PM PST 24 125026689 ps
T323 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4205925484 Jan 21 07:32:34 PM PST 24 Jan 21 07:32:59 PM PST 24 2322046836 ps
T410 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1359748012 Jan 21 07:32:34 PM PST 24 Jan 21 07:32:44 PM PST 24 139155482 ps
T411 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3433528295 Jan 21 07:32:57 PM PST 24 Jan 21 07:33:06 PM PST 24 124904413 ps
T412 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3176157701 Jan 21 07:33:06 PM PST 24 Jan 21 07:33:09 PM PST 24 82263897 ps
T413 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.348818232 Jan 21 07:33:06 PM PST 24 Jan 21 07:33:09 PM PST 24 41423719 ps
T264 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3235732610 Jan 21 07:32:48 PM PST 24 Jan 21 07:32:59 PM PST 24 38172424 ps
T414 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1043433390 Jan 21 07:32:05 PM PST 24 Jan 21 07:32:16 PM PST 24 675156023 ps
T415 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.378955064 Jan 21 07:32:45 PM PST 24 Jan 21 07:33:00 PM PST 24 218981782 ps
T416 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3806202565 Jan 21 08:36:35 PM PST 24 Jan 21 08:36:38 PM PST 24 36442894 ps
T417 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.823793116 Jan 21 07:32:04 PM PST 24 Jan 21 07:32:08 PM PST 24 137107893 ps
T418 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.4031350201 Jan 21 07:33:07 PM PST 24 Jan 21 07:33:10 PM PST 24 39624021 ps
T265 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3968173145 Jan 21 07:32:48 PM PST 24 Jan 21 07:32:59 PM PST 24 166874125 ps
T419 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1097998798 Jan 21 07:33:06 PM PST 24 Jan 21 07:33:09 PM PST 24 44311286 ps
T420 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2201915318 Jan 21 07:32:53 PM PST 24 Jan 21 07:33:02 PM PST 24 144159663 ps
T421 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3190513652 Jan 21 07:32:42 PM PST 24 Jan 21 07:32:57 PM PST 24 195510444 ps
T289 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1913616327 Jan 21 07:32:10 PM PST 24 Jan 21 07:32:15 PM PST 24 98323816 ps
T422 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2491039371 Jan 21 07:33:05 PM PST 24 Jan 21 07:33:09 PM PST 24 582431369 ps
T423 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.89166238 Jan 21 07:32:48 PM PST 24 Jan 21 07:33:01 PM PST 24 334131246 ps
T324 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.156161164 Jan 21 07:32:17 PM PST 24 Jan 21 07:32:43 PM PST 24 1137298680 ps
T424 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.277262249 Jan 21 07:33:10 PM PST 24 Jan 21 07:33:14 PM PST 24 132608306 ps
T425 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1133729092 Jan 21 07:32:42 PM PST 24 Jan 21 07:32:56 PM PST 24 616945000 ps
T426 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1099319972 Jan 21 07:32:47 PM PST 24 Jan 21 07:33:01 PM PST 24 226818133 ps
T427 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3325734458 Jan 21 07:32:37 PM PST 24 Jan 21 07:32:46 PM PST 24 41558990 ps
T428 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.4004459871 Jan 21 07:32:08 PM PST 24 Jan 21 07:32:13 PM PST 24 512089775 ps
T429 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1999485163 Jan 21 07:31:59 PM PST 24 Jan 21 07:32:06 PM PST 24 62005957 ps
T430 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.830697455 Jan 21 07:32:03 PM PST 24 Jan 21 07:32:11 PM PST 24 689167979 ps
T431 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1932212391 Jan 21 07:33:07 PM PST 24 Jan 21 07:33:10 PM PST 24 140672799 ps
T432 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.101192102 Jan 21 07:32:26 PM PST 24 Jan 21 07:32:44 PM PST 24 2110092463 ps
T433 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3725554936 Jan 21 07:32:52 PM PST 24 Jan 21 07:33:00 PM PST 24 577755662 ps
T434 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3672037422 Jan 21 07:32:44 PM PST 24 Jan 21 07:32:56 PM PST 24 79578758 ps
T435 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3435740737 Jan 21 07:31:48 PM PST 24 Jan 21 07:31:54 PM PST 24 131448176 ps
T436 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.4146430944 Jan 21 07:32:13 PM PST 24 Jan 21 07:32:19 PM PST 24 546570570 ps
T437 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1427895916 Jan 21 07:32:00 PM PST 24 Jan 21 07:32:04 PM PST 24 43580239 ps
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