Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	1	14	93.33
Crosses	51	7	44	86.27

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	8	0	8	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	51	7	44	86.27	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48017	1			T7	2		T107	386		T29	210
access_err	84516	1			T1	124		T2	44		T3	405
write_blank_err	429	1			T9	1		T95	14		T14	2
ecc_uncorr_err	69241	1			T9	582		T95	409		T118	188
ecc_corr_err	1341	1			T29	51		T118	6		T119	8
no_err	383615	1			T1	266		T2	128		T3	827

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lc_or_oob	44902	1			T1	42		T2	8		T3	112
secret2	64569	1			T1	34		T2	36		T3	164
secret1	84547	1			T1	54		T2	20		T3	126
secret0	110377	1			T1	56		T2	26		T3	98
hw_cfg	74573	1			T1	44		T2	14		T3	160
owner_sw_cfg	62307	1			T1	44		T2	26		T3	288
creator_sw_cfg	66155	1			T1	64		T2	8		T3	152
vendor_test	79729	1			T1	52		T2	34		T3	132

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	51	7	44	86.27	7
Automatically Generated Cross Bins	51	7	44	86.27	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	7

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	lc_or_oob	2766	1			T312	107		T203	99		T313	130
fsm_err	secret2	3237	1			T174	35		T207	93		T314	341
fsm_err	secret1	6558	1			T102	225		T91	259		T92	609
fsm_err	secret0	5667	1			T102	232		T315	164		T316	199
fsm_err	hw_cfg	5632	1			T317	163		T318	160		T195	325
fsm_err	owner_sw_cfg	2718	1			T7	2		T119	40		T319	70
fsm_err	creator_sw_cfg	4338	1			T95	45		T204	30		T123	32
fsm_err	vendor_test	17101	1			T107	386		T29	210		T320	165
access_err	lc_or_oob	19681	1			T1	21		T2	4		T3	56
access_err	secret2	14398	1			T1	3		T2	13		T3	46
access_err	secret1	6967	1			T1	22		T2	7		T3	51
access_err	secret0	5850	1			T1	23		T2	12		T3	27
access_err	hw_cfg	3270	1			T1	10		T2	2		T3	20
access_err	owner_sw_cfg	13184	1			T1	21		T2	3		T3	118
access_err	creator_sw_cfg	12937	1			T1	16		T3	59		T6	3
access_err	vendor_test	8229	1			T1	8		T2	3		T3	28
write_blank_err	secret2	17	1			T212	1		T214	1		T321	1
write_blank_err	secret1	40	1			T9	1		T102	2		T212	1
write_blank_err	secret0	86	1			T95	1		T14	2		T121	1
write_blank_err	hw_cfg	32	1			T102	1		T215	1		T304	3
write_blank_err	owner_sw_cfg	112	1			T95	4		T102	7		T212	1
write_blank_err	creator_sw_cfg	122	1			T95	8		T102	7		T122	4
write_blank_err	vendor_test	20	1			T95	1		T102	1		T322	1
ecc_uncorr_err	secret2	7167	1			T118	47		T123	28		T212	569
ecc_uncorr_err	secret1	15338	1			T9	582		T118	52		T119	110
ecc_uncorr_err	secret0	31624	1			T95	409		T14	211		T121	170
ecc_uncorr_err	hw_cfg	11505	1			T118	44		T102	410		T120	313
ecc_uncorr_err	owner_sw_cfg	1157	1			T118	45		T123	23		T301	48
ecc_uncorr_err	creator_sw_cfg	2450	1			T119	49		T120	126		T123	27
ecc_corr_err	secret2	101	1			T130	5		T44	4		T33	4
ecc_corr_err	secret1	200	1			T29	4		T119	2		T130	4
ecc_corr_err	secret0	174	1			T29	2		T118	1		T14	1
ecc_corr_err	hw_cfg	322	1			T29	22		T118	1		T119	2
ecc_corr_err	owner_sw_cfg	171	1			T29	10		T118	1		T119	2
ecc_corr_err	creator_sw_cfg	190	1			T29	13		T118	1		T130	1
ecc_corr_err	vendor_test	183	1			T118	2		T119	2		T102	1
no_err	lc_or_oob	22455	1			T1	21		T2	4		T3	56
no_err	secret2	39649	1			T1	31		T2	23		T3	118
no_err	secret1	55444	1			T1	32		T2	13		T3	75
no_err	secret0	66976	1			T1	33		T2	14		T3	71
no_err	hw_cfg	53812	1			T1	34		T2	12		T3	140
no_err	owner_sw_cfg	44965	1			T1	23		T2	23		T3	170
no_err	creator_sw_cfg	46118	1			T1	48		T2	8		T3	93
no_err	vendor_test	54196	1			T1	44		T2	31		T3	104

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
lc_or_oob_ignore	0	Excluded