Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.42 92.63 91.48 92.48 92.11 93.49 96.53 95.19


Total test records in report: 1332
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1260 /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3569469496 Jan 21 10:18:00 PM PST 24 Jan 22 12:21:44 AM PST 24 519215290893 ps
T1261 /workspace/coverage/default/14.otp_ctrl_dai_errs.1550748158 Jan 21 10:13:15 PM PST 24 Jan 21 10:13:28 PM PST 24 382425936 ps
T1262 /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.742483191 Jan 21 10:13:23 PM PST 24 Jan 21 11:40:25 PM PST 24 350871645603 ps
T1263 /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.853033786 Jan 21 10:13:58 PM PST 24 Jan 21 10:14:05 PM PST 24 1575074202 ps
T1264 /workspace/coverage/default/6.otp_ctrl_regwen.3398460150 Jan 21 10:12:06 PM PST 24 Jan 21 10:12:12 PM PST 24 344796386 ps
T1265 /workspace/coverage/default/8.otp_ctrl_alert_test.1396506184 Jan 21 10:12:42 PM PST 24 Jan 21 10:12:47 PM PST 24 208675875 ps
T1266 /workspace/coverage/default/261.otp_ctrl_init_fail.300862890 Jan 21 10:56:47 PM PST 24 Jan 21 10:56:51 PM PST 24 142166535 ps
T1267 /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2398505804 Jan 21 10:17:09 PM PST 24 Jan 21 10:17:35 PM PST 24 6687717639 ps
T1268 /workspace/coverage/default/43.otp_ctrl_dai_errs.421604796 Jan 21 10:16:34 PM PST 24 Jan 21 10:16:42 PM PST 24 122059617 ps
T1269 /workspace/coverage/default/41.otp_ctrl_init_fail.889326866 Jan 21 10:16:14 PM PST 24 Jan 21 10:16:26 PM PST 24 1775025218 ps
T1270 /workspace/coverage/default/0.otp_ctrl_stress_all.1383673470 Jan 21 10:11:37 PM PST 24 Jan 21 10:12:23 PM PST 24 5670059172 ps
T1271 /workspace/coverage/default/20.otp_ctrl_init_fail.2753400421 Jan 21 10:13:50 PM PST 24 Jan 21 10:14:00 PM PST 24 508386123 ps
T1272 /workspace/coverage/default/14.otp_ctrl_parallel_key_req.4080217896 Jan 21 10:13:19 PM PST 24 Jan 21 10:13:39 PM PST 24 746133196 ps
T1273 /workspace/coverage/default/49.otp_ctrl_macro_errs.2410053039 Jan 21 10:17:03 PM PST 24 Jan 21 10:17:21 PM PST 24 2070833427 ps
T1274 /workspace/coverage/default/203.otp_ctrl_init_fail.1334562223 Jan 21 10:20:22 PM PST 24 Jan 21 10:20:32 PM PST 24 684278142 ps
T1275 /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.303185886 Jan 21 10:11:44 PM PST 24 Jan 21 10:12:05 PM PST 24 1041310812 ps
T1276 /workspace/coverage/default/8.otp_ctrl_macro_errs.3953177165 Jan 21 10:12:37 PM PST 24 Jan 21 10:13:00 PM PST 24 907498634 ps
T1277 /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.1079070291 Jan 21 10:18:45 PM PST 24 Jan 21 10:18:55 PM PST 24 158611728 ps
T1278 /workspace/coverage/default/27.otp_ctrl_parallel_key_req.4051993732 Jan 21 10:14:41 PM PST 24 Jan 21 10:15:03 PM PST 24 3465901123 ps
T1279 /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1037452309 Jan 21 10:19:47 PM PST 24 Jan 21 10:19:55 PM PST 24 116210184 ps
T1280 /workspace/coverage/default/27.otp_ctrl_smoke.612927610 Jan 21 10:14:35 PM PST 24 Jan 21 10:14:46 PM PST 24 1524286474 ps
T1281 /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2172937842 Jan 21 10:17:05 PM PST 24 Jan 22 12:58:08 AM PST 24 3817801780652 ps
T231 /workspace/coverage/default/226.otp_ctrl_init_fail.3451747049 Jan 21 10:20:25 PM PST 24 Jan 21 10:20:32 PM PST 24 607500458 ps
T1282 /workspace/coverage/default/201.otp_ctrl_init_fail.3836689811 Jan 21 10:20:22 PM PST 24 Jan 21 10:20:33 PM PST 24 490907737 ps
T1283 /workspace/coverage/default/25.otp_ctrl_init_fail.986523256 Jan 21 10:14:29 PM PST 24 Jan 21 10:14:36 PM PST 24 144624118 ps
T1284 /workspace/coverage/default/36.otp_ctrl_dai_errs.248617686 Jan 21 10:15:43 PM PST 24 Jan 21 10:15:58 PM PST 24 399679591 ps
T1285 /workspace/coverage/default/160.otp_ctrl_init_fail.1446384188 Jan 21 10:19:32 PM PST 24 Jan 21 10:19:41 PM PST 24 2210854642 ps
T1286 /workspace/coverage/default/260.otp_ctrl_init_fail.2733324917 Jan 21 10:20:47 PM PST 24 Jan 21 10:21:06 PM PST 24 165798432 ps
T1287 /workspace/coverage/default/49.otp_ctrl_dai_lock.2912387208 Jan 21 10:17:06 PM PST 24 Jan 21 10:17:19 PM PST 24 505869643 ps
T1288 /workspace/coverage/default/165.otp_ctrl_init_fail.2837387076 Jan 21 10:19:34 PM PST 24 Jan 21 10:19:43 PM PST 24 494193261 ps
T1289 /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.873311401 Jan 21 10:18:59 PM PST 24 Jan 21 10:19:09 PM PST 24 1658561301 ps
T1290 /workspace/coverage/default/8.otp_ctrl_smoke.3864630371 Jan 21 10:37:59 PM PST 24 Jan 21 10:38:07 PM PST 24 296315371 ps
T1291 /workspace/coverage/default/69.otp_ctrl_init_fail.3130671999 Jan 21 10:17:46 PM PST 24 Jan 21 10:17:59 PM PST 24 2383923401 ps
T1292 /workspace/coverage/default/16.otp_ctrl_alert_test.2261567573 Jan 21 10:13:30 PM PST 24 Jan 21 10:13:35 PM PST 24 93563289 ps
T1293 /workspace/coverage/default/219.otp_ctrl_init_fail.1620882782 Jan 21 10:49:13 PM PST 24 Jan 21 10:49:20 PM PST 24 578441296 ps
T1294 /workspace/coverage/default/11.otp_ctrl_test_access.2979299828 Jan 21 11:11:45 PM PST 24 Jan 21 11:11:59 PM PST 24 738882775 ps
T1295 /workspace/coverage/default/40.otp_ctrl_stress_all.255314888 Jan 21 10:40:57 PM PST 24 Jan 21 10:42:28 PM PST 24 5382903675 ps
T1296 /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1011054061 Jan 21 10:20:13 PM PST 24 Jan 21 10:20:28 PM PST 24 364100718 ps
T1297 /workspace/coverage/default/259.otp_ctrl_init_fail.2375665323 Jan 21 10:20:45 PM PST 24 Jan 21 10:21:03 PM PST 24 535357898 ps
T271 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1719374411 Jan 21 07:32:07 PM PST 24 Jan 21 07:32:14 PM PST 24 107164386 ps
T1298 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2325475178 Jan 21 07:32:53 PM PST 24 Jan 21 07:33:01 PM PST 24 138565543 ps
T1299 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2556733008 Jan 21 07:32:10 PM PST 24 Jan 21 07:32:16 PM PST 24 196054316 ps
T1300 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1806630018 Jan 21 07:32:05 PM PST 24 Jan 21 07:32:09 PM PST 24 130872647 ps
T1301 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2109596506 Jan 21 07:32:38 PM PST 24 Jan 21 07:32:46 PM PST 24 46170541 ps
T1302 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2332628769 Jan 21 07:32:42 PM PST 24 Jan 21 07:32:55 PM PST 24 617921232 ps
T1303 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3393488379 Jan 21 07:32:43 PM PST 24 Jan 21 07:32:57 PM PST 24 113351449 ps
T272 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.841143181 Jan 21 07:32:23 PM PST 24 Jan 21 07:32:31 PM PST 24 560199601 ps
T1304 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1575179383 Jan 21 07:33:05 PM PST 24 Jan 21 07:33:09 PM PST 24 38659481 ps
T1305 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.4023654158 Jan 21 07:33:08 PM PST 24 Jan 21 07:33:12 PM PST 24 68192334 ps
T327 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.240438516 Jan 21 07:32:47 PM PST 24 Jan 21 07:33:16 PM PST 24 1381887375 ps
T1306 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2632694549 Jan 21 07:31:53 PM PST 24 Jan 21 07:32:00 PM PST 24 341932917 ps
T273 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3939819795 Jan 21 07:32:06 PM PST 24 Jan 21 07:32:11 PM PST 24 129077656 ps
T1307 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2342331788 Jan 21 07:32:54 PM PST 24 Jan 21 07:33:07 PM PST 24 1173709177 ps
T1308 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3971340773 Jan 21 07:32:36 PM PST 24 Jan 21 07:32:45 PM PST 24 81115794 ps
T1309 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.610984055 Jan 21 07:32:25 PM PST 24 Jan 21 07:32:33 PM PST 24 47942416 ps
T1310 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.580047399 Jan 21 07:32:43 PM PST 24 Jan 21 07:32:55 PM PST 24 79618252 ps
T1311 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1567645721 Jan 21 07:32:02 PM PST 24 Jan 21 07:32:06 PM PST 24 232925562 ps
T329 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.894308842 Jan 21 07:32:10 PM PST 24 Jan 21 07:32:23 PM PST 24 880440815 ps
T1312 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.1155142803 Jan 21 07:32:22 PM PST 24 Jan 21 07:32:30 PM PST 24 953680631 ps
T1313 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.883096072 Jan 21 07:32:22 PM PST 24 Jan 21 07:32:30 PM PST 24 71433214 ps
T1314 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2125564657 Jan 21 07:32:21 PM PST 24 Jan 21 07:32:30 PM PST 24 219296229 ps
T1315 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.4211743784 Jan 21 07:32:14 PM PST 24 Jan 21 07:32:23 PM PST 24 156658751 ps
T1316 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1703338002 Jan 21 07:32:22 PM PST 24 Jan 21 07:32:30 PM PST 24 101652496 ps
T1317 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1056670927 Jan 21 07:32:57 PM PST 24 Jan 21 07:33:06 PM PST 24 44239818 ps
T1318 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.609145731 Jan 21 07:32:13 PM PST 24 Jan 21 07:32:19 PM PST 24 45887742 ps
T326 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.771167846 Jan 21 07:32:13 PM PST 24 Jan 21 07:32:37 PM PST 24 2586244318 ps
T1319 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3179874973 Jan 21 07:32:17 PM PST 24 Jan 21 07:32:29 PM PST 24 203730906 ps
T1320 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3711377619 Jan 21 07:32:21 PM PST 24 Jan 21 07:32:28 PM PST 24 236394099 ps
T328 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3271665264 Jan 21 07:32:45 PM PST 24 Jan 21 07:33:13 PM PST 24 1273135549 ps
T1321 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3239265737 Jan 21 07:32:17 PM PST 24 Jan 21 07:32:27 PM PST 24 130889696 ps
T1322 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2423121655 Jan 21 07:32:32 PM PST 24 Jan 21 07:32:47 PM PST 24 2131158101 ps
T1323 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3189835471 Jan 21 07:32:17 PM PST 24 Jan 21 07:32:29 PM PST 24 371362097 ps
T274 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1808697737 Jan 21 07:32:16 PM PST 24 Jan 21 07:32:27 PM PST 24 556917541 ps
T1324 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1697538387 Jan 21 07:32:44 PM PST 24 Jan 21 07:32:57 PM PST 24 849397131 ps
T1325 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3150152443 Jan 21 07:32:27 PM PST 24 Jan 21 07:32:42 PM PST 24 1029617348 ps
T1326 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.457996607 Jan 21 07:32:57 PM PST 24 Jan 21 07:33:06 PM PST 24 73709619 ps
T1327 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2927634923 Jan 21 07:33:09 PM PST 24 Jan 21 07:33:14 PM PST 24 54601822 ps
T1328 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.866396178 Jan 21 07:32:38 PM PST 24 Jan 21 07:32:47 PM PST 24 184251396 ps
T1329 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3524623767 Jan 21 07:32:22 PM PST 24 Jan 21 07:32:29 PM PST 24 105658178 ps
T1330 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2097782669 Jan 21 07:32:10 PM PST 24 Jan 21 07:32:14 PM PST 24 201775744 ps
T1331 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.214699689 Jan 21 07:32:30 PM PST 24 Jan 21 07:32:40 PM PST 24 112926876 ps
T1332 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1803977156 Jan 21 07:32:45 PM PST 24 Jan 21 07:33:04 PM PST 24 1281867336 ps

Test location /workspace/coverage/default/4.otp_ctrl_test_access.3640111933
Short name T3
Test name
Test status
Simulation time 2204607408 ps
CPU time 24.17 seconds
Started Jan 21 10:12:04 PM PST 24
Finished Jan 21 10:12:32 PM PST 24
Peak memory 247016 kb
Host smart-85967e37-217a-404f-a0f4-24ac00afe22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640111933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3640111933
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.1142168013
Short name T16
Test name
Test status
Simulation time 630312972 ps
CPU time 2.63 seconds
Started Jan 21 07:32:49 PM PST 24
Finished Jan 21 07:33:00 PM PST 24
Peak memory 230100 kb
Host smart-0f861353-1368-40af-8a3a-8cfea26b4f48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142168013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.1142168013
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.1687978870
Short name T95
Test name
Test status
Simulation time 27771250625 ps
CPU time 141.45 seconds
Started Jan 21 10:12:54 PM PST 24
Finished Jan 21 10:15:17 PM PST 24
Peak memory 244248 kb
Host smart-76dba826-9629-4aa6-a55c-ecad2c8b2715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687978870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.1687978870
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2953747885
Short name T211
Test name
Test status
Simulation time 4679173680 ps
CPU time 18.94 seconds
Started Jan 21 07:32:21 PM PST 24
Finished Jan 21 07:32:45 PM PST 24
Peak memory 230196 kb
Host smart-4dd1b257-2850-4156-933b-3225b48f4a05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953747885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2953747885
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.92144036
Short name T7
Test name
Test status
Simulation time 111091985337 ps
CPU time 2890.81 seconds
Started Jan 21 10:15:19 PM PST 24
Finished Jan 21 11:03:50 PM PST 24
Peak memory 888832 kb
Host smart-6b0c3396-fa19-418f-aab3-75b4f55f467a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92144036 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.92144036
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.2419254262
Short name T102
Test name
Test status
Simulation time 8830835751 ps
CPU time 81.37 seconds
Started Jan 21 10:17:01 PM PST 24
Finished Jan 21 10:18:30 PM PST 24
Peak memory 247088 kb
Host smart-37040cad-4cf5-49f0-a52a-4f98706259ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419254262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.2419254262
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3196946925
Short name T110
Test name
Test status
Simulation time 68062588 ps
CPU time 2.35 seconds
Started Jan 21 07:32:32 PM PST 24
Finished Jan 21 07:32:42 PM PST 24
Peak memory 238352 kb
Host smart-d45db65b-a354-420f-b20a-3b2f9766de7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196946925 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3196946925
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2011821588
Short name T112
Test name
Test status
Simulation time 124093255 ps
CPU time 1.5 seconds
Started Jan 21 07:32:24 PM PST 24
Finished Jan 21 07:32:31 PM PST 24
Peak memory 230128 kb
Host smart-72711cef-bdab-4fb5-b058-eeb9fbeed762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011821588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2011821588
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3125857121
Short name T219
Test name
Test status
Simulation time 14197573280 ps
CPU time 165.7 seconds
Started Jan 21 10:12:07 PM PST 24
Finished Jan 21 10:14:55 PM PST 24
Peak memory 268900 kb
Host smart-0674fe1b-1c7c-4e74-bb06-34c721065d51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125857121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3125857121
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.1770300733
Short name T29
Test name
Test status
Simulation time 2341350719 ps
CPU time 18.56 seconds
Started Jan 21 10:17:00 PM PST 24
Finished Jan 21 10:17:26 PM PST 24
Peak memory 238892 kb
Host smart-8eb2e70f-c40c-474a-b23e-54cac95b2281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770300733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1770300733
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.2397645267
Short name T309
Test name
Test status
Simulation time 125880861863 ps
CPU time 191.12 seconds
Started Jan 21 10:14:38 PM PST 24
Finished Jan 21 10:17:52 PM PST 24
Peak memory 246992 kb
Host smart-beaa7670-bfa3-451a-a584-a99a5f58e604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397645267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.2397645267
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.3087059952
Short name T137
Test name
Test status
Simulation time 914688570 ps
CPU time 17.18 seconds
Started Jan 21 10:12:48 PM PST 24
Finished Jan 21 10:13:08 PM PST 24
Peak memory 238784 kb
Host smart-40f23e3c-1cb0-4769-a8aa-c59c8ba9c158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3087059952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3087059952
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1001101652
Short name T250
Test name
Test status
Simulation time 19446831518 ps
CPU time 17.31 seconds
Started Jan 21 07:32:31 PM PST 24
Finished Jan 21 07:32:56 PM PST 24
Peak memory 230456 kb
Host smart-58ef1a1a-a678-40f0-a04e-a6dea0cb84ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001101652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.1001101652
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1538763911
Short name T208
Test name
Test status
Simulation time 616615934004 ps
CPU time 4317.17 seconds
Started Jan 21 10:18:15 PM PST 24
Finished Jan 21 11:30:22 PM PST 24
Peak memory 417532 kb
Host smart-911dae63-e590-4989-9c4b-a86d684334ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538763911 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.1538763911
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.811777068
Short name T178
Test name
Test status
Simulation time 12106595197 ps
CPU time 73.61 seconds
Started Jan 21 10:13:31 PM PST 24
Finished Jan 21 10:14:47 PM PST 24
Peak memory 240484 kb
Host smart-79df9b4e-fd44-426e-9720-4bfeea26a585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811777068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.
811777068
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.2753576668
Short name T258
Test name
Test status
Simulation time 78774082 ps
CPU time 2.83 seconds
Started Jan 21 07:32:23 PM PST 24
Finished Jan 21 07:32:32 PM PST 24
Peak memory 230060 kb
Host smart-649a1dd2-5b32-4312-9a9f-3aba475a745f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753576668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.2753576668
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.3376728609
Short name T142
Test name
Test status
Simulation time 405240178 ps
CPU time 4.6 seconds
Started Jan 21 10:20:25 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 240852 kb
Host smart-46deaf28-d3f4-4de3-8bb3-f0c357dec284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376728609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3376728609
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.121082466
Short name T98
Test name
Test status
Simulation time 2257598194 ps
CPU time 43.51 seconds
Started Jan 21 10:11:47 PM PST 24
Finished Jan 21 10:12:33 PM PST 24
Peak memory 247076 kb
Host smart-23129846-29b8-4ad2-835c-8137a9430125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121082466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.121082466
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.833640191
Short name T187
Test name
Test status
Simulation time 373158817 ps
CPU time 4.34 seconds
Started Jan 21 07:32:31 PM PST 24
Finished Jan 21 07:32:44 PM PST 24
Peak memory 238456 kb
Host smart-f9196af9-84b3-4112-9c30-43b74a14c0e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833640191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.833640191
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3159736195
Short name T4
Test name
Test status
Simulation time 4049953542686 ps
CPU time 6230.09 seconds
Started Jan 21 10:17:48 PM PST 24
Finished Jan 22 12:01:45 AM PST 24
Peak memory 677188 kb
Host smart-846a63f3-3ac9-4254-be48-914d1832554a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159736195 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3159736195
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.997999128
Short name T348
Test name
Test status
Simulation time 17705966878 ps
CPU time 113.02 seconds
Started Jan 21 10:12:05 PM PST 24
Finished Jan 21 10:14:01 PM PST 24
Peak memory 243524 kb
Host smart-936d60b9-5015-4c15-9e9b-feccfc33828a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997999128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.997999128
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.239643507
Short name T362
Test name
Test status
Simulation time 4303382643767 ps
CPU time 7972.39 seconds
Started Jan 21 10:11:39 PM PST 24
Finished Jan 22 12:24:35 AM PST 24
Peak memory 279984 kb
Host smart-17a1a05b-41f2-4096-bb3d-27d559f7e439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239643507 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.239643507
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2255433598
Short name T38
Test name
Test status
Simulation time 437845685 ps
CPU time 5.19 seconds
Started Jan 21 10:20:43 PM PST 24
Finished Jan 21 10:20:57 PM PST 24
Peak memory 238736 kb
Host smart-f442c59a-f23b-4500-8c31-edb5c38d8604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255433598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2255433598
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.4023926601
Short name T33
Test name
Test status
Simulation time 1654460132 ps
CPU time 19.14 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:17:12 PM PST 24
Peak memory 246988 kb
Host smart-61d44793-f016-4c07-8af3-8ed6eef694a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023926601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.4023926601
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.4271241130
Short name T41
Test name
Test status
Simulation time 156507698 ps
CPU time 3.88 seconds
Started Jan 21 10:19:52 PM PST 24
Finished Jan 21 10:20:03 PM PST 24
Peak memory 246920 kb
Host smart-5f4b779f-d020-46f8-9fcc-58cf33919c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271241130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.4271241130
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.1149506474
Short name T123
Test name
Test status
Simulation time 1224445242 ps
CPU time 12.21 seconds
Started Jan 21 10:14:11 PM PST 24
Finished Jan 21 10:14:27 PM PST 24
Peak memory 238756 kb
Host smart-c4101289-8a01-4e7d-8df2-4bf79983f365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149506474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1149506474
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.240438516
Short name T327
Test name
Test status
Simulation time 1381887375 ps
CPU time 19.93 seconds
Started Jan 21 07:32:47 PM PST 24
Finished Jan 21 07:33:16 PM PST 24
Peak memory 230312 kb
Host smart-12d23406-8320-4d24-af5c-5e571a4a2044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240438516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in
tg_err.240438516
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3475440439
Short name T240
Test name
Test status
Simulation time 3581809434 ps
CPU time 9.25 seconds
Started Jan 21 10:11:37 PM PST 24
Finished Jan 21 10:11:48 PM PST 24
Peak memory 238936 kb
Host smart-619694e8-7c54-4972-8deb-fbebbbf15a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475440439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3475440439
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.4018056685
Short name T813
Test name
Test status
Simulation time 37975421244 ps
CPU time 178 seconds
Started Jan 21 10:11:55 PM PST 24
Finished Jan 21 10:14:55 PM PST 24
Peak memory 255760 kb
Host smart-84a14361-72a7-479a-acaf-b08c3542fa00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018056685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
4018056685
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.4055659430
Short name T63
Test name
Test status
Simulation time 722686003 ps
CPU time 12.92 seconds
Started Jan 21 10:12:46 PM PST 24
Finished Jan 21 10:13:01 PM PST 24
Peak memory 247032 kb
Host smart-a0b101e0-768a-4a39-aadd-61af6712901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055659430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.4055659430
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3408962209
Short name T152
Test name
Test status
Simulation time 142217440 ps
CPU time 4.25 seconds
Started Jan 21 10:20:26 PM PST 24
Finished Jan 21 10:20:34 PM PST 24
Peak memory 238680 kb
Host smart-46b6bbd9-a8b3-46c7-8c48-f5ec51f8067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408962209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3408962209
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.758525011
Short name T26
Test name
Test status
Simulation time 178557594 ps
CPU time 4.92 seconds
Started Jan 21 10:18:48 PM PST 24
Finished Jan 21 10:18:59 PM PST 24
Peak memory 238744 kb
Host smart-c0f87190-613e-4de8-96d9-a2eab04a36f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758525011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.758525011
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3602947117
Short name T1123
Test name
Test status
Simulation time 1047090377 ps
CPU time 11.09 seconds
Started Jan 21 10:15:48 PM PST 24
Finished Jan 21 10:16:06 PM PST 24
Peak memory 238860 kb
Host smart-b92fe8d9-4806-49d4-b0c2-2f91518165e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602947117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3602947117
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.3157640151
Short name T59
Test name
Test status
Simulation time 155831594 ps
CPU time 3.67 seconds
Started Jan 21 10:11:37 PM PST 24
Finished Jan 21 10:11:43 PM PST 24
Peak memory 241388 kb
Host smart-048857e7-e4ab-4aba-b594-abb020ef9c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157640151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3157640151
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.4425111
Short name T111
Test name
Test status
Simulation time 147720128 ps
CPU time 1.64 seconds
Started Jan 21 07:33:05 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 230144 kb
Host smart-c34f3835-60df-4b47-aafe-912d7b3c3477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4425111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.4425111
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1205288821
Short name T654
Test name
Test status
Simulation time 270891618 ps
CPU time 3.81 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:18:18 PM PST 24
Peak memory 238736 kb
Host smart-6a2c0b6e-b3c8-405d-ad9a-474150158f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205288821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1205288821
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.3651996898
Short name T719
Test name
Test status
Simulation time 266114876 ps
CPU time 7.05 seconds
Started Jan 21 10:15:10 PM PST 24
Finished Jan 21 10:15:34 PM PST 24
Peak memory 238780 kb
Host smart-8312f616-edf5-4743-8bcb-86ab8fb13a2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651996898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.3651996898
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.1513141696
Short name T129
Test name
Test status
Simulation time 511400721 ps
CPU time 10.73 seconds
Started Jan 21 10:16:26 PM PST 24
Finished Jan 21 10:16:38 PM PST 24
Peak memory 238752 kb
Host smart-782eeeb0-a051-4a72-b6b5-a47585755ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513141696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1513141696
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.4169997209
Short name T19
Test name
Test status
Simulation time 3034654606344 ps
CPU time 7400.05 seconds
Started Jan 21 10:16:41 PM PST 24
Finished Jan 22 12:20:13 AM PST 24
Peak memory 272472 kb
Host smart-7cfc102e-ca0d-464a-944c-cff0ce1346e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169997209 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.4169997209
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.2890144713
Short name T35
Test name
Test status
Simulation time 819850277 ps
CPU time 5.01 seconds
Started Jan 21 10:20:24 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 238644 kb
Host smart-6a58ae6c-482e-44ae-b561-c830a2b253dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890144713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2890144713
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.1732001647
Short name T446
Test name
Test status
Simulation time 807929671 ps
CPU time 1.83 seconds
Started Jan 21 10:12:55 PM PST 24
Finished Jan 21 10:12:59 PM PST 24
Peak memory 238680 kb
Host smart-a8612273-74aa-44d8-b373-3afa41de10f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732001647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1732001647
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3478777151
Short name T177
Test name
Test status
Simulation time 713460791 ps
CPU time 22.58 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:40 PM PST 24
Peak memory 243460 kb
Host smart-05a82e99-74a1-4933-b6ac-524e79c16007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478777151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3478777151
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4205925484
Short name T323
Test name
Test status
Simulation time 2322046836 ps
CPU time 17.34 seconds
Started Jan 21 07:32:34 PM PST 24
Finished Jan 21 07:32:59 PM PST 24
Peak memory 241488 kb
Host smart-8b466e17-1f95-4f91-a8da-f37850b2c1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205925484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.4205925484
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1520690099
Short name T75
Test name
Test status
Simulation time 2397018772 ps
CPU time 5.29 seconds
Started Jan 21 10:20:28 PM PST 24
Finished Jan 21 10:20:36 PM PST 24
Peak memory 238856 kb
Host smart-0ac7e345-4264-4f0b-a048-861d3523a43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520690099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1520690099
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.1362645241
Short name T44
Test name
Test status
Simulation time 1246777577 ps
CPU time 12.24 seconds
Started Jan 21 10:16:28 PM PST 24
Finished Jan 21 10:16:42 PM PST 24
Peak memory 247200 kb
Host smart-9d0c2572-ff84-40e5-84c2-92bee2463b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362645241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1362645241
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.3786998521
Short name T566
Test name
Test status
Simulation time 1482189704192 ps
CPU time 6573.64 seconds
Started Jan 21 10:14:43 PM PST 24
Finished Jan 22 12:04:30 AM PST 24
Peak memory 1012300 kb
Host smart-251ab018-a0d4-4eaf-98c8-1d52d5ef6755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786998521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.3786998521
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3271665264
Short name T328
Test name
Test status
Simulation time 1273135549 ps
CPU time 17.67 seconds
Started Jan 21 07:32:45 PM PST 24
Finished Jan 21 07:33:13 PM PST 24
Peak memory 230360 kb
Host smart-97a44224-7b93-45ba-8b94-6ba1a0383d05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271665264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.3271665264
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.35579811
Short name T776
Test name
Test status
Simulation time 81360521387 ps
CPU time 180.23 seconds
Started Jan 21 10:14:46 PM PST 24
Finished Jan 21 10:17:58 PM PST 24
Peak memory 255196 kb
Host smart-f164004f-56b1-4b59-a72e-6603f83fb5be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35579811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.35579811
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.769436860
Short name T57
Test name
Test status
Simulation time 161872994 ps
CPU time 4.06 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 10:14:59 PM PST 24
Peak memory 238412 kb
Host smart-14689fcb-212f-47f8-b8a0-c51c9d776c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769436860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.769436860
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.1634501900
Short name T302
Test name
Test status
Simulation time 1756780089 ps
CPU time 3.91 seconds
Started Jan 21 10:18:39 PM PST 24
Finished Jan 21 10:18:48 PM PST 24
Peak memory 246948 kb
Host smart-68079c17-5a3d-4154-b70b-1cc424a4f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634501900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1634501900
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3946535455
Short name T462
Test name
Test status
Simulation time 2427537183 ps
CPU time 7.17 seconds
Started Jan 21 10:21:02 PM PST 24
Finished Jan 21 10:21:24 PM PST 24
Peak memory 238800 kb
Host smart-5fafaa35-8a35-459c-9859-43123c61b70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946535455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3946535455
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.1383348970
Short name T69
Test name
Test status
Simulation time 284736909 ps
CPU time 4.02 seconds
Started Jan 21 10:42:17 PM PST 24
Finished Jan 21 10:42:22 PM PST 24
Peak memory 240848 kb
Host smart-d3fd115a-cc03-4a0f-bfe6-59864e9bd2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383348970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1383348970
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3105039911
Short name T176
Test name
Test status
Simulation time 22955114556 ps
CPU time 49.29 seconds
Started Jan 21 10:16:22 PM PST 24
Finished Jan 21 10:17:13 PM PST 24
Peak memory 239948 kb
Host smart-c072422b-9662-4969-99e1-fd476d842730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105039911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3105039911
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.2072146140
Short name T618
Test name
Test status
Simulation time 1999929094 ps
CPU time 5.97 seconds
Started Jan 21 10:18:57 PM PST 24
Finished Jan 21 10:19:07 PM PST 24
Peak memory 238732 kb
Host smart-ef047712-fd98-412e-85e9-53ba1300bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072146140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.2072146140
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.1117190268
Short name T135
Test name
Test status
Simulation time 124213943 ps
CPU time 3.66 seconds
Started Jan 21 10:18:27 PM PST 24
Finished Jan 21 10:18:37 PM PST 24
Peak memory 241436 kb
Host smart-bd0f2e8d-f89a-4c69-9131-9811721207d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117190268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1117190268
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.2421724659
Short name T234
Test name
Test status
Simulation time 159393764 ps
CPU time 4.03 seconds
Started Jan 21 10:20:12 PM PST 24
Finished Jan 21 10:20:23 PM PST 24
Peak memory 241076 kb
Host smart-a7637f2f-8636-4d72-832f-96c5292bd918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421724659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2421724659
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2072072452
Short name T244
Test name
Test status
Simulation time 93873970 ps
CPU time 2.93 seconds
Started Jan 21 07:32:47 PM PST 24
Finished Jan 21 07:32:59 PM PST 24
Peak memory 238488 kb
Host smart-4ff6a2a4-1185-4acf-ae5a-f299643a9252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072072452 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2072072452
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2701150599
Short name T342
Test name
Test status
Simulation time 110122363 ps
CPU time 4.47 seconds
Started Jan 21 10:20:06 PM PST 24
Finished Jan 21 10:20:17 PM PST 24
Peak memory 241644 kb
Host smart-654ae398-4cf3-4f04-9444-ebdd21f97df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701150599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2701150599
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2547234046
Short name T215
Test name
Test status
Simulation time 883282580741 ps
CPU time 4122.78 seconds
Started Jan 21 10:14:45 PM PST 24
Finished Jan 21 11:23:39 PM PST 24
Peak memory 948636 kb
Host smart-c15ca00a-eb6a-4fc9-b407-dbd6b80f9537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547234046 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.2547234046
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.4203998590
Short name T347
Test name
Test status
Simulation time 1831645767 ps
CPU time 14.83 seconds
Started Jan 21 10:16:37 PM PST 24
Finished Jan 21 10:16:55 PM PST 24
Peak memory 238680 kb
Host smart-84b5f0bf-1317-4d21-8f6b-1083040dc122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203998590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.4203998590
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.484110240
Short name T236
Test name
Test status
Simulation time 128811156 ps
CPU time 3.61 seconds
Started Jan 21 10:18:26 PM PST 24
Finished Jan 21 10:18:37 PM PST 24
Peak memory 238672 kb
Host smart-bf7c8759-4a52-4935-97d7-72f49e367880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484110240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.484110240
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.894308842
Short name T329
Test name
Test status
Simulation time 880440815 ps
CPU time 10.22 seconds
Started Jan 21 07:32:10 PM PST 24
Finished Jan 21 07:32:23 PM PST 24
Peak memory 230208 kb
Host smart-8cdd272f-39a2-4b4d-a182-e47ee29eaecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894308842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_int
g_err.894308842
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.2636524153
Short name T230
Test name
Test status
Simulation time 284678520 ps
CPU time 3.79 seconds
Started Jan 21 10:13:40 PM PST 24
Finished Jan 21 10:13:48 PM PST 24
Peak memory 246892 kb
Host smart-c77979f6-cb69-458e-8e72-3749378b1060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636524153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.2636524153
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2883033479
Short name T199
Test name
Test status
Simulation time 17377311235 ps
CPU time 133.43 seconds
Started Jan 21 10:16:37 PM PST 24
Finished Jan 21 10:18:53 PM PST 24
Peak memory 247052 kb
Host smart-33eb4e85-68d5-44b6-a2bb-15a841e38747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883033479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2883033479
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3905892500
Short name T22
Test name
Test status
Simulation time 35395123997 ps
CPU time 200.73 seconds
Started Jan 21 10:11:36 PM PST 24
Finished Jan 21 10:14:59 PM PST 24
Peak memory 268684 kb
Host smart-337bb42b-3b13-4083-9eea-eabec794369e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905892500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3905892500
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.3284082530
Short name T381
Test name
Test status
Simulation time 4180735492 ps
CPU time 12.01 seconds
Started Jan 21 10:13:46 PM PST 24
Finished Jan 21 10:14:05 PM PST 24
Peak memory 238936 kb
Host smart-217f8f94-9067-4718-8309-7450c4e9a19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284082530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3284082530
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.209927309
Short name T298
Test name
Test status
Simulation time 998368458 ps
CPU time 13.15 seconds
Started Jan 21 10:15:27 PM PST 24
Finished Jan 21 10:15:56 PM PST 24
Peak memory 246936 kb
Host smart-1b84b773-f190-4e0b-bfc1-340bb3d1f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209927309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.209927309
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.3195823556
Short name T83
Test name
Test status
Simulation time 384346391 ps
CPU time 4.12 seconds
Started Jan 21 10:17:42 PM PST 24
Finished Jan 21 10:17:50 PM PST 24
Peak memory 246900 kb
Host smart-4f0308d3-bd36-4600-9565-869a12209559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195823556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.3195823556
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.4069706608
Short name T200
Test name
Test status
Simulation time 4112895874694 ps
CPU time 9412.38 seconds
Started Jan 21 10:17:55 PM PST 24
Finished Jan 22 12:54:57 AM PST 24
Peak memory 909588 kb
Host smart-bb4f4d76-89eb-4e80-a04b-51ea6d4afee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069706608 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.4069706608
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.1262821443
Short name T349
Test name
Test status
Simulation time 735784182 ps
CPU time 15.22 seconds
Started Jan 21 10:15:25 PM PST 24
Finished Jan 21 10:15:57 PM PST 24
Peak memory 238760 kb
Host smart-d7a7314f-7dce-4ae4-9be0-eba9d8f9f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262821443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1262821443
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.1775814601
Short name T955
Test name
Test status
Simulation time 325565482 ps
CPU time 2.94 seconds
Started Jan 21 10:19:19 PM PST 24
Finished Jan 21 10:19:28 PM PST 24
Peak memory 238684 kb
Host smart-6778188c-51e4-4763-96a7-1b68c949f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775814601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1775814601
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.277019196
Short name T674
Test name
Test status
Simulation time 7663145731 ps
CPU time 70.65 seconds
Started Jan 21 10:13:19 PM PST 24
Finished Jan 21 10:14:33 PM PST 24
Peak memory 244512 kb
Host smart-04d32f95-da8a-4095-aa38-8d015a35e443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277019196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.277019196
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.670132378
Short name T233
Test name
Test status
Simulation time 1495533462 ps
CPU time 4.85 seconds
Started Jan 21 10:18:35 PM PST 24
Finished Jan 21 10:18:44 PM PST 24
Peak memory 240828 kb
Host smart-e0b81e21-830a-4352-b4ce-b331662263db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670132378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.670132378
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.350746939
Short name T232
Test name
Test status
Simulation time 1780546151 ps
CPU time 6.23 seconds
Started Jan 21 10:12:47 PM PST 24
Finished Jan 21 10:12:56 PM PST 24
Peak memory 240676 kb
Host smart-ef4d0730-d2c4-46e9-8e07-d0bb849d67df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350746939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.350746939
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2090143518
Short name T80
Test name
Test status
Simulation time 356419316 ps
CPU time 4.61 seconds
Started Jan 21 10:19:31 PM PST 24
Finished Jan 21 10:19:40 PM PST 24
Peak memory 240876 kb
Host smart-bf27ba8b-a6bd-48b5-9863-931854384da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090143518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2090143518
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.2957367322
Short name T848
Test name
Test status
Simulation time 469035883 ps
CPU time 4.27 seconds
Started Jan 21 10:15:23 PM PST 24
Finished Jan 21 10:15:45 PM PST 24
Peak memory 238744 kb
Host smart-e62a5f3a-7b85-4c1e-b831-b9ee2e5abf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957367322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2957367322
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.35911579
Short name T101
Test name
Test status
Simulation time 12206846097 ps
CPU time 24.98 seconds
Started Jan 21 10:16:40 PM PST 24
Finished Jan 21 10:17:16 PM PST 24
Peak memory 238960 kb
Host smart-b082a207-b004-4dfd-94e0-09515c2e26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35911579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.35911579
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.1741187210
Short name T81
Test name
Test status
Simulation time 243072828 ps
CPU time 4.33 seconds
Started Jan 21 10:18:05 PM PST 24
Finished Jan 21 10:18:19 PM PST 24
Peak memory 240884 kb
Host smart-58c0c62f-ee98-4e58-8ed4-12e3a72b5bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741187210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1741187210
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.1530430239
Short name T77
Test name
Test status
Simulation time 729295286 ps
CPU time 4.36 seconds
Started Jan 21 10:11:23 PM PST 24
Finished Jan 21 10:11:34 PM PST 24
Peak memory 242736 kb
Host smart-b7c32265-ff64-48e8-a17e-58413876a2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530430239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1530430239
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.1282980318
Short name T962
Test name
Test status
Simulation time 450314101 ps
CPU time 5.09 seconds
Started Jan 21 10:20:35 PM PST 24
Finished Jan 21 10:20:43 PM PST 24
Peak memory 241188 kb
Host smart-7bc7acac-296a-4483-99d7-56b7b233953e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282980318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1282980318
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2998281448
Short name T1053
Test name
Test status
Simulation time 339828405 ps
CPU time 4.66 seconds
Started Jan 21 10:17:49 PM PST 24
Finished Jan 21 10:18:01 PM PST 24
Peak memory 238716 kb
Host smart-b88d22cc-bc0d-4336-bc96-12a8b7248d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998281448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2998281448
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1916186743
Short name T333
Test name
Test status
Simulation time 397318913 ps
CPU time 6.59 seconds
Started Jan 21 10:13:36 PM PST 24
Finished Jan 21 10:13:44 PM PST 24
Peak memory 243988 kb
Host smart-b4d5bb48-697b-4883-89df-75d6855d5c7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916186743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1916186743
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1324810731
Short name T438
Test name
Test status
Simulation time 177951102 ps
CPU time 2.6 seconds
Started Jan 21 07:32:06 PM PST 24
Finished Jan 21 07:32:10 PM PST 24
Peak memory 230200 kb
Host smart-20b2097d-cc87-4b10-9215-d1745613cc1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324810731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1324810731
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.830697455
Short name T430
Test name
Test status
Simulation time 689167979 ps
CPU time 5.7 seconds
Started Jan 21 07:32:03 PM PST 24
Finished Jan 21 07:32:11 PM PST 24
Peak memory 230052 kb
Host smart-3cb4c26b-bdb7-443a-b99d-4a0cc9f3110b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830697455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b
ash.830697455
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1567645721
Short name T1311
Test name
Test status
Simulation time 232925562 ps
CPU time 1.78 seconds
Started Jan 21 07:32:02 PM PST 24
Finished Jan 21 07:32:06 PM PST 24
Peak memory 230100 kb
Host smart-48eb6c9d-68b4-41d3-b78c-28d34d2e8fc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567645721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.1567645721
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3300073105
Short name T286
Test name
Test status
Simulation time 219539318 ps
CPU time 3.12 seconds
Started Jan 21 07:32:03 PM PST 24
Finished Jan 21 07:32:09 PM PST 24
Peak memory 238404 kb
Host smart-7cba2842-fe75-4ffd-b4e4-cf3996f0b9e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300073105 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3300073105
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1101607495
Short name T255
Test name
Test status
Simulation time 110352153 ps
CPU time 1.59 seconds
Started Jan 21 07:32:02 PM PST 24
Finished Jan 21 07:32:05 PM PST 24
Peak memory 230140 kb
Host smart-0da3792a-054d-4563-b591-e8349748aced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101607495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1101607495
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.203074263
Short name T182
Test name
Test status
Simulation time 38614895 ps
CPU time 1.34 seconds
Started Jan 21 07:32:01 PM PST 24
Finished Jan 21 07:32:04 PM PST 24
Peak memory 229916 kb
Host smart-3ef985a5-c5b3-454d-adde-504143e664d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203074263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.203074263
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1083833594
Short name T391
Test name
Test status
Simulation time 37636126 ps
CPU time 1.34 seconds
Started Jan 21 07:32:02 PM PST 24
Finished Jan 21 07:32:05 PM PST 24
Peak memory 229876 kb
Host smart-b8e43294-6a41-4df1-a741-61c9b15e1c6b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083833594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.1083833594
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3435740737
Short name T435
Test name
Test status
Simulation time 131448176 ps
CPU time 1.35 seconds
Started Jan 21 07:31:48 PM PST 24
Finished Jan 21 07:31:54 PM PST 24
Peak memory 230032 kb
Host smart-23b1ee91-6d5c-4140-8462-ff90125cb8d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435740737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3435740737
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3658852211
Short name T248
Test name
Test status
Simulation time 173224262 ps
CPU time 2.77 seconds
Started Jan 21 07:32:00 PM PST 24
Finished Jan 21 07:32:05 PM PST 24
Peak memory 230168 kb
Host smart-ee8686b5-46a8-4c4a-adae-8c1485130412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658852211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.3658852211
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.2632694549
Short name T1306
Test name
Test status
Simulation time 341932917 ps
CPU time 3.77 seconds
Started Jan 21 07:31:53 PM PST 24
Finished Jan 21 07:32:00 PM PST 24
Peak memory 242332 kb
Host smart-a0a68eab-999c-49c0-b982-abb969f4b5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632694549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.2632694549
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.280108398
Short name T288
Test name
Test status
Simulation time 2438785305 ps
CPU time 19.4 seconds
Started Jan 21 07:31:58 PM PST 24
Finished Jan 21 07:32:21 PM PST 24
Peak memory 241112 kb
Host smart-1130931a-4371-46bf-a090-f90e56f13213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280108398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int
g_err.280108398
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.4122600581
Short name T259
Test name
Test status
Simulation time 1155836865 ps
CPU time 3.45 seconds
Started Jan 21 07:32:05 PM PST 24
Finished Jan 21 07:32:10 PM PST 24
Peak memory 230172 kb
Host smart-f3a1fa8e-1615-4cde-a0c2-da82cd5f6026
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122600581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.4122600581
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1043433390
Short name T414
Test name
Test status
Simulation time 675156023 ps
CPU time 9.4 seconds
Started Jan 21 07:32:05 PM PST 24
Finished Jan 21 07:32:16 PM PST 24
Peak memory 230104 kb
Host smart-62f183d2-b373-4fe0-b814-2a3a1983b29e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043433390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.1043433390
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2398176766
Short name T117
Test name
Test status
Simulation time 236258949 ps
CPU time 2.03 seconds
Started Jan 21 07:32:01 PM PST 24
Finished Jan 21 07:32:05 PM PST 24
Peak memory 230152 kb
Host smart-9a3d2f0c-326b-4610-874c-68306d9a962e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398176766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.2398176766
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1913616327
Short name T289
Test name
Test status
Simulation time 98323816 ps
CPU time 2.55 seconds
Started Jan 21 07:32:10 PM PST 24
Finished Jan 21 07:32:15 PM PST 24
Peak memory 238392 kb
Host smart-27297e58-dda4-42c2-99ec-16bb869f7e9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913616327 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1913616327
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1427895916
Short name T437
Test name
Test status
Simulation time 43580239 ps
CPU time 1.65 seconds
Started Jan 21 07:32:00 PM PST 24
Finished Jan 21 07:32:04 PM PST 24
Peak memory 230092 kb
Host smart-12b87fe0-097a-4b47-b396-fab5f8cc70ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427895916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1427895916
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.118525640
Short name T389
Test name
Test status
Simulation time 43161243 ps
CPU time 1.5 seconds
Started Jan 21 07:32:03 PM PST 24
Finished Jan 21 07:32:07 PM PST 24
Peak memory 230116 kb
Host smart-6d3159a7-e68c-49c2-89a1-f159af3004af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118525640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.118525640
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.823793116
Short name T417
Test name
Test status
Simulation time 137107893 ps
CPU time 1.5 seconds
Started Jan 21 07:32:04 PM PST 24
Finished Jan 21 07:32:08 PM PST 24
Peak memory 229960 kb
Host smart-201357a4-698c-4109-b9c0-865277bcb1a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823793116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl
_mem_partial_access.823793116
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.4004050099
Short name T287
Test name
Test status
Simulation time 516098608 ps
CPU time 1.58 seconds
Started Jan 21 07:32:01 PM PST 24
Finished Jan 21 07:32:04 PM PST 24
Peak memory 230024 kb
Host smart-15c58d64-44a2-4d03-9471-9ff5e54e4eaa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004050099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.4004050099
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2097782669
Short name T1330
Test name
Test status
Simulation time 201775744 ps
CPU time 1.96 seconds
Started Jan 21 07:32:10 PM PST 24
Finished Jan 21 07:32:14 PM PST 24
Peak memory 230124 kb
Host smart-57add123-8d69-4fe9-ad50-c421fa135298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097782669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2097782669
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1999485163
Short name T429
Test name
Test status
Simulation time 62005957 ps
CPU time 3.94 seconds
Started Jan 21 07:31:59 PM PST 24
Finished Jan 21 07:32:06 PM PST 24
Peak memory 238412 kb
Host smart-c16cb528-3284-483a-b40a-05b17627f183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999485163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1999485163
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2523826231
Short name T441
Test name
Test status
Simulation time 18375104161 ps
CPU time 21.2 seconds
Started Jan 21 07:31:59 PM PST 24
Finished Jan 21 07:32:23 PM PST 24
Peak memory 238396 kb
Host smart-d7a22178-46b8-4a55-9bc1-513ac4d47f85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523826231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.2523826231
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4251678036
Short name T406
Test name
Test status
Simulation time 207879250 ps
CPU time 4.63 seconds
Started Jan 21 07:32:48 PM PST 24
Finished Jan 21 07:33:02 PM PST 24
Peak memory 238336 kb
Host smart-934e3aa4-bea7-4bb4-a2d9-a706e9bc28a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251678036 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.4251678036
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.144612296
Short name T439
Test name
Test status
Simulation time 63677506 ps
CPU time 1.66 seconds
Started Jan 21 07:32:31 PM PST 24
Finished Jan 21 07:32:40 PM PST 24
Peak memory 230140 kb
Host smart-b004f257-f8e4-44c9-b64c-aa2ba73562c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144612296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.144612296
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2856819548
Short name T386
Test name
Test status
Simulation time 95643598 ps
CPU time 1.37 seconds
Started Jan 21 07:32:30 PM PST 24
Finished Jan 21 07:32:40 PM PST 24
Peak memory 229892 kb
Host smart-3330bbce-aa08-4991-9a8d-2799b160a00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856819548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2856819548
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3325734458
Short name T427
Test name
Test status
Simulation time 41558990 ps
CPU time 1.83 seconds
Started Jan 21 07:32:37 PM PST 24
Finished Jan 21 07:32:46 PM PST 24
Peak memory 230160 kb
Host smart-e40418b0-68b3-44ee-bec7-60526287d26d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325734458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.3325734458
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3393488379
Short name T1303
Test name
Test status
Simulation time 113351449 ps
CPU time 3.66 seconds
Started Jan 21 07:32:43 PM PST 24
Finished Jan 21 07:32:57 PM PST 24
Peak memory 238396 kb
Host smart-ab3cbc1d-1604-4fd2-b9f5-8c8e4caf18a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393488379 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3393488379
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3845740329
Short name T292
Test name
Test status
Simulation time 40258178 ps
CPU time 1.56 seconds
Started Jan 21 07:32:35 PM PST 24
Finished Jan 21 07:32:45 PM PST 24
Peak memory 230160 kb
Host smart-8e1349ca-a88f-497d-8313-5c88d66616c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845740329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3845740329
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.580047399
Short name T1310
Test name
Test status
Simulation time 79618252 ps
CPU time 1.53 seconds
Started Jan 21 07:32:43 PM PST 24
Finished Jan 21 07:32:55 PM PST 24
Peak memory 230192 kb
Host smart-28d0b3c5-63a2-44db-bc75-85242173ea6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580047399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.580047399
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3971340773
Short name T1308
Test name
Test status
Simulation time 81115794 ps
CPU time 1.75 seconds
Started Jan 21 07:32:36 PM PST 24
Finished Jan 21 07:32:45 PM PST 24
Peak memory 230176 kb
Host smart-7b3a7a57-d82c-43fe-b0af-87bf3645d57f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971340773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3971340773
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.89166238
Short name T423
Test name
Test status
Simulation time 334131246 ps
CPU time 3.91 seconds
Started Jan 21 07:32:48 PM PST 24
Finished Jan 21 07:33:01 PM PST 24
Peak memory 238360 kb
Host smart-270db136-7c48-41f1-92f8-66cc6dc53d16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89166238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.89166238
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4266614960
Short name T115
Test name
Test status
Simulation time 9921354646 ps
CPU time 13.46 seconds
Started Jan 21 07:32:49 PM PST 24
Finished Jan 21 07:33:11 PM PST 24
Peak memory 230148 kb
Host smart-ef6985c5-8014-419c-ad22-ce96a7a9d46f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266614960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.4266614960
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1510970646
Short name T242
Test name
Test status
Simulation time 1623358786 ps
CPU time 4.71 seconds
Started Jan 21 07:32:36 PM PST 24
Finished Jan 21 07:32:48 PM PST 24
Peak memory 246068 kb
Host smart-cf8fdfec-37fa-4b90-826e-4fa251ae7f7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510970646 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1510970646
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2332628769
Short name T1302
Test name
Test status
Simulation time 617921232 ps
CPU time 1.72 seconds
Started Jan 21 07:32:42 PM PST 24
Finished Jan 21 07:32:55 PM PST 24
Peak memory 230196 kb
Host smart-bbc444cb-7498-4d32-8857-44e039ccade8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332628769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2332628769
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.1740820455
Short name T260
Test name
Test status
Simulation time 76629054 ps
CPU time 1.43 seconds
Started Jan 21 07:32:38 PM PST 24
Finished Jan 21 07:32:46 PM PST 24
Peak memory 230148 kb
Host smart-bac1dd2f-c095-4a8f-a668-a696e56eee9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740820455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.1740820455
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2555600903
Short name T394
Test name
Test status
Simulation time 143703782 ps
CPU time 2.45 seconds
Started Jan 21 07:32:37 PM PST 24
Finished Jan 21 07:32:46 PM PST 24
Peak memory 230136 kb
Host smart-e98b5296-9ec4-4d33-baef-e608c8999f9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555600903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.2555600903
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.866396178
Short name T1328
Test name
Test status
Simulation time 184251396 ps
CPU time 2.97 seconds
Started Jan 21 07:32:38 PM PST 24
Finished Jan 21 07:32:47 PM PST 24
Peak memory 238408 kb
Host smart-92b613db-2d44-4eaa-9ea2-968ea9de12aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866396178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.866396178
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1309700567
Short name T252
Test name
Test status
Simulation time 4624615499 ps
CPU time 19.98 seconds
Started Jan 21 07:32:34 PM PST 24
Finished Jan 21 07:33:02 PM PST 24
Peak memory 238508 kb
Host smart-4baaeb1f-72dd-408c-8051-c687b28e993c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309700567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.1309700567
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3683324973
Short name T185
Test name
Test status
Simulation time 185052329 ps
CPU time 3.06 seconds
Started Jan 21 07:32:48 PM PST 24
Finished Jan 21 07:33:00 PM PST 24
Peak memory 238408 kb
Host smart-c8d56022-9aa5-4ee6-8853-cd00f870e8a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683324973 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3683324973
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1036400854
Short name T114
Test name
Test status
Simulation time 86366293 ps
CPU time 1.63 seconds
Started Jan 21 07:32:36 PM PST 24
Finished Jan 21 07:32:45 PM PST 24
Peak memory 230168 kb
Host smart-12b38163-a06d-4897-8beb-e4a3de51f102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036400854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1036400854
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.4264727559
Short name T401
Test name
Test status
Simulation time 550243704 ps
CPU time 2.03 seconds
Started Jan 21 07:32:38 PM PST 24
Finished Jan 21 07:32:46 PM PST 24
Peak memory 229964 kb
Host smart-c3d07eaf-022f-4ceb-88cd-a141c8c1d066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264727559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.4264727559
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2109596506
Short name T1301
Test name
Test status
Simulation time 46170541 ps
CPU time 1.69 seconds
Started Jan 21 07:32:38 PM PST 24
Finished Jan 21 07:32:46 PM PST 24
Peak memory 230156 kb
Host smart-ced6bc4b-fb1a-4a46-9d25-ac26da57ae30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109596506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.2109596506
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2630048034
Short name T192
Test name
Test status
Simulation time 233515258 ps
CPU time 5.32 seconds
Started Jan 21 07:32:36 PM PST 24
Finished Jan 21 07:32:49 PM PST 24
Peak memory 238352 kb
Host smart-5b952c22-ccda-474b-8088-48f895f8623b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630048034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2630048034
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1099319972
Short name T426
Test name
Test status
Simulation time 226818133 ps
CPU time 4.66 seconds
Started Jan 21 07:32:47 PM PST 24
Finished Jan 21 07:33:01 PM PST 24
Peak memory 238420 kb
Host smart-f0cc106a-7496-4780-8966-4321df99a4d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099319972 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.1099319972
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3968173145
Short name T265
Test name
Test status
Simulation time 166874125 ps
CPU time 1.74 seconds
Started Jan 21 07:32:48 PM PST 24
Finished Jan 21 07:32:59 PM PST 24
Peak memory 230136 kb
Host smart-df8d8088-2ebf-4f6e-87fa-881ce1c831e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968173145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3968173145
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2316051740
Short name T291
Test name
Test status
Simulation time 518610361 ps
CPU time 1.77 seconds
Started Jan 21 07:32:37 PM PST 24
Finished Jan 21 07:32:46 PM PST 24
Peak memory 229920 kb
Host smart-15f4dcc1-83bd-4769-af70-02b55596149a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316051740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2316051740
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1133729092
Short name T425
Test name
Test status
Simulation time 616945000 ps
CPU time 2.31 seconds
Started Jan 21 07:32:42 PM PST 24
Finished Jan 21 07:32:56 PM PST 24
Peak memory 230168 kb
Host smart-6b20fa19-9c7e-4181-892f-f0cfd2c049b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133729092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1133729092
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3190513652
Short name T421
Test name
Test status
Simulation time 195510444 ps
CPU time 3.23 seconds
Started Jan 21 07:32:42 PM PST 24
Finished Jan 21 07:32:57 PM PST 24
Peak memory 238388 kb
Host smart-3905c13c-5e98-4e15-9f96-dcb7d67e26a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190513652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3190513652
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1541658801
Short name T385
Test name
Test status
Simulation time 292596232 ps
CPU time 2.73 seconds
Started Jan 21 07:32:47 PM PST 24
Finished Jan 21 07:32:59 PM PST 24
Peak memory 238660 kb
Host smart-f05dbe2d-bc8c-4aad-afcb-0041ee1ce215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541658801 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1541658801
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3235732610
Short name T264
Test name
Test status
Simulation time 38172424 ps
CPU time 1.5 seconds
Started Jan 21 07:32:48 PM PST 24
Finished Jan 21 07:32:59 PM PST 24
Peak memory 230144 kb
Host smart-b004eb5d-a5da-4fed-bdc0-4177b6adef55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235732610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3235732610
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3672037422
Short name T434
Test name
Test status
Simulation time 79578758 ps
CPU time 1.42 seconds
Started Jan 21 07:32:44 PM PST 24
Finished Jan 21 07:32:56 PM PST 24
Peak memory 230164 kb
Host smart-50ede7c6-0c2b-4473-b4b9-2afed112acdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672037422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3672037422
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3486101934
Short name T188
Test name
Test status
Simulation time 123202820 ps
CPU time 2.76 seconds
Started Jan 21 07:32:44 PM PST 24
Finished Jan 21 07:32:57 PM PST 24
Peak memory 238448 kb
Host smart-a04ad5e4-2594-4bee-aa84-cdb84bb1552c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486101934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.3486101934
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.6105137
Short name T254
Test name
Test status
Simulation time 43622834 ps
CPU time 1.49 seconds
Started Jan 21 07:32:46 PM PST 24
Finished Jan 21 07:32:57 PM PST 24
Peak memory 230396 kb
Host smart-3208a8d3-3772-48da-8289-d7a948beeff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6105137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.6105137
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.3186470925
Short name T398
Test name
Test status
Simulation time 72982231 ps
CPU time 1.46 seconds
Started Jan 21 07:32:47 PM PST 24
Finished Jan 21 07:32:57 PM PST 24
Peak memory 230144 kb
Host smart-c5060d9c-419b-4d93-94ca-66d20b29dfdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186470925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3186470925
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1697538387
Short name T1324
Test name
Test status
Simulation time 849397131 ps
CPU time 2.34 seconds
Started Jan 21 07:32:44 PM PST 24
Finished Jan 21 07:32:57 PM PST 24
Peak memory 230048 kb
Host smart-2ce0159d-ee74-45ee-ba17-6f034811d6da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697538387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.1697538387
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.4112797647
Short name T190
Test name
Test status
Simulation time 84551580 ps
CPU time 3.25 seconds
Started Jan 21 07:32:44 PM PST 24
Finished Jan 21 07:32:58 PM PST 24
Peak memory 238356 kb
Host smart-92553cae-8955-4f76-ac3e-340136feec57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112797647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.4112797647
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1803977156
Short name T1332
Test name
Test status
Simulation time 1281867336 ps
CPU time 9.56 seconds
Started Jan 21 07:32:45 PM PST 24
Finished Jan 21 07:33:04 PM PST 24
Peak memory 230152 kb
Host smart-3843e42a-5f15-4d2b-ab52-7f7aac8903d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803977156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.1803977156
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.3817058150
Short name T285
Test name
Test status
Simulation time 134463534 ps
CPU time 2.28 seconds
Started Jan 21 07:32:47 PM PST 24
Finished Jan 21 07:32:58 PM PST 24
Peak memory 238400 kb
Host smart-bd539e80-c52c-4673-8464-e0cd62166860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817058150 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.3817058150
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1249946391
Short name T249
Test name
Test status
Simulation time 94393058 ps
CPU time 1.57 seconds
Started Jan 21 07:32:55 PM PST 24
Finished Jan 21 07:33:05 PM PST 24
Peak memory 230160 kb
Host smart-6db587a2-f028-4c42-b8cc-30fcc880e375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249946391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1249946391
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.573496911
Short name T395
Test name
Test status
Simulation time 74808785 ps
CPU time 1.46 seconds
Started Jan 21 07:32:55 PM PST 24
Finished Jan 21 07:33:05 PM PST 24
Peak memory 230168 kb
Host smart-0645b0e9-aac6-4cf7-9f40-20a21663feab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573496911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.573496911
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.2631585976
Short name T279
Test name
Test status
Simulation time 66835647 ps
CPU time 2.11 seconds
Started Jan 21 07:32:55 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 230160 kb
Host smart-e733bee0-2241-44d9-95c7-5820eb21a245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631585976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.2631585976
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.378955064
Short name T415
Test name
Test status
Simulation time 218981782 ps
CPU time 5.91 seconds
Started Jan 21 07:32:45 PM PST 24
Finished Jan 21 07:33:00 PM PST 24
Peak memory 238436 kb
Host smart-04e9cd07-d8cf-49aa-9c3c-79c2e3ebc9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378955064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.378955064
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2574305131
Short name T246
Test name
Test status
Simulation time 18318318912 ps
CPU time 41.94 seconds
Started Jan 21 08:54:01 PM PST 24
Finished Jan 21 08:54:55 PM PST 24
Peak memory 230268 kb
Host smart-22445101-3d3e-4e84-8bb3-b8a6fc3a0c50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574305131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2574305131
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.997191273
Short name T281
Test name
Test status
Simulation time 258850764 ps
CPU time 2.15 seconds
Started Jan 21 07:32:53 PM PST 24
Finished Jan 21 07:33:02 PM PST 24
Peak memory 238432 kb
Host smart-6de33cee-a97d-4904-8cba-3c3ec5283312
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997191273 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.997191273
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.876604812
Short name T256
Test name
Test status
Simulation time 146219486 ps
CPU time 1.57 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:30 PM PST 24
Peak memory 230180 kb
Host smart-1c7500a5-ea2d-417c-8ee1-11ef0e9f6bd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876604812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.876604812
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3806202565
Short name T416
Test name
Test status
Simulation time 36442894 ps
CPU time 1.33 seconds
Started Jan 21 08:36:35 PM PST 24
Finished Jan 21 08:36:38 PM PST 24
Peak memory 229968 kb
Host smart-4dbfdcec-dc7a-40ed-8e51-c335cef98805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806202565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3806202565
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1126531995
Short name T280
Test name
Test status
Simulation time 248476572 ps
CPU time 3 seconds
Started Jan 21 07:32:55 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 230144 kb
Host smart-221375b8-eef3-4650-9386-8f1c966c880b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126531995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1126531995
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.812216925
Short name T400
Test name
Test status
Simulation time 195159404 ps
CPU time 3.88 seconds
Started Jan 21 08:10:23 PM PST 24
Finished Jan 21 08:10:29 PM PST 24
Peak memory 238412 kb
Host smart-3d645f50-bfca-4adb-bf12-05bc74e543a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812216925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.812216925
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2408519134
Short name T241
Test name
Test status
Simulation time 9512830137 ps
CPU time 10.69 seconds
Started Jan 21 08:12:53 PM PST 24
Finished Jan 21 08:13:06 PM PST 24
Peak memory 230212 kb
Host smart-127ec097-0aa5-45ef-83b4-3e21eda2f8ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408519134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.2408519134
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2201915318
Short name T420
Test name
Test status
Simulation time 144159663 ps
CPU time 2.85 seconds
Started Jan 21 07:32:53 PM PST 24
Finished Jan 21 07:33:02 PM PST 24
Peak memory 238404 kb
Host smart-bf7a6daf-cfab-4fdf-ac3e-27addd7ec86b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201915318 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2201915318
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3433528295
Short name T411
Test name
Test status
Simulation time 124904413 ps
CPU time 1.47 seconds
Started Jan 21 07:32:57 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 229840 kb
Host smart-fe09f2a4-f377-4394-9546-37ce869ac4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433528295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3433528295
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2001638366
Short name T443
Test name
Test status
Simulation time 114761982 ps
CPU time 1.4 seconds
Started Jan 21 07:32:56 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 229936 kb
Host smart-6bda9dc9-f8cf-4ed9-af63-18e604534372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001638366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2001638366
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.2872332501
Short name T397
Test name
Test status
Simulation time 174212271 ps
CPU time 2.51 seconds
Started Jan 21 07:32:51 PM PST 24
Finished Jan 21 07:33:00 PM PST 24
Peak memory 230060 kb
Host smart-d5c21972-1b7a-418b-b9d4-446a068edfd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872332501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.2872332501
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2342331788
Short name T1307
Test name
Test status
Simulation time 1173709177 ps
CPU time 3.99 seconds
Started Jan 21 07:32:54 PM PST 24
Finished Jan 21 07:33:07 PM PST 24
Peak memory 246588 kb
Host smart-e924183b-19a2-4f71-b93a-05917733afd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342331788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2342331788
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2463481183
Short name T325
Test name
Test status
Simulation time 1733332159 ps
CPU time 10.77 seconds
Started Jan 21 07:32:57 PM PST 24
Finished Jan 21 07:33:15 PM PST 24
Peak memory 230196 kb
Host smart-27bfaaea-7534-45b4-93d6-337d43d92ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463481183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2463481183
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3690764988
Short name T266
Test name
Test status
Simulation time 162519276 ps
CPU time 2.6 seconds
Started Jan 21 07:32:10 PM PST 24
Finished Jan 21 07:32:15 PM PST 24
Peak memory 230152 kb
Host smart-8468936d-f241-4d34-80c0-2254d6269117
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690764988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.3690764988
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3277135822
Short name T409
Test name
Test status
Simulation time 125026689 ps
CPU time 6.14 seconds
Started Jan 21 07:32:07 PM PST 24
Finished Jan 21 07:32:16 PM PST 24
Peak memory 230144 kb
Host smart-03ae5d53-bcad-43da-a911-1dc64b762144
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277135822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.3277135822
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1719374411
Short name T271
Test name
Test status
Simulation time 107164386 ps
CPU time 2.34 seconds
Started Jan 21 07:32:07 PM PST 24
Finished Jan 21 07:32:14 PM PST 24
Peak memory 230160 kb
Host smart-c01d5766-4fc5-4f2d-90c9-0264a2dedaac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719374411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1719374411
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3751055444
Short name T184
Test name
Test status
Simulation time 955024861 ps
CPU time 2.16 seconds
Started Jan 21 07:32:12 PM PST 24
Finished Jan 21 07:32:17 PM PST 24
Peak memory 238476 kb
Host smart-ba551848-852f-4de1-a743-132af0dfea21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751055444 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3751055444
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3939819795
Short name T273
Test name
Test status
Simulation time 129077656 ps
CPU time 1.51 seconds
Started Jan 21 07:32:06 PM PST 24
Finished Jan 21 07:32:11 PM PST 24
Peak memory 230188 kb
Host smart-698fc41b-69a6-4e8e-91ec-f919fb8819e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939819795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3939819795
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.1806630018
Short name T1300
Test name
Test status
Simulation time 130872647 ps
CPU time 1.53 seconds
Started Jan 21 07:32:05 PM PST 24
Finished Jan 21 07:32:09 PM PST 24
Peak memory 229920 kb
Host smart-7449fb74-16a0-4b3b-8a50-982f68732267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806630018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1806630018
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.4004459871
Short name T428
Test name
Test status
Simulation time 512089775 ps
CPU time 1.47 seconds
Started Jan 21 07:32:08 PM PST 24
Finished Jan 21 07:32:13 PM PST 24
Peak memory 229924 kb
Host smart-51919bf8-6e80-4a0c-96d3-cba9def43c2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004459871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.4004459871
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3191740477
Short name T283
Test name
Test status
Simulation time 66263906 ps
CPU time 1.43 seconds
Started Jan 21 07:32:11 PM PST 24
Finished Jan 21 07:32:14 PM PST 24
Peak memory 230036 kb
Host smart-fa09fe6e-fa62-46ed-936f-41cfa7a730a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191740477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3191740477
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.4211743784
Short name T1315
Test name
Test status
Simulation time 156658751 ps
CPU time 2.05 seconds
Started Jan 21 07:32:14 PM PST 24
Finished Jan 21 07:32:23 PM PST 24
Peak memory 230112 kb
Host smart-eb1d3fdf-4d9f-45a5-b745-9daf78201c07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211743784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.4211743784
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2556733008
Short name T1299
Test name
Test status
Simulation time 196054316 ps
CPU time 3.2 seconds
Started Jan 21 07:32:10 PM PST 24
Finished Jan 21 07:32:16 PM PST 24
Peak memory 238448 kb
Host smart-4ffc65ef-195c-4994-a898-3f6a384137c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556733008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2556733008
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1636070279
Short name T390
Test name
Test status
Simulation time 148421181 ps
CPU time 1.63 seconds
Started Jan 21 08:27:06 PM PST 24
Finished Jan 21 08:27:09 PM PST 24
Peak memory 230192 kb
Host smart-0c3fbfc2-2368-4e56-94eb-46922d4bbfe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636070279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1636070279
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2325475178
Short name T1298
Test name
Test status
Simulation time 138565543 ps
CPU time 1.73 seconds
Started Jan 21 07:32:53 PM PST 24
Finished Jan 21 07:33:01 PM PST 24
Peak memory 230176 kb
Host smart-8381ccee-84eb-4793-a4df-90208e77523b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325475178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2325475178
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1056670927
Short name T1317
Test name
Test status
Simulation time 44239818 ps
CPU time 1.4 seconds
Started Jan 21 07:32:57 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 229984 kb
Host smart-e0a66616-6d4d-4275-93e2-c8d47e3107e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056670927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1056670927
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3725554936
Short name T433
Test name
Test status
Simulation time 577755662 ps
CPU time 1.56 seconds
Started Jan 21 07:32:52 PM PST 24
Finished Jan 21 07:33:00 PM PST 24
Peak memory 230192 kb
Host smart-366b6068-fc30-4f23-a14a-07d025b6f5a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725554936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3725554936
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3549593401
Short name T402
Test name
Test status
Simulation time 137349801 ps
CPU time 1.33 seconds
Started Jan 21 07:32:57 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 230224 kb
Host smart-e0197b71-a2ee-4bbc-91ce-4a7aeae3395e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549593401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3549593401
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.457996607
Short name T1326
Test name
Test status
Simulation time 73709619 ps
CPU time 1.48 seconds
Started Jan 21 07:32:57 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 229864 kb
Host smart-0a0df66f-74f8-4d89-ade4-e708c5da3e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457996607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.457996607
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.69273334
Short name T262
Test name
Test status
Simulation time 533981868 ps
CPU time 2.12 seconds
Started Jan 21 07:32:56 PM PST 24
Finished Jan 21 07:33:06 PM PST 24
Peak memory 229928 kb
Host smart-349ad57f-3f47-4be7-a111-897d3fef31ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69273334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.69273334
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2491039371
Short name T422
Test name
Test status
Simulation time 582431369 ps
CPU time 1.94 seconds
Started Jan 21 07:33:05 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 229968 kb
Host smart-2a7dccf6-5f49-4f9a-9d37-304ae9fdee76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491039371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2491039371
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2024606395
Short name T181
Test name
Test status
Simulation time 92787185 ps
CPU time 1.41 seconds
Started Jan 21 07:32:58 PM PST 24
Finished Jan 21 07:33:07 PM PST 24
Peak memory 230192 kb
Host smart-23d8ac5e-dd37-48ab-a6e8-41b5ee4401f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024606395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2024606395
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3106993863
Short name T261
Test name
Test status
Simulation time 81196953 ps
CPU time 1.48 seconds
Started Jan 21 07:33:07 PM PST 24
Finished Jan 21 07:33:10 PM PST 24
Peak memory 229812 kb
Host smart-50f7f2cd-462d-448f-9bac-beaa00302828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106993863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.3106993863
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.4093876014
Short name T263
Test name
Test status
Simulation time 75437024 ps
CPU time 2.84 seconds
Started Jan 21 07:32:13 PM PST 24
Finished Jan 21 07:32:20 PM PST 24
Peak memory 230240 kb
Host smart-1afc3656-47aa-4ca2-b906-1395af9cb46a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093876014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.4093876014
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4009721541
Short name T210
Test name
Test status
Simulation time 470873437 ps
CPU time 6.29 seconds
Started Jan 21 07:32:15 PM PST 24
Finished Jan 21 07:32:28 PM PST 24
Peak memory 230132 kb
Host smart-61e6f21d-2b81-4e30-8927-fcf6e94bf95d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009721541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.4009721541
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.504057413
Short name T116
Test name
Test status
Simulation time 85520979 ps
CPU time 1.73 seconds
Started Jan 21 07:32:14 PM PST 24
Finished Jan 21 07:32:22 PM PST 24
Peak memory 230132 kb
Host smart-04aae844-f2a8-45e5-8055-d692973bf977
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504057413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_re
set.504057413
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3189835471
Short name T1323
Test name
Test status
Simulation time 371362097 ps
CPU time 3.93 seconds
Started Jan 21 07:32:17 PM PST 24
Finished Jan 21 07:32:29 PM PST 24
Peak memory 238380 kb
Host smart-a2e60c03-5356-4892-a18b-995860698494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189835471 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3189835471
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.1808697737
Short name T274
Test name
Test status
Simulation time 556917541 ps
CPU time 2.06 seconds
Started Jan 21 07:32:16 PM PST 24
Finished Jan 21 07:32:27 PM PST 24
Peak memory 230136 kb
Host smart-db2c4b42-650c-484b-bf29-34881c83aaf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808697737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.1808697737
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.609145731
Short name T1318
Test name
Test status
Simulation time 45887742 ps
CPU time 1.4 seconds
Started Jan 21 07:32:13 PM PST 24
Finished Jan 21 07:32:19 PM PST 24
Peak memory 230152 kb
Host smart-abe12095-53d5-4ff6-9bd6-8ad48a2ebad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609145731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.609145731
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.4146430944
Short name T436
Test name
Test status
Simulation time 546570570 ps
CPU time 2.16 seconds
Started Jan 21 07:32:13 PM PST 24
Finished Jan 21 07:32:19 PM PST 24
Peak memory 229984 kb
Host smart-feb7427f-a850-48f9-b5d7-3c0a661f884a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146430944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.4146430944
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.2156064844
Short name T440
Test name
Test status
Simulation time 89815887 ps
CPU time 1.32 seconds
Started Jan 21 07:32:14 PM PST 24
Finished Jan 21 07:32:22 PM PST 24
Peak memory 230024 kb
Host smart-5287e92a-0a33-4af3-80d4-c23d711e26a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156064844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.2156064844
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2496648731
Short name T405
Test name
Test status
Simulation time 299336568 ps
CPU time 2.8 seconds
Started Jan 21 07:32:11 PM PST 24
Finished Jan 21 07:32:15 PM PST 24
Peak memory 230136 kb
Host smart-5d02ee53-5ac7-4c70-b060-bc7dbeb2af5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496648731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.2496648731
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.4267753509
Short name T251
Test name
Test status
Simulation time 140606858 ps
CPU time 5.48 seconds
Started Jan 21 07:32:15 PM PST 24
Finished Jan 21 07:32:27 PM PST 24
Peak memory 238364 kb
Host smart-e8c688eb-9213-49b0-a2fb-a15c77111d15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267753509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.4267753509
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.771167846
Short name T326
Test name
Test status
Simulation time 2586244318 ps
CPU time 17.57 seconds
Started Jan 21 07:32:13 PM PST 24
Finished Jan 21 07:32:37 PM PST 24
Peak memory 230200 kb
Host smart-fcdfd0ca-8605-49c6-95ff-839a64fa04fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771167846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_int
g_err.771167846
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.930973148
Short name T113
Test name
Test status
Simulation time 40283668 ps
CPU time 1.53 seconds
Started Jan 21 07:33:06 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 230156 kb
Host smart-98a5d529-2a42-4748-93dc-d681d37fac94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930973148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.930973148
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.348818232
Short name T413
Test name
Test status
Simulation time 41423719 ps
CPU time 1.45 seconds
Started Jan 21 07:33:06 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 230156 kb
Host smart-2806e800-7f84-4b0b-ad7d-faedfa5385d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348818232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.348818232
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2703665204
Short name T392
Test name
Test status
Simulation time 106374735 ps
CPU time 1.52 seconds
Started Jan 21 07:33:05 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 229964 kb
Host smart-96a153f7-c745-4780-9547-0b1204678288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703665204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2703665204
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1575179383
Short name T1304
Test name
Test status
Simulation time 38659481 ps
CPU time 1.37 seconds
Started Jan 21 07:33:05 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 230164 kb
Host smart-cf15802c-5dbc-4025-b0f9-d213f5191408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575179383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1575179383
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.674763332
Short name T396
Test name
Test status
Simulation time 547261635 ps
CPU time 1.57 seconds
Started Jan 21 07:33:07 PM PST 24
Finished Jan 21 07:33:10 PM PST 24
Peak memory 229856 kb
Host smart-cd5b4dcb-c418-4366-be35-4c941f8d17ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674763332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.674763332
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2727198903
Short name T193
Test name
Test status
Simulation time 71781778 ps
CPU time 1.38 seconds
Started Jan 21 07:33:00 PM PST 24
Finished Jan 21 07:33:07 PM PST 24
Peak memory 230156 kb
Host smart-774d5e5d-36e3-49c2-a27e-81159c44187b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727198903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2727198903
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.647015349
Short name T297
Test name
Test status
Simulation time 37934197 ps
CPU time 1.5 seconds
Started Jan 21 07:33:07 PM PST 24
Finished Jan 21 07:33:10 PM PST 24
Peak memory 230032 kb
Host smart-7f1b92e3-a110-47b8-97b2-ae0ec2cab288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647015349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.647015349
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1932212391
Short name T431
Test name
Test status
Simulation time 140672799 ps
CPU time 1.31 seconds
Started Jan 21 07:33:07 PM PST 24
Finished Jan 21 07:33:10 PM PST 24
Peak memory 229892 kb
Host smart-13b03b42-4d04-4eb9-8ac4-452ce15c8db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932212391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1932212391
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.1097998798
Short name T419
Test name
Test status
Simulation time 44311286 ps
CPU time 1.45 seconds
Started Jan 21 07:33:06 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 230160 kb
Host smart-1003c2f6-bf10-4075-b0eb-605a520d9656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097998798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1097998798
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.575805334
Short name T268
Test name
Test status
Simulation time 619765173 ps
CPU time 6.63 seconds
Started Jan 21 07:32:23 PM PST 24
Finished Jan 21 07:32:36 PM PST 24
Peak memory 230048 kb
Host smart-00de0739-5597-4d5e-bd71-57d469bdfef5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575805334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.575805334
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3711377619
Short name T1320
Test name
Test status
Simulation time 236394099 ps
CPU time 1.79 seconds
Started Jan 21 07:32:21 PM PST 24
Finished Jan 21 07:32:28 PM PST 24
Peak memory 230088 kb
Host smart-dbbd2127-5679-4b54-9029-4f5c98abb96f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711377619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3711377619
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3188525779
Short name T257
Test name
Test status
Simulation time 42929785 ps
CPU time 1.52 seconds
Started Jan 21 07:32:32 PM PST 24
Finished Jan 21 07:32:41 PM PST 24
Peak memory 229940 kb
Host smart-e8874dd2-9427-4138-9044-56e3a37d6ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188525779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3188525779
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.651198032
Short name T276
Test name
Test status
Simulation time 73848678 ps
CPU time 1.33 seconds
Started Jan 21 07:32:15 PM PST 24
Finished Jan 21 07:32:23 PM PST 24
Peak memory 229968 kb
Host smart-38c6478a-a847-446c-8723-00cbaac8acc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651198032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.651198032
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3239265737
Short name T1321
Test name
Test status
Simulation time 130889696 ps
CPU time 1.36 seconds
Started Jan 21 07:32:17 PM PST 24
Finished Jan 21 07:32:27 PM PST 24
Peak memory 229920 kb
Host smart-117d5efe-aedb-4124-a55e-0e433d1df51d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239265737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.3239265737
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.165957096
Short name T387
Test name
Test status
Simulation time 131078681 ps
CPU time 1.43 seconds
Started Jan 21 07:32:18 PM PST 24
Finished Jan 21 07:32:27 PM PST 24
Peak memory 229984 kb
Host smart-8c69e93e-253e-4e67-a818-6b21b3d98352
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165957096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.
165957096
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.4074622483
Short name T109
Test name
Test status
Simulation time 176575468 ps
CPU time 2.1 seconds
Started Jan 21 07:32:20 PM PST 24
Finished Jan 21 07:32:28 PM PST 24
Peak memory 230156 kb
Host smart-32aea7c7-38a1-4d5a-9770-6fbf6089898d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074622483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.4074622483
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3179874973
Short name T1319
Test name
Test status
Simulation time 203730906 ps
CPU time 3.18 seconds
Started Jan 21 07:32:17 PM PST 24
Finished Jan 21 07:32:29 PM PST 24
Peak memory 238612 kb
Host smart-ca514756-af5c-419d-92da-66f419844aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179874973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3179874973
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.156161164
Short name T324
Test name
Test status
Simulation time 1137298680 ps
CPU time 17.93 seconds
Started Jan 21 07:32:17 PM PST 24
Finished Jan 21 07:32:43 PM PST 24
Peak memory 230156 kb
Host smart-8fba0366-6653-46a3-a782-f18f62e65137
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156161164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int
g_err.156161164
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.4023654158
Short name T1305
Test name
Test status
Simulation time 68192334 ps
CPU time 1.5 seconds
Started Jan 21 07:33:08 PM PST 24
Finished Jan 21 07:33:12 PM PST 24
Peak memory 229908 kb
Host smart-ef1db647-4ed7-4354-b339-bd1179110cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023654158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.4023654158
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.1563094934
Short name T404
Test name
Test status
Simulation time 111077698 ps
CPU time 1.5 seconds
Started Jan 21 07:33:05 PM PST 24
Finished Jan 21 07:33:08 PM PST 24
Peak memory 229964 kb
Host smart-284eacef-19aa-4fa6-a469-c3501747eb6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563094934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.1563094934
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.4031350201
Short name T418
Test name
Test status
Simulation time 39624021 ps
CPU time 1.43 seconds
Started Jan 21 07:33:07 PM PST 24
Finished Jan 21 07:33:10 PM PST 24
Peak memory 229932 kb
Host smart-27946f70-5bde-4422-a61e-f3e7633d9bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031350201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.4031350201
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1190108215
Short name T388
Test name
Test status
Simulation time 543995745 ps
CPU time 1.85 seconds
Started Jan 21 07:33:10 PM PST 24
Finished Jan 21 07:33:15 PM PST 24
Peak memory 229944 kb
Host smart-243808e0-e97b-4c69-8ed8-57922aa039ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190108215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1190108215
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3176157701
Short name T412
Test name
Test status
Simulation time 82263897 ps
CPU time 1.59 seconds
Started Jan 21 07:33:06 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 230172 kb
Host smart-1c14b398-b941-4760-a312-c6532aa7088c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176157701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3176157701
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.2927634923
Short name T1327
Test name
Test status
Simulation time 54601822 ps
CPU time 1.5 seconds
Started Jan 21 07:33:09 PM PST 24
Finished Jan 21 07:33:14 PM PST 24
Peak memory 230132 kb
Host smart-78303572-a58b-4123-82cb-3aab07d94f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927634923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2927634923
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.342016333
Short name T284
Test name
Test status
Simulation time 70654072 ps
CPU time 1.41 seconds
Started Jan 21 07:33:08 PM PST 24
Finished Jan 21 07:33:13 PM PST 24
Peak memory 229900 kb
Host smart-87c2b65e-0a3c-4699-aad6-25eb8c5c5dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342016333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.342016333
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1229479795
Short name T275
Test name
Test status
Simulation time 53723390 ps
CPU time 1.35 seconds
Started Jan 21 07:33:06 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 230208 kb
Host smart-708de1ed-e807-4b39-83a6-30f2576d238a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229479795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1229479795
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.277262249
Short name T424
Test name
Test status
Simulation time 132608306 ps
CPU time 1.43 seconds
Started Jan 21 07:33:10 PM PST 24
Finished Jan 21 07:33:14 PM PST 24
Peak memory 229964 kb
Host smart-3d6e535e-4f02-4e94-977a-a3197c8f03dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277262249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.277262249
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2571891198
Short name T393
Test name
Test status
Simulation time 154191677 ps
CPU time 1.47 seconds
Started Jan 21 07:33:08 PM PST 24
Finished Jan 21 07:33:13 PM PST 24
Peak memory 230172 kb
Host smart-eb5a20ec-4bfd-4541-8b21-f1e0ff6e5fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571891198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.2571891198
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.1155142803
Short name T1312
Test name
Test status
Simulation time 953680631 ps
CPU time 2.34 seconds
Started Jan 21 07:32:22 PM PST 24
Finished Jan 21 07:32:30 PM PST 24
Peak memory 238492 kb
Host smart-bd13d0d6-3351-4be9-a452-00f4a3e4e24c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155142803 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.1155142803
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.925374882
Short name T253
Test name
Test status
Simulation time 80929743 ps
CPU time 1.66 seconds
Started Jan 21 07:32:23 PM PST 24
Finished Jan 21 07:32:31 PM PST 24
Peak memory 230116 kb
Host smart-cc3af169-62bf-40b2-8399-49baebe71e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925374882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.925374882
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.41540984
Short name T399
Test name
Test status
Simulation time 88269114 ps
CPU time 1.44 seconds
Started Jan 21 07:32:24 PM PST 24
Finished Jan 21 07:32:31 PM PST 24
Peak memory 229908 kb
Host smart-cafcac98-1931-4dcb-82e3-7fcc42e58e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.41540984
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3449255901
Short name T442
Test name
Test status
Simulation time 171515067 ps
CPU time 1.85 seconds
Started Jan 21 07:32:24 PM PST 24
Finished Jan 21 07:32:32 PM PST 24
Peak memory 230112 kb
Host smart-3c7a24b5-f249-4998-b689-fb96a858a6e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449255901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.3449255901
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1261072905
Short name T408
Test name
Test status
Simulation time 58300503 ps
CPU time 3.37 seconds
Started Jan 21 07:32:23 PM PST 24
Finished Jan 21 07:32:33 PM PST 24
Peak memory 238288 kb
Host smart-92f3ce7a-80ef-4842-b0cb-479181386f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261072905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1261072905
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2254144440
Short name T245
Test name
Test status
Simulation time 4773537849 ps
CPU time 23.5 seconds
Started Jan 21 07:32:20 PM PST 24
Finished Jan 21 07:32:50 PM PST 24
Peak memory 238416 kb
Host smart-1b7da543-505a-468e-b77b-a24cfed77fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254144440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.2254144440
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.1224407871
Short name T407
Test name
Test status
Simulation time 140146577 ps
CPU time 2.3 seconds
Started Jan 21 07:32:30 PM PST 24
Finished Jan 21 07:32:41 PM PST 24
Peak memory 238376 kb
Host smart-9fd53c12-3fda-459a-84fb-6b910fd55d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224407871 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.1224407871
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.610984055
Short name T1309
Test name
Test status
Simulation time 47942416 ps
CPU time 1.48 seconds
Started Jan 21 07:32:25 PM PST 24
Finished Jan 21 07:32:33 PM PST 24
Peak memory 230152 kb
Host smart-8fe80114-eb44-4222-bd92-cd2df16386e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610984055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.610984055
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2742225292
Short name T247
Test name
Test status
Simulation time 921895784 ps
CPU time 2.33 seconds
Started Jan 21 07:32:26 PM PST 24
Finished Jan 21 07:32:36 PM PST 24
Peak memory 230164 kb
Host smart-fb0537ba-28dd-404b-9e1a-ac191e6598b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742225292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.2742225292
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3906973562
Short name T191
Test name
Test status
Simulation time 250994603 ps
CPU time 4.54 seconds
Started Jan 21 07:32:32 PM PST 24
Finished Jan 21 07:32:44 PM PST 24
Peak memory 238368 kb
Host smart-794e300d-1854-4ab1-b60b-6cfda3a5b388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906973562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3906973562
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.3059622652
Short name T189
Test name
Test status
Simulation time 132401714 ps
CPU time 2.91 seconds
Started Jan 21 07:32:28 PM PST 24
Finished Jan 21 07:32:40 PM PST 24
Peak memory 238488 kb
Host smart-858c2a45-050c-4745-b927-b6983e52b7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059622652 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.3059622652
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.841143181
Short name T272
Test name
Test status
Simulation time 560199601 ps
CPU time 1.77 seconds
Started Jan 21 07:32:23 PM PST 24
Finished Jan 21 07:32:31 PM PST 24
Peak memory 230152 kb
Host smart-53b50e0a-19fd-4c54-931d-755ce83e1fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841143181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.841143181
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3524623767
Short name T1329
Test name
Test status
Simulation time 105658178 ps
CPU time 1.41 seconds
Started Jan 21 07:32:22 PM PST 24
Finished Jan 21 07:32:29 PM PST 24
Peak memory 229972 kb
Host smart-ee539136-65d9-4619-82bd-ee8f43681fa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524623767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3524623767
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.214699689
Short name T1331
Test name
Test status
Simulation time 112926876 ps
CPU time 1.93 seconds
Started Jan 21 07:32:30 PM PST 24
Finished Jan 21 07:32:40 PM PST 24
Peak memory 230112 kb
Host smart-39ea00c0-6373-48b7-983f-42f8882d736e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214699689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct
rl_same_csr_outstanding.214699689
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3150152443
Short name T1325
Test name
Test status
Simulation time 1029617348 ps
CPU time 5.11 seconds
Started Jan 21 07:32:27 PM PST 24
Finished Jan 21 07:32:42 PM PST 24
Peak memory 238444 kb
Host smart-50cc317b-6c98-4209-b731-2984b41e07d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150152443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3150152443
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.101192102
Short name T432
Test name
Test status
Simulation time 2110092463 ps
CPU time 10.05 seconds
Started Jan 21 07:32:26 PM PST 24
Finished Jan 21 07:32:44 PM PST 24
Peak memory 238360 kb
Host smart-ca1ae4e2-77ed-40a4-aed8-987efa205c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101192102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.101192102
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.844102837
Short name T403
Test name
Test status
Simulation time 106274403 ps
CPU time 2.93 seconds
Started Jan 21 07:32:28 PM PST 24
Finished Jan 21 07:32:40 PM PST 24
Peak memory 238428 kb
Host smart-5d2f54dd-aa50-4c22-882f-c75b76e018a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844102837 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.844102837
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.883096072
Short name T1313
Test name
Test status
Simulation time 71433214 ps
CPU time 1.57 seconds
Started Jan 21 07:32:22 PM PST 24
Finished Jan 21 07:32:30 PM PST 24
Peak memory 230200 kb
Host smart-2d481a62-ea46-4460-9b5a-85011ecdbcb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883096072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.883096072
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.1703338002
Short name T1316
Test name
Test status
Simulation time 101652496 ps
CPU time 1.39 seconds
Started Jan 21 07:32:22 PM PST 24
Finished Jan 21 07:32:30 PM PST 24
Peak memory 230140 kb
Host smart-044c1286-bd1f-4090-bf7d-f5a5bdbaae8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703338002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1703338002
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2125564657
Short name T1314
Test name
Test status
Simulation time 219296229 ps
CPU time 3.2 seconds
Started Jan 21 07:32:21 PM PST 24
Finished Jan 21 07:32:30 PM PST 24
Peak memory 230096 kb
Host smart-0f92b7bc-a1ec-49a9-bb6e-5466c55e78d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125564657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.2125564657
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2423121655
Short name T1322
Test name
Test status
Simulation time 2131158101 ps
CPU time 7.23 seconds
Started Jan 21 07:32:32 PM PST 24
Finished Jan 21 07:32:47 PM PST 24
Peak memory 238412 kb
Host smart-2689fb96-e414-47ea-9216-4a1cf6916cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423121655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2423121655
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.995649920
Short name T282
Test name
Test status
Simulation time 661547910 ps
CPU time 9.92 seconds
Started Jan 21 07:32:30 PM PST 24
Finished Jan 21 07:32:48 PM PST 24
Peak memory 230128 kb
Host smart-8df0c9bf-06d0-4e19-8944-06a98fd5aa5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995649920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_int
g_err.995649920
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2646774267
Short name T186
Test name
Test status
Simulation time 138092479 ps
CPU time 2.44 seconds
Started Jan 21 07:32:32 PM PST 24
Finished Jan 21 07:32:42 PM PST 24
Peak memory 238448 kb
Host smart-6480205f-8e0c-42ae-8cc4-7a782286b5ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646774267 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.2646774267
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1911204173
Short name T270
Test name
Test status
Simulation time 61732283 ps
CPU time 1.6 seconds
Started Jan 21 07:32:32 PM PST 24
Finished Jan 21 07:32:41 PM PST 24
Peak memory 230108 kb
Host smart-b5022a46-cdbf-402e-a122-121cec0c2bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911204173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1911204173
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1359748012
Short name T410
Test name
Test status
Simulation time 139155482 ps
CPU time 1.6 seconds
Started Jan 21 07:32:34 PM PST 24
Finished Jan 21 07:32:44 PM PST 24
Peak memory 230144 kb
Host smart-1eef0253-1f91-4644-bb66-f6f3eed8e7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359748012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1359748012
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.4038850455
Short name T183
Test name
Test status
Simulation time 974206407 ps
CPU time 2.85 seconds
Started Jan 21 07:32:30 PM PST 24
Finished Jan 21 07:32:41 PM PST 24
Peak memory 230128 kb
Host smart-8abbde88-7969-4a97-b47c-f11e402c8f62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038850455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.4038850455
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1635100347
Short name T243
Test name
Test status
Simulation time 1118605244 ps
CPU time 3.54 seconds
Started Jan 21 07:32:28 PM PST 24
Finished Jan 21 07:32:40 PM PST 24
Peak memory 238472 kb
Host smart-3a7a1a55-5c95-4ee5-a3f4-71dc106aa4f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635100347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1635100347
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.342913915
Short name T217
Test name
Test status
Simulation time 1182690076 ps
CPU time 16.44 seconds
Started Jan 21 07:32:30 PM PST 24
Finished Jan 21 07:32:55 PM PST 24
Peak memory 230324 kb
Host smart-addfa7dc-7447-49a0-8807-769d0ba183f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342913915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_int
g_err.342913915
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.3986338265
Short name T847
Test name
Test status
Simulation time 116828529 ps
CPU time 1.63 seconds
Started Jan 21 10:11:37 PM PST 24
Finished Jan 21 10:11:40 PM PST 24
Peak memory 230496 kb
Host smart-0216b153-58b5-497d-a615-fe5fe1e52e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986338265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3986338265
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3987294339
Short name T987
Test name
Test status
Simulation time 868571129 ps
CPU time 16.45 seconds
Started Jan 21 10:11:28 PM PST 24
Finished Jan 21 10:11:48 PM PST 24
Peak memory 238780 kb
Host smart-8b1c383c-520a-49c2-baf0-b40ca5102945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987294339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3987294339
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.2633592583
Short name T70
Test name
Test status
Simulation time 1024224507 ps
CPU time 5.79 seconds
Started Jan 21 10:11:32 PM PST 24
Finished Jan 21 10:11:41 PM PST 24
Peak memory 244140 kb
Host smart-610ec66d-3a32-46d4-bee9-87198b0d1af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633592583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2633592583
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.2014940125
Short name T1107
Test name
Test status
Simulation time 328473334 ps
CPU time 8.28 seconds
Started Jan 21 10:11:28 PM PST 24
Finished Jan 21 10:11:40 PM PST 24
Peak memory 243348 kb
Host smart-d2427015-f2c7-4d10-85ab-606a348718a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014940125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2014940125
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.2499818711
Short name T1132
Test name
Test status
Simulation time 791769074 ps
CPU time 5.34 seconds
Started Jan 21 10:11:30 PM PST 24
Finished Jan 21 10:11:40 PM PST 24
Peak memory 238732 kb
Host smart-4b72e84a-df5e-48d4-87a3-8621f2160f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499818711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2499818711
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3821375784
Short name T1250
Test name
Test status
Simulation time 3023701775 ps
CPU time 12.47 seconds
Started Jan 21 10:11:21 PM PST 24
Finished Jan 21 10:11:37 PM PST 24
Peak memory 230680 kb
Host smart-c6d76972-e0a6-4bf3-9fd2-cfaac23074bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821375784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3821375784
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.3631540262
Short name T118
Test name
Test status
Simulation time 7444696957 ps
CPU time 15.41 seconds
Started Jan 21 10:11:31 PM PST 24
Finished Jan 21 10:11:50 PM PST 24
Peak memory 239576 kb
Host smart-d1ddbe5d-4f41-4115-8875-b85cfa1a9cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631540262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.3631540262
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.2609936064
Short name T582
Test name
Test status
Simulation time 1236143332 ps
CPU time 9.18 seconds
Started Jan 21 10:11:27 PM PST 24
Finished Jan 21 10:11:41 PM PST 24
Peak memory 238860 kb
Host smart-51dc85a2-8be7-4caa-bdb6-c635e3ae32ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609936064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2609936064
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.1336900560
Short name T597
Test name
Test status
Simulation time 1007308820 ps
CPU time 6.95 seconds
Started Jan 21 11:22:07 PM PST 24
Finished Jan 21 11:22:23 PM PST 24
Peak memory 243236 kb
Host smart-73070c10-c6ff-4169-913a-d645c7057c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336900560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1336900560
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2255816700
Short name T564
Test name
Test status
Simulation time 361215762 ps
CPU time 9.01 seconds
Started Jan 21 10:11:26 PM PST 24
Finished Jan 21 10:11:41 PM PST 24
Peak memory 238672 kb
Host smart-7e103323-7161-4192-8f96-14baa0f5dbf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255816700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2255816700
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.112275796
Short name T180
Test name
Test status
Simulation time 815573529 ps
CPU time 18.63 seconds
Started Jan 21 10:11:20 PM PST 24
Finished Jan 21 10:11:43 PM PST 24
Peak memory 240824 kb
Host smart-e76e48c5-b27a-410b-9613-0b7b68808449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112275796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.112275796
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.2869859963
Short name T1129
Test name
Test status
Simulation time 1057343651 ps
CPU time 7.81 seconds
Started Jan 21 10:28:55 PM PST 24
Finished Jan 21 10:29:07 PM PST 24
Peak memory 244020 kb
Host smart-9cc45ca9-0e3f-4a0e-a7d4-475fc26f06a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869859963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2869859963
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.1744601662
Short name T456
Test name
Test status
Simulation time 457826740 ps
CPU time 4.19 seconds
Started Jan 21 10:11:23 PM PST 24
Finished Jan 21 10:11:33 PM PST 24
Peak memory 238808 kb
Host smart-03cc5368-72f1-4954-b903-ac79d9091562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744601662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1744601662
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.1383673470
Short name T1270
Test name
Test status
Simulation time 5670059172 ps
CPU time 44.15 seconds
Started Jan 21 10:11:37 PM PST 24
Finished Jan 21 10:12:23 PM PST 24
Peak memory 247092 kb
Host smart-c89c9311-717d-4517-b736-d2ba74eac606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383673470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
1383673470
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.4211078781
Short name T17
Test name
Test status
Simulation time 1736035855503 ps
CPU time 5450.95 seconds
Started Jan 21 10:44:17 PM PST 24
Finished Jan 22 12:15:10 AM PST 24
Peak memory 658352 kb
Host smart-390d6e7f-fc73-44e3-89b3-7ac50131abbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211078781 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.4211078781
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.1209942633
Short name T1021
Test name
Test status
Simulation time 2751432387 ps
CPU time 19.12 seconds
Started Jan 21 10:11:27 PM PST 24
Finished Jan 21 10:11:51 PM PST 24
Peak memory 245380 kb
Host smart-d0114941-76f2-493b-b103-b0061a7d6d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209942633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1209942633
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.1018153500
Short name T482
Test name
Test status
Simulation time 119619109 ps
CPU time 1.84 seconds
Started Jan 21 10:11:21 PM PST 24
Finished Jan 21 10:11:26 PM PST 24
Peak memory 228756 kb
Host smart-ab0e14f7-084a-4129-8d1b-66c206b4ecb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018153500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1018153500
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.1191988386
Short name T800
Test name
Test status
Simulation time 636238130 ps
CPU time 1.71 seconds
Started Jan 21 10:11:40 PM PST 24
Finished Jan 21 10:11:44 PM PST 24
Peak memory 239644 kb
Host smart-a2c5753a-75bc-4aa8-9c41-8526ae2f7414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191988386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1191988386
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1493022954
Short name T1198
Test name
Test status
Simulation time 2885280432 ps
CPU time 21.49 seconds
Started Jan 21 10:33:16 PM PST 24
Finished Jan 21 10:33:42 PM PST 24
Peak memory 238812 kb
Host smart-3837e294-5f0b-4a8f-a0ee-1bf791a9aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493022954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1493022954
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1430651222
Short name T1220
Test name
Test status
Simulation time 471005797 ps
CPU time 10.96 seconds
Started Jan 21 10:11:32 PM PST 24
Finished Jan 21 10:11:46 PM PST 24
Peak memory 238720 kb
Host smart-48c845b1-e147-493c-90c8-f521ed05768c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430651222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1430651222
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.1452691255
Short name T599
Test name
Test status
Simulation time 1120064427 ps
CPU time 11.26 seconds
Started Jan 21 10:11:35 PM PST 24
Finished Jan 21 10:11:48 PM PST 24
Peak memory 245924 kb
Host smart-f34e23fc-e4e9-46fa-adda-3e41366199c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452691255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1452691255
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.1352952626
Short name T1056
Test name
Test status
Simulation time 9686037460 ps
CPU time 17.17 seconds
Started Jan 21 10:11:33 PM PST 24
Finished Jan 21 10:11:53 PM PST 24
Peak memory 245904 kb
Host smart-ba72215c-295b-4ead-a6db-7f4868b8651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352952626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1352952626
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.98593392
Short name T1145
Test name
Test status
Simulation time 692142567 ps
CPU time 12.19 seconds
Started Jan 21 10:11:33 PM PST 24
Finished Jan 21 10:11:48 PM PST 24
Peak memory 238780 kb
Host smart-c3159981-6866-45e2-873f-e306b23db394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98593392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.98593392
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.1359874319
Short name T1157
Test name
Test status
Simulation time 495504408 ps
CPU time 8.06 seconds
Started Jan 21 10:11:35 PM PST 24
Finished Jan 21 10:11:44 PM PST 24
Peak memory 241236 kb
Host smart-1ce31b37-0c17-4907-a539-debeeb3680d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359874319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.1359874319
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1179820429
Short name T1015
Test name
Test status
Simulation time 395647179 ps
CPU time 6.03 seconds
Started Jan 21 10:22:22 PM PST 24
Finished Jan 21 10:22:39 PM PST 24
Peak memory 242852 kb
Host smart-589df8b4-658e-4b8a-b6ab-ae8718febffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179820429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1179820429
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.362148944
Short name T1226
Test name
Test status
Simulation time 1791194707 ps
CPU time 13.25 seconds
Started Jan 21 10:11:39 PM PST 24
Finished Jan 21 10:11:54 PM PST 24
Peak memory 238768 kb
Host smart-b35d200f-74cc-483d-8f36-339ae0803973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362148944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.362148944
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.3111776012
Short name T20
Test name
Test status
Simulation time 34025395805 ps
CPU time 162.22 seconds
Started Jan 21 10:11:38 PM PST 24
Finished Jan 21 10:14:23 PM PST 24
Peak memory 272540 kb
Host smart-bfdf5195-6fb5-4960-b2b7-ee58c8f0f7af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111776012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3111776012
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.3704095934
Short name T1137
Test name
Test status
Simulation time 224674390 ps
CPU time 4.1 seconds
Started Jan 21 10:11:35 PM PST 24
Finished Jan 21 10:11:42 PM PST 24
Peak memory 238732 kb
Host smart-7e73d0ce-a8de-45b8-8623-1745ad0d5647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704095934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3704095934
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3444522770
Short name T376
Test name
Test status
Simulation time 5169812809 ps
CPU time 114.46 seconds
Started Jan 21 10:11:45 PM PST 24
Finished Jan 21 10:13:41 PM PST 24
Peak memory 240808 kb
Host smart-e5d99ff8-a34d-4d02-ae02-07137f5ae1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444522770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3444522770
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.2758746013
Short name T964
Test name
Test status
Simulation time 1886788149 ps
CPU time 18.34 seconds
Started Jan 21 10:11:37 PM PST 24
Finished Jan 21 10:11:57 PM PST 24
Peak memory 238672 kb
Host smart-06084e09-4e80-4f63-bbf2-ef91c7ffb2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758746013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2758746013
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.514195894
Short name T647
Test name
Test status
Simulation time 741336672 ps
CPU time 2.79 seconds
Started Jan 21 10:12:44 PM PST 24
Finished Jan 21 10:12:49 PM PST 24
Peak memory 239668 kb
Host smart-01764edf-21e4-420f-99fd-39217f645a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514195894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.514195894
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.833514472
Short name T504
Test name
Test status
Simulation time 140195463 ps
CPU time 6.42 seconds
Started Jan 21 10:12:42 PM PST 24
Finished Jan 21 10:12:51 PM PST 24
Peak memory 238752 kb
Host smart-1026e662-086a-493d-9f7c-4b368f54d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833514472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.833514472
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.3600041388
Short name T619
Test name
Test status
Simulation time 426950349 ps
CPU time 7.63 seconds
Started Jan 21 10:12:43 PM PST 24
Finished Jan 21 10:12:53 PM PST 24
Peak memory 238772 kb
Host smart-7601873b-fd68-4c5a-9b84-48bbecee812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600041388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.3600041388
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3695217699
Short name T1203
Test name
Test status
Simulation time 183952780 ps
CPU time 4.68 seconds
Started Jan 21 10:12:40 PM PST 24
Finished Jan 21 10:12:47 PM PST 24
Peak memory 238768 kb
Host smart-635a6133-7ac4-49f1-b125-57fa4db62bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695217699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3695217699
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.3672940920
Short name T917
Test name
Test status
Simulation time 1143375306 ps
CPU time 15.97 seconds
Started Jan 21 10:12:54 PM PST 24
Finished Jan 21 10:13:12 PM PST 24
Peak memory 243528 kb
Host smart-fefb5f11-a558-4503-8c22-7074c77e3c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672940920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.3672940920
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.3840916269
Short name T379
Test name
Test status
Simulation time 1141986712 ps
CPU time 17.66 seconds
Started Jan 21 10:12:42 PM PST 24
Finished Jan 21 10:13:03 PM PST 24
Peak memory 244048 kb
Host smart-6334116c-ca64-410d-8316-450f30e48b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840916269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3840916269
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.280338197
Short name T781
Test name
Test status
Simulation time 175593330 ps
CPU time 6.32 seconds
Started Jan 21 10:12:42 PM PST 24
Finished Jan 21 10:12:51 PM PST 24
Peak memory 242828 kb
Host smart-089c228c-87a1-463f-a6fc-ee5658bb0f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280338197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.280338197
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.1489067610
Short name T500
Test name
Test status
Simulation time 6486742731 ps
CPU time 18.57 seconds
Started Jan 21 10:12:40 PM PST 24
Finished Jan 21 10:13:01 PM PST 24
Peak memory 244424 kb
Host smart-6da51161-eeb9-432f-a45d-2b4f3b1b3bbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489067610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1489067610
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.3858003643
Short name T1079
Test name
Test status
Simulation time 119027475 ps
CPU time 3.88 seconds
Started Jan 21 10:12:42 PM PST 24
Finished Jan 21 10:12:49 PM PST 24
Peak memory 243252 kb
Host smart-f76126f0-19c9-4953-99ee-b92b78f25659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3858003643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3858003643
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.1307745907
Short name T533
Test name
Test status
Simulation time 200855899 ps
CPU time 4.21 seconds
Started Jan 21 10:12:40 PM PST 24
Finished Jan 21 10:12:47 PM PST 24
Peak memory 242996 kb
Host smart-e1583c1b-088b-435e-baa2-a0a2e6941a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307745907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.1307745907
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2481791207
Short name T870
Test name
Test status
Simulation time 579401130669 ps
CPU time 937.55 seconds
Started Jan 21 10:12:54 PM PST 24
Finished Jan 21 10:28:33 PM PST 24
Peak memory 337084 kb
Host smart-738c0b1a-2235-41f8-87d5-507c39a72ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481791207 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.2481791207
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.3588705622
Short name T94
Test name
Test status
Simulation time 1346432506 ps
CPU time 16.24 seconds
Started Jan 21 10:12:42 PM PST 24
Finished Jan 21 10:13:01 PM PST 24
Peak memory 245216 kb
Host smart-139b3c57-0eaf-4c5b-a156-28f7db659115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588705622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3588705622
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2638907302
Short name T764
Test name
Test status
Simulation time 324020394 ps
CPU time 7.47 seconds
Started Jan 21 10:18:29 PM PST 24
Finished Jan 21 10:18:42 PM PST 24
Peak memory 243760 kb
Host smart-0ff2f72e-6adc-4c50-8b47-b59701b2ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638907302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2638907302
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.2328293530
Short name T901
Test name
Test status
Simulation time 165038000 ps
CPU time 3.15 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 10:18:31 PM PST 24
Peak memory 241296 kb
Host smart-aa662da5-6511-40f0-a951-678d764234a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328293530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2328293530
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.753508299
Short name T1200
Test name
Test status
Simulation time 455494926 ps
CPU time 3.97 seconds
Started Jan 21 10:49:53 PM PST 24
Finished Jan 21 10:49:59 PM PST 24
Peak memory 238596 kb
Host smart-1e3a7f9b-532c-4118-b650-124348524733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753508299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.753508299
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.807440087
Short name T665
Test name
Test status
Simulation time 300809573 ps
CPU time 4.4 seconds
Started Jan 21 10:18:21 PM PST 24
Finished Jan 21 10:18:33 PM PST 24
Peak memory 238828 kb
Host smart-8e3b8e78-bf9b-4511-8e96-bb6386c225bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807440087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.807440087
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1763914218
Short name T531
Test name
Test status
Simulation time 116591284 ps
CPU time 3.29 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 10:18:31 PM PST 24
Peak memory 238724 kb
Host smart-110ee7c7-02f5-484d-b488-00f96877bd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763914218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1763914218
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1321487201
Short name T698
Test name
Test status
Simulation time 826077536 ps
CPU time 6.45 seconds
Started Jan 21 10:18:19 PM PST 24
Finished Jan 21 10:18:33 PM PST 24
Peak memory 243272 kb
Host smart-47984658-65eb-4302-99a3-c9e9e57c6e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321487201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1321487201
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.2047050214
Short name T595
Test name
Test status
Simulation time 251581909 ps
CPU time 4.57 seconds
Started Jan 21 10:18:21 PM PST 24
Finished Jan 21 10:18:33 PM PST 24
Peak memory 240740 kb
Host smart-b1781760-67e3-4a95-8308-d24d8ddff28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047050214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.2047050214
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.3962472106
Short name T222
Test name
Test status
Simulation time 318363718 ps
CPU time 4.81 seconds
Started Jan 21 10:50:00 PM PST 24
Finished Jan 21 10:50:07 PM PST 24
Peak memory 242652 kb
Host smart-c527d71f-ff7a-4e02-bb64-d0c50bcec566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962472106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3962472106
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1336175123
Short name T518
Test name
Test status
Simulation time 202837790 ps
CPU time 4.58 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 10:18:32 PM PST 24
Peak memory 238728 kb
Host smart-891e14f6-8b7a-4ecc-b9b4-51d9864d390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336175123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1336175123
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.2886448080
Short name T1104
Test name
Test status
Simulation time 186028522 ps
CPU time 3.84 seconds
Started Jan 21 10:18:21 PM PST 24
Finished Jan 21 10:18:32 PM PST 24
Peak memory 242916 kb
Host smart-e8733441-4dd7-42b8-8190-9afd63fd604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886448080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.2886448080
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.4091208987
Short name T1024
Test name
Test status
Simulation time 233038590 ps
CPU time 3.63 seconds
Started Jan 21 10:18:21 PM PST 24
Finished Jan 21 10:18:32 PM PST 24
Peak memory 241448 kb
Host smart-7b380eec-5790-43cf-a6ef-66e2bf8795b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091208987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.4091208987
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3034652421
Short name T1106
Test name
Test status
Simulation time 652389039 ps
CPU time 6 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 10:18:34 PM PST 24
Peak memory 243012 kb
Host smart-bf85b253-142d-4351-9f73-a7badb51c4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034652421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3034652421
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.631029207
Short name T37
Test name
Test status
Simulation time 223370630 ps
CPU time 3.65 seconds
Started Jan 21 10:32:17 PM PST 24
Finished Jan 21 10:32:23 PM PST 24
Peak memory 238744 kb
Host smart-290797ab-b71c-407b-98ef-eef75d8fd355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631029207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.631029207
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.193629797
Short name T603
Test name
Test status
Simulation time 531951978 ps
CPU time 3.58 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 10:18:31 PM PST 24
Peak memory 238828 kb
Host smart-91c9da9e-3020-467d-ad57-287181d2d24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193629797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.193629797
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.762078297
Short name T149
Test name
Test status
Simulation time 133112894 ps
CPU time 4.08 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 10:18:31 PM PST 24
Peak memory 238672 kb
Host smart-3edb0294-0dc6-4a40-a3b6-476697a4f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762078297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.762078297
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3419497357
Short name T583
Test name
Test status
Simulation time 278354499 ps
CPU time 7.52 seconds
Started Jan 21 10:18:19 PM PST 24
Finished Jan 21 10:18:34 PM PST 24
Peak memory 243232 kb
Host smart-98c322f7-6ff8-4406-94c5-601a6559ba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419497357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3419497357
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.471906845
Short name T1171
Test name
Test status
Simulation time 138670844 ps
CPU time 3.62 seconds
Started Jan 21 10:18:26 PM PST 24
Finished Jan 21 10:18:37 PM PST 24
Peak memory 242344 kb
Host smart-70cee6c4-6e92-42f6-bcf2-6a38797e69bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471906845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.471906845
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.878953373
Short name T31
Test name
Test status
Simulation time 422281026 ps
CPU time 3.39 seconds
Started Jan 21 10:12:46 PM PST 24
Finished Jan 21 10:12:52 PM PST 24
Peak memory 238656 kb
Host smart-1f9fcf94-4eda-496c-91f9-cdedefe72864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878953373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.878953373
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.3288226542
Short name T842
Test name
Test status
Simulation time 406736052 ps
CPU time 4.45 seconds
Started Jan 21 10:12:54 PM PST 24
Finished Jan 21 10:13:00 PM PST 24
Peak memory 238688 kb
Host smart-8efa9cfc-5cc8-469d-bff2-2e311c4c059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288226542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3288226542
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.525084270
Short name T1086
Test name
Test status
Simulation time 596790023 ps
CPU time 9.14 seconds
Started Jan 21 10:54:56 PM PST 24
Finished Jan 21 10:55:08 PM PST 24
Peak memory 238736 kb
Host smart-7bf7d654-e430-4af8-ae20-f81ce527e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525084270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.525084270
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.365532551
Short name T572
Test name
Test status
Simulation time 5719188749 ps
CPU time 16.16 seconds
Started Jan 21 10:12:49 PM PST 24
Finished Jan 21 10:13:08 PM PST 24
Peak memory 238788 kb
Host smart-f32728e0-3305-4871-aab1-87416c0f2b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365532551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.365532551
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2394122329
Short name T540
Test name
Test status
Simulation time 472927320 ps
CPU time 4.57 seconds
Started Jan 21 10:12:49 PM PST 24
Finished Jan 21 10:12:56 PM PST 24
Peak memory 243392 kb
Host smart-44f7f054-320c-487a-b0d7-09d39ea0e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394122329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2394122329
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.193420963
Short name T687
Test name
Test status
Simulation time 332010633 ps
CPU time 3.67 seconds
Started Jan 21 10:12:46 PM PST 24
Finished Jan 21 10:12:53 PM PST 24
Peak memory 238688 kb
Host smart-7754e876-8f9a-4cd1-8bd6-be1ecacf9bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193420963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.193420963
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.165361749
Short name T508
Test name
Test status
Simulation time 261929497 ps
CPU time 4.49 seconds
Started Jan 21 11:14:45 PM PST 24
Finished Jan 21 11:14:52 PM PST 24
Peak memory 243740 kb
Host smart-903896f8-cbd0-468a-81d9-46604563b454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165361749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.165361749
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.1711660954
Short name T451
Test name
Test status
Simulation time 621240000 ps
CPU time 7.58 seconds
Started Jan 21 10:12:47 PM PST 24
Finished Jan 21 10:12:57 PM PST 24
Peak memory 230580 kb
Host smart-8446fb7b-64a4-419c-a869-12040daa390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711660954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.1711660954
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.4201644027
Short name T1142
Test name
Test status
Simulation time 12618154802 ps
CPU time 52.74 seconds
Started Jan 21 10:12:49 PM PST 24
Finished Jan 21 10:13:44 PM PST 24
Peak memory 242184 kb
Host smart-1777014d-63fb-48a6-a811-52f3b0b3ae52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201644027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.4201644027
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.3042497681
Short name T605
Test name
Test status
Simulation time 317042564906 ps
CPU time 3864.54 seconds
Started Jan 21 10:12:48 PM PST 24
Finished Jan 21 11:17:16 PM PST 24
Peak memory 271644 kb
Host smart-c8cf71e7-c064-48ac-a10c-93f9352e7478
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042497681 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.3042497681
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2979299828
Short name T1294
Test name
Test status
Simulation time 738882775 ps
CPU time 13.84 seconds
Started Jan 21 11:11:45 PM PST 24
Finished Jan 21 11:11:59 PM PST 24
Peak memory 238892 kb
Host smart-f0ed44de-d781-4bfe-889d-cb795259de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979299828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2979299828
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.2905618846
Short name T950
Test name
Test status
Simulation time 2753915303 ps
CPU time 7.41 seconds
Started Jan 21 10:18:35 PM PST 24
Finished Jan 21 10:18:47 PM PST 24
Peak memory 243324 kb
Host smart-ba65a575-b843-4587-b16b-c5d49082f47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905618846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2905618846
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.1059712129
Short name T579
Test name
Test status
Simulation time 227029773 ps
CPU time 4.42 seconds
Started Jan 21 10:18:35 PM PST 24
Finished Jan 21 10:18:44 PM PST 24
Peak memory 238752 kb
Host smart-75f17c95-4d53-4799-8ba0-d75439acc1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059712129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1059712129
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3170937977
Short name T936
Test name
Test status
Simulation time 245471225 ps
CPU time 5.28 seconds
Started Jan 21 10:18:25 PM PST 24
Finished Jan 21 10:18:37 PM PST 24
Peak memory 241460 kb
Host smart-18f79891-db05-448a-817f-c4544b42e8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170937977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3170937977
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3972037095
Short name T664
Test name
Test status
Simulation time 386934637 ps
CPU time 7.9 seconds
Started Jan 21 10:18:29 PM PST 24
Finished Jan 21 10:18:43 PM PST 24
Peak memory 242180 kb
Host smart-e55815c5-47e8-4b19-b7f3-b6a0982777ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972037095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3972037095
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.1476704436
Short name T1217
Test name
Test status
Simulation time 470481795 ps
CPU time 5.03 seconds
Started Jan 21 10:18:25 PM PST 24
Finished Jan 21 10:18:37 PM PST 24
Peak memory 241292 kb
Host smart-7d19c196-33e7-4b7a-9e26-c73f637cfe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476704436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1476704436
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3989392307
Short name T494
Test name
Test status
Simulation time 2071808731 ps
CPU time 4.53 seconds
Started Jan 21 10:18:29 PM PST 24
Finished Jan 21 10:18:39 PM PST 24
Peak memory 238844 kb
Host smart-e9aa5aed-2445-4cec-9d46-9888ee50a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989392307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3989392307
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.2446983887
Short name T663
Test name
Test status
Simulation time 223772291 ps
CPU time 3.97 seconds
Started Jan 21 10:18:36 PM PST 24
Finished Jan 21 10:18:44 PM PST 24
Peak memory 238736 kb
Host smart-3918ad56-07e6-4a92-b8c7-78428b2863c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446983887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2446983887
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2870631445
Short name T1168
Test name
Test status
Simulation time 3185100494 ps
CPU time 5.46 seconds
Started Jan 21 10:18:33 PM PST 24
Finished Jan 21 10:18:44 PM PST 24
Peak memory 243424 kb
Host smart-2c14c782-d593-4068-8f01-a4ff0a57447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870631445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2870631445
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.343179685
Short name T980
Test name
Test status
Simulation time 1745866956 ps
CPU time 4.45 seconds
Started Jan 21 10:18:35 PM PST 24
Finished Jan 21 10:18:44 PM PST 24
Peak memory 238748 kb
Host smart-8640dd63-9f4a-4028-ab17-aa90efd4c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343179685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.343179685
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.4157300880
Short name T315
Test name
Test status
Simulation time 658374605 ps
CPU time 5.2 seconds
Started Jan 21 10:18:33 PM PST 24
Finished Jan 21 10:18:43 PM PST 24
Peak memory 238780 kb
Host smart-d8ef9147-53cb-47d9-a339-7ed0edf7246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157300880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.4157300880
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.2795061214
Short name T502
Test name
Test status
Simulation time 299081776 ps
CPU time 3.06 seconds
Started Jan 21 10:18:35 PM PST 24
Finished Jan 21 10:18:42 PM PST 24
Peak memory 246836 kb
Host smart-d986e49e-0bc9-43bd-9388-0a798e4ff5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795061214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2795061214
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3265515587
Short name T921
Test name
Test status
Simulation time 315335677 ps
CPU time 7.66 seconds
Started Jan 21 10:18:41 PM PST 24
Finished Jan 21 10:18:55 PM PST 24
Peak memory 238760 kb
Host smart-c6c2f38f-61e5-45bb-913d-0121c5239d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265515587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3265515587
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.3994007088
Short name T727
Test name
Test status
Simulation time 2906680033 ps
CPU time 6.83 seconds
Started Jan 21 10:18:45 PM PST 24
Finished Jan 21 10:18:58 PM PST 24
Peak memory 238296 kb
Host smart-0e8fa845-dc33-47a8-bd02-5a9d5d97b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994007088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3994007088
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.1343952018
Short name T883
Test name
Test status
Simulation time 4632019954 ps
CPU time 7.54 seconds
Started Jan 21 10:18:45 PM PST 24
Finished Jan 21 10:18:58 PM PST 24
Peak memory 243552 kb
Host smart-2942ba70-944c-4ef4-b566-523bc54593d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343952018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.1343952018
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2965394373
Short name T487
Test name
Test status
Simulation time 568802586 ps
CPU time 4.91 seconds
Started Jan 21 10:18:42 PM PST 24
Finished Jan 21 10:18:53 PM PST 24
Peak memory 238764 kb
Host smart-679e764c-0630-42f8-abb5-cab399c53bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965394373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2965394373
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.1079070291
Short name T1277
Test name
Test status
Simulation time 158611728 ps
CPU time 3.9 seconds
Started Jan 21 10:18:45 PM PST 24
Finished Jan 21 10:18:55 PM PST 24
Peak memory 238796 kb
Host smart-9f0fd763-d2cc-4c0e-b664-1d33d38ed087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079070291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.1079070291
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2756486724
Short name T563
Test name
Test status
Simulation time 597620056 ps
CPU time 7.48 seconds
Started Jan 21 10:18:44 PM PST 24
Finished Jan 21 10:18:58 PM PST 24
Peak memory 244280 kb
Host smart-a973ef9c-2993-4177-ad0e-87e36087498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756486724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2756486724
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.808553543
Short name T140
Test name
Test status
Simulation time 339741134 ps
CPU time 4.05 seconds
Started Jan 21 10:18:41 PM PST 24
Finished Jan 21 10:18:52 PM PST 24
Peak memory 240684 kb
Host smart-4db27f78-9f1d-4b0d-a14e-075963cf6bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808553543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.808553543
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.3014382584
Short name T689
Test name
Test status
Simulation time 297265400 ps
CPU time 4.86 seconds
Started Jan 21 10:18:40 PM PST 24
Finished Jan 21 10:18:51 PM PST 24
Peak memory 246692 kb
Host smart-6a7c1ca1-cfdb-4a20-893c-894cd6bb965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014382584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3014382584
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.1883737601
Short name T1232
Test name
Test status
Simulation time 907573995 ps
CPU time 2.95 seconds
Started Jan 21 10:13:03 PM PST 24
Finished Jan 21 10:13:08 PM PST 24
Peak memory 239168 kb
Host smart-2c26727f-4868-417a-8570-7bf64dc47fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883737601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1883737601
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.871613702
Short name T627
Test name
Test status
Simulation time 11000597173 ps
CPU time 21.93 seconds
Started Jan 21 10:12:58 PM PST 24
Finished Jan 21 10:13:21 PM PST 24
Peak memory 247052 kb
Host smart-59abc34a-60b1-44b0-843d-7e1619bb12bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871613702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.871613702
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.720092727
Short name T607
Test name
Test status
Simulation time 325694907 ps
CPU time 8.22 seconds
Started Jan 21 10:13:01 PM PST 24
Finished Jan 21 10:13:10 PM PST 24
Peak memory 244332 kb
Host smart-d25498ec-456a-4253-9716-3c6f692f40eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720092727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.720092727
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2145548689
Short name T577
Test name
Test status
Simulation time 5678567440 ps
CPU time 11.28 seconds
Started Jan 21 10:12:57 PM PST 24
Finished Jan 21 10:13:09 PM PST 24
Peak memory 243748 kb
Host smart-306ff639-6a54-4807-86a2-69a85c0df5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145548689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2145548689
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.857321756
Short name T165
Test name
Test status
Simulation time 160477551 ps
CPU time 3.79 seconds
Started Jan 21 10:12:58 PM PST 24
Finished Jan 21 10:13:03 PM PST 24
Peak memory 240780 kb
Host smart-d65042de-781d-4b39-a26b-cdfbe4596ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857321756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.857321756
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.355999927
Short name T1062
Test name
Test status
Simulation time 794192200 ps
CPU time 15.98 seconds
Started Jan 21 10:13:03 PM PST 24
Finished Jan 21 10:13:21 PM PST 24
Peak memory 245716 kb
Host smart-9899f614-5487-40e6-8ee8-74a56999e8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355999927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.355999927
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.2469533288
Short name T939
Test name
Test status
Simulation time 2020836215 ps
CPU time 7.67 seconds
Started Jan 21 10:12:56 PM PST 24
Finished Jan 21 10:13:06 PM PST 24
Peak memory 238736 kb
Host smart-ecdc3e43-d3eb-485a-bc4d-4302a941253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469533288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.2469533288
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2967943579
Short name T629
Test name
Test status
Simulation time 6402835643 ps
CPU time 14.13 seconds
Started Jan 21 10:13:02 PM PST 24
Finished Jan 21 10:13:18 PM PST 24
Peak memory 246548 kb
Host smart-f33daf6d-cbc4-4c0a-8b2e-ee44da1cf575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967943579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2967943579
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.2626090820
Short name T370
Test name
Test status
Simulation time 1783561653 ps
CPU time 14.06 seconds
Started Jan 21 10:12:56 PM PST 24
Finished Jan 21 10:13:12 PM PST 24
Peak memory 238668 kb
Host smart-487db74f-fe65-4d19-b9c5-b34823f915d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626090820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.2626090820
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2804415013
Short name T906
Test name
Test status
Simulation time 146506719 ps
CPU time 5.26 seconds
Started Jan 21 10:12:57 PM PST 24
Finished Jan 21 10:13:04 PM PST 24
Peak memory 238792 kb
Host smart-8c9f4320-3503-4e30-8ad7-91e9edf55b52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804415013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2804415013
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.3156574127
Short name T886
Test name
Test status
Simulation time 806921209 ps
CPU time 8.18 seconds
Started Jan 21 10:12:56 PM PST 24
Finished Jan 21 10:13:05 PM PST 24
Peak memory 238860 kb
Host smart-17586f6f-ff1b-44a0-ad56-30a1440a0b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156574127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3156574127
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.2385448984
Short name T1235
Test name
Test status
Simulation time 79264910175 ps
CPU time 186.55 seconds
Started Jan 21 10:12:57 PM PST 24
Finished Jan 21 10:16:06 PM PST 24
Peak memory 247084 kb
Host smart-879e969b-e789-4bae-86fb-10d8b57de0af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385448984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.2385448984
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.362008226
Short name T1249
Test name
Test status
Simulation time 8715000803276 ps
CPU time 8906.04 seconds
Started Jan 21 10:12:59 PM PST 24
Finished Jan 22 12:41:28 AM PST 24
Peak memory 346820 kb
Host smart-a4da58f9-2f5c-4816-aabf-a5460afc600d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362008226 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.362008226
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.4082127369
Short name T1225
Test name
Test status
Simulation time 318207244 ps
CPU time 3.79 seconds
Started Jan 21 10:13:01 PM PST 24
Finished Jan 21 10:13:06 PM PST 24
Peak memory 238712 kb
Host smart-25cda45e-e803-4b8a-ac93-6541a6913741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082127369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.4082127369
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.2395486981
Short name T447
Test name
Test status
Simulation time 2377154100 ps
CPU time 7.66 seconds
Started Jan 21 10:18:38 PM PST 24
Finished Jan 21 10:18:49 PM PST 24
Peak memory 238688 kb
Host smart-9fcc4146-300a-4ac4-bd9d-8b0e675b53a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395486981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2395486981
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.3946893623
Short name T1032
Test name
Test status
Simulation time 167488318 ps
CPU time 3.58 seconds
Started Jan 21 10:18:41 PM PST 24
Finished Jan 21 10:18:51 PM PST 24
Peak memory 238728 kb
Host smart-11ae7b4a-3251-4c98-a34c-d674b4b98208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946893623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3946893623
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2208370324
Short name T168
Test name
Test status
Simulation time 262676596 ps
CPU time 4.28 seconds
Started Jan 21 10:18:39 PM PST 24
Finished Jan 21 10:18:48 PM PST 24
Peak memory 238732 kb
Host smart-1c0aa679-6d4c-4e34-b734-8b6a5ee8fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208370324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2208370324
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3611007922
Short name T673
Test name
Test status
Simulation time 1368667635 ps
CPU time 6.1 seconds
Started Jan 21 10:18:41 PM PST 24
Finished Jan 21 10:18:54 PM PST 24
Peak memory 242052 kb
Host smart-ef4db7ad-d3b2-4966-8904-c9ac32e7d043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611007922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3611007922
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.1321340324
Short name T1066
Test name
Test status
Simulation time 159919049 ps
CPU time 3.86 seconds
Started Jan 21 10:18:39 PM PST 24
Finished Jan 21 10:18:47 PM PST 24
Peak memory 238696 kb
Host smart-653081fe-9a34-4a63-bcfb-4a6dbe59b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321340324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1321340324
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.3807848801
Short name T882
Test name
Test status
Simulation time 537579992 ps
CPU time 6.2 seconds
Started Jan 21 10:18:40 PM PST 24
Finished Jan 21 10:18:53 PM PST 24
Peak memory 242900 kb
Host smart-c5d94a09-488c-4eae-8531-60cf3235f1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807848801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.3807848801
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.4194255024
Short name T548
Test name
Test status
Simulation time 206351439 ps
CPU time 4.87 seconds
Started Jan 21 10:18:49 PM PST 24
Finished Jan 21 10:18:59 PM PST 24
Peak memory 242592 kb
Host smart-74c09555-5e03-4c15-84be-1fcdfbd956be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194255024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.4194255024
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.3016693248
Short name T39
Test name
Test status
Simulation time 141452404 ps
CPU time 3.79 seconds
Started Jan 21 10:18:55 PM PST 24
Finished Jan 21 10:19:04 PM PST 24
Peak memory 241412 kb
Host smart-dd0c9463-aad6-4613-a325-1313a6f2066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016693248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3016693248
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.804227000
Short name T1180
Test name
Test status
Simulation time 314630042 ps
CPU time 5.13 seconds
Started Jan 21 10:18:51 PM PST 24
Finished Jan 21 10:19:01 PM PST 24
Peak memory 238760 kb
Host smart-6e77f480-34e9-42d4-a6c1-05f524bdd958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804227000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.804227000
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.2800301477
Short name T730
Test name
Test status
Simulation time 2692519150 ps
CPU time 7.02 seconds
Started Jan 21 10:18:55 PM PST 24
Finished Jan 21 10:19:07 PM PST 24
Peak memory 241828 kb
Host smart-3af24c2a-5500-498c-b8e1-9fb39e861b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800301477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2800301477
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1341170998
Short name T995
Test name
Test status
Simulation time 349188831 ps
CPU time 4.41 seconds
Started Jan 21 10:18:55 PM PST 24
Finished Jan 21 10:19:04 PM PST 24
Peak memory 238768 kb
Host smart-7d28cb53-c739-43f3-ab85-1ad89ae90abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341170998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1341170998
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.3771187323
Short name T158
Test name
Test status
Simulation time 559429713 ps
CPU time 4.34 seconds
Started Jan 21 10:18:49 PM PST 24
Finished Jan 21 10:18:59 PM PST 24
Peak memory 242444 kb
Host smart-85de7c53-2b1c-4a5e-aa8b-872d76c25736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771187323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.3771187323
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2463578869
Short name T27
Test name
Test status
Simulation time 312234348 ps
CPU time 3.7 seconds
Started Jan 21 10:18:49 PM PST 24
Finished Jan 21 10:18:59 PM PST 24
Peak memory 246908 kb
Host smart-2dae20a9-629d-4ee5-b660-cdc9d75a526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463578869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2463578869
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2702541288
Short name T1023
Test name
Test status
Simulation time 240735188 ps
CPU time 4.45 seconds
Started Jan 21 10:18:59 PM PST 24
Finished Jan 21 10:19:07 PM PST 24
Peak memory 241840 kb
Host smart-afc162c1-ac11-4d49-bb15-ebfb161aef4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702541288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2702541288
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.3918360942
Short name T1037
Test name
Test status
Simulation time 196910307 ps
CPU time 3.27 seconds
Started Jan 21 10:18:58 PM PST 24
Finished Jan 21 10:19:06 PM PST 24
Peak memory 238672 kb
Host smart-a8574c7a-4d83-4dbc-a554-f2d0d9f4a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918360942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3918360942
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3612669948
Short name T982
Test name
Test status
Simulation time 3648337634 ps
CPU time 11.56 seconds
Started Jan 21 10:18:55 PM PST 24
Finished Jan 21 10:19:11 PM PST 24
Peak memory 245556 kb
Host smart-9ac004c8-c66d-42ee-87f8-01eae60faeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612669948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3612669948
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.832826879
Short name T128
Test name
Test status
Simulation time 2572364491 ps
CPU time 5.46 seconds
Started Jan 21 10:18:57 PM PST 24
Finished Jan 21 10:19:07 PM PST 24
Peak memory 246992 kb
Host smart-c7e90000-02f0-4253-a691-ce733fabac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832826879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.832826879
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.873311401
Short name T1289
Test name
Test status
Simulation time 1658561301 ps
CPU time 6.35 seconds
Started Jan 21 10:18:59 PM PST 24
Finished Jan 21 10:19:09 PM PST 24
Peak memory 238604 kb
Host smart-e2584b5b-6d73-492d-824f-c79a730df575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873311401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.873311401
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.336463475
Short name T1028
Test name
Test status
Simulation time 122925951 ps
CPU time 1.74 seconds
Started Jan 21 10:13:09 PM PST 24
Finished Jan 21 10:13:13 PM PST 24
Peak memory 239648 kb
Host smart-9efd288d-99be-46ad-8c87-f8e1c662a02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336463475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.336463475
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.1760782400
Short name T892
Test name
Test status
Simulation time 1470906570 ps
CPU time 15.53 seconds
Started Jan 21 10:13:16 PM PST 24
Finished Jan 21 10:13:34 PM PST 24
Peak memory 244700 kb
Host smart-cd9b1fff-1fd6-4241-be8a-222d020d6a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760782400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1760782400
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.669122464
Short name T122
Test name
Test status
Simulation time 6137039795 ps
CPU time 18.34 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:36 PM PST 24
Peak memory 238936 kb
Host smart-b0d4a410-8225-4be3-9589-ef6b97c150f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669122464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.669122464
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3227301455
Short name T819
Test name
Test status
Simulation time 1238974339 ps
CPU time 20.68 seconds
Started Jan 21 10:13:11 PM PST 24
Finished Jan 21 10:13:33 PM PST 24
Peak memory 238776 kb
Host smart-c13b1e5d-fe6b-4540-a468-c9c5e418b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227301455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3227301455
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.2661668551
Short name T1040
Test name
Test status
Simulation time 266370610 ps
CPU time 4.16 seconds
Started Jan 21 10:13:08 PM PST 24
Finished Jan 21 10:13:14 PM PST 24
Peak memory 241404 kb
Host smart-f1d52e37-5e3c-4493-9af6-72a15b280b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661668551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2661668551
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.3096845029
Short name T120
Test name
Test status
Simulation time 812633096 ps
CPU time 19.59 seconds
Started Jan 21 10:13:12 PM PST 24
Finished Jan 21 10:13:34 PM PST 24
Peak memory 239808 kb
Host smart-b67dabac-3b83-46df-8254-39e6a2d50ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096845029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3096845029
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.3606022481
Short name T363
Test name
Test status
Simulation time 6007845024 ps
CPU time 17.15 seconds
Started Jan 21 10:13:12 PM PST 24
Finished Jan 21 10:13:31 PM PST 24
Peak memory 238940 kb
Host smart-cc0233b4-b8a0-43b1-93ac-6a2c8b856dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606022481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3606022481
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.765955238
Short name T507
Test name
Test status
Simulation time 145602852 ps
CPU time 3.92 seconds
Started Jan 21 10:13:10 PM PST 24
Finished Jan 21 10:13:15 PM PST 24
Peak memory 242484 kb
Host smart-b032a291-40e0-4faf-aeeb-aa1cb7bc8fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765955238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.765955238
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.4285199412
Short name T1202
Test name
Test status
Simulation time 684421808 ps
CPU time 8.52 seconds
Started Jan 21 10:13:13 PM PST 24
Finished Jan 21 10:13:25 PM PST 24
Peak memory 238832 kb
Host smart-7923b0f7-6738-49a8-ab7f-2e636fc9c9ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285199412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.4285199412
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.1813017795
Short name T685
Test name
Test status
Simulation time 3265701154 ps
CPU time 10.17 seconds
Started Jan 21 10:13:13 PM PST 24
Finished Jan 21 10:13:27 PM PST 24
Peak memory 238812 kb
Host smart-dc822e4f-9541-4438-8e0f-554fae8b6128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813017795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1813017795
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1800171840
Short name T1025
Test name
Test status
Simulation time 240600136 ps
CPU time 3.18 seconds
Started Jan 21 10:57:27 PM PST 24
Finished Jan 21 10:57:35 PM PST 24
Peak memory 243636 kb
Host smart-fa1eb365-69b8-4a41-8404-de29c9ad2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800171840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1800171840
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.1570190773
Short name T876
Test name
Test status
Simulation time 109616550332 ps
CPU time 266.5 seconds
Started Jan 21 10:13:10 PM PST 24
Finished Jan 21 10:17:39 PM PST 24
Peak memory 257012 kb
Host smart-8db5a866-6709-4d34-a92a-0457b13fcbe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570190773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.1570190773
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.1150711433
Short name T985
Test name
Test status
Simulation time 221214187679 ps
CPU time 4839.93 seconds
Started Jan 21 10:13:07 PM PST 24
Finished Jan 21 11:33:49 PM PST 24
Peak memory 288144 kb
Host smart-f571d38f-92f4-40d2-bca4-594473734f52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150711433 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.1150711433
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.2491587812
Short name T105
Test name
Test status
Simulation time 8639536410 ps
CPU time 22.21 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:40 PM PST 24
Peak memory 238920 kb
Host smart-d7e43103-8b98-471e-aa65-1d06d4f407d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491587812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2491587812
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.4065612284
Short name T908
Test name
Test status
Simulation time 248697042 ps
CPU time 5 seconds
Started Jan 21 10:19:03 PM PST 24
Finished Jan 21 10:19:11 PM PST 24
Peak memory 241148 kb
Host smart-0f41b538-e415-4f58-af47-6c79def07dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065612284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.4065612284
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2150748373
Short name T965
Test name
Test status
Simulation time 300894697 ps
CPU time 3.56 seconds
Started Jan 21 10:18:57 PM PST 24
Finished Jan 21 10:19:05 PM PST 24
Peak memory 247028 kb
Host smart-99830370-6e02-4995-bde4-d5ad8315e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150748373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2150748373
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.1756442343
Short name T645
Test name
Test status
Simulation time 529676480 ps
CPU time 5.1 seconds
Started Jan 21 10:18:55 PM PST 24
Finished Jan 21 10:19:05 PM PST 24
Peak memory 241200 kb
Host smart-c7f2b971-25ee-4d7c-b61e-348c43e2ed87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756442343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1756442343
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3437194925
Short name T206
Test name
Test status
Simulation time 271176256 ps
CPU time 4.67 seconds
Started Jan 21 10:19:07 PM PST 24
Finished Jan 21 10:19:18 PM PST 24
Peak memory 238720 kb
Host smart-8eac3c41-4598-4b75-8557-dcf9b0dd6b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437194925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3437194925
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.2693275824
Short name T777
Test name
Test status
Simulation time 240341663 ps
CPU time 3.84 seconds
Started Jan 21 10:19:05 PM PST 24
Finished Jan 21 10:19:14 PM PST 24
Peak memory 238684 kb
Host smart-db946526-3e4e-4ad4-9eb9-feb0a6446ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693275824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2693275824
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.940203862
Short name T990
Test name
Test status
Simulation time 304783546 ps
CPU time 8.01 seconds
Started Jan 21 11:12:02 PM PST 24
Finished Jan 21 11:12:14 PM PST 24
Peak memory 244592 kb
Host smart-63bbeb17-8abe-47ec-99d2-667a013ad0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940203862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.940203862
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.1878836576
Short name T455
Test name
Test status
Simulation time 166446545 ps
CPU time 4.64 seconds
Started Jan 21 10:19:06 PM PST 24
Finished Jan 21 10:19:17 PM PST 24
Peak memory 244204 kb
Host smart-235d8a66-404f-4cef-88b6-61673c9c8237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878836576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1878836576
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.60749938
Short name T596
Test name
Test status
Simulation time 453636382 ps
CPU time 5.32 seconds
Started Jan 21 10:19:00 PM PST 24
Finished Jan 21 10:19:09 PM PST 24
Peak memory 240824 kb
Host smart-7a45f9b6-617c-4754-96ed-65e63ea74feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60749938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.60749938
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.142564391
Short name T1223
Test name
Test status
Simulation time 245026324 ps
CPU time 6.49 seconds
Started Jan 21 10:19:05 PM PST 24
Finished Jan 21 10:19:18 PM PST 24
Peak memory 242648 kb
Host smart-a92bd35f-49ad-47d5-81f4-699590b5b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142564391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.142564391
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.1646225683
Short name T171
Test name
Test status
Simulation time 2619241664 ps
CPU time 5.97 seconds
Started Jan 21 10:19:04 PM PST 24
Finished Jan 21 10:19:15 PM PST 24
Peak memory 242176 kb
Host smart-e69e2ee2-df54-4de5-8166-cea54c8349c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646225683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1646225683
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.4161954257
Short name T1230
Test name
Test status
Simulation time 125758866 ps
CPU time 3.11 seconds
Started Jan 21 10:19:00 PM PST 24
Finished Jan 21 10:19:06 PM PST 24
Peak memory 238796 kb
Host smart-067063f0-5cff-43b9-8b1f-1a8797bda20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161954257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.4161954257
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.4124618094
Short name T498
Test name
Test status
Simulation time 220112831 ps
CPU time 4.57 seconds
Started Jan 21 10:19:03 PM PST 24
Finished Jan 21 10:19:11 PM PST 24
Peak memory 238804 kb
Host smart-fb0fa673-3587-4a26-9786-93fdb2cbcfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124618094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.4124618094
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1213618128
Short name T662
Test name
Test status
Simulation time 717202157 ps
CPU time 5.1 seconds
Started Jan 21 10:19:05 PM PST 24
Finished Jan 21 10:19:16 PM PST 24
Peak memory 241220 kb
Host smart-6b7c87f7-2fc2-4837-9c22-53f6f9480c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213618128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1213618128
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.1090170714
Short name T844
Test name
Test status
Simulation time 567285359 ps
CPU time 3.96 seconds
Started Jan 21 10:19:05 PM PST 24
Finished Jan 21 10:19:14 PM PST 24
Peak memory 238704 kb
Host smart-e48c42fa-122d-4551-abb9-bd6e1d15f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090170714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1090170714
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1281937426
Short name T1071
Test name
Test status
Simulation time 205729689 ps
CPU time 4.87 seconds
Started Jan 21 10:19:04 PM PST 24
Finished Jan 21 10:19:15 PM PST 24
Peak memory 238716 kb
Host smart-f37dbb3e-975f-4584-b4b7-d96bf74bf6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281937426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1281937426
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2132889592
Short name T655
Test name
Test status
Simulation time 365100467 ps
CPU time 4.8 seconds
Started Jan 21 10:19:04 PM PST 24
Finished Jan 21 10:19:14 PM PST 24
Peak memory 238760 kb
Host smart-eeb51b07-2042-4f29-a378-28ed571b2a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132889592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2132889592
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.3957766948
Short name T461
Test name
Test status
Simulation time 189863908 ps
CPU time 2.77 seconds
Started Jan 21 11:21:43 PM PST 24
Finished Jan 21 11:21:53 PM PST 24
Peak memory 238836 kb
Host smart-8b8ee72e-03bc-4330-b910-19321c95fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957766948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3957766948
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.639467791
Short name T735
Test name
Test status
Simulation time 1502667178 ps
CPU time 5.11 seconds
Started Jan 21 10:19:09 PM PST 24
Finished Jan 21 10:19:21 PM PST 24
Peak memory 246936 kb
Host smart-5a4e477e-9d7b-4dc8-9332-3cf11dc5e066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639467791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.639467791
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.945718144
Short name T589
Test name
Test status
Simulation time 792944580 ps
CPU time 4.86 seconds
Started Jan 21 10:19:08 PM PST 24
Finished Jan 21 10:19:18 PM PST 24
Peak memory 242652 kb
Host smart-91c926a9-6839-45b9-9166-0ef809be3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945718144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.945718144
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.81771447
Short name T89
Test name
Test status
Simulation time 87327720 ps
CPU time 1.9 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:19 PM PST 24
Peak memory 239684 kb
Host smart-a9c088e8-af65-4f4e-9c5a-eb9637f069bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81771447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.81771447
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.346778449
Short name T46
Test name
Test status
Simulation time 5910626281 ps
CPU time 15.45 seconds
Started Jan 21 10:13:14 PM PST 24
Finished Jan 21 10:13:32 PM PST 24
Peak memory 247024 kb
Host smart-ebf40469-aee9-404f-aa41-43f3d7d98815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346778449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.346778449
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.1550748158
Short name T1261
Test name
Test status
Simulation time 382425936 ps
CPU time 10.41 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:28 PM PST 24
Peak memory 238568 kb
Host smart-27dfb33a-2ba0-4de9-aa6c-46372f543d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550748158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1550748158
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.758953282
Short name T796
Test name
Test status
Simulation time 273675326 ps
CPU time 3.46 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:21 PM PST 24
Peak memory 238652 kb
Host smart-1a1ea237-79fd-4db5-ada0-3db510f67729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758953282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.758953282
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.2375734567
Short name T1103
Test name
Test status
Simulation time 96380556 ps
CPU time 3.07 seconds
Started Jan 21 10:13:10 PM PST 24
Finished Jan 21 10:13:15 PM PST 24
Peak memory 241312 kb
Host smart-9bb4c836-3ae0-4ad9-96ed-165cf04d7c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375734567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2375734567
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.506961084
Short name T1077
Test name
Test status
Simulation time 1524119091 ps
CPU time 22.44 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:40 PM PST 24
Peak memory 238780 kb
Host smart-57d8b167-e1e2-4fea-8d1d-1f87d871c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506961084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.506961084
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.4080217896
Short name T1272
Test name
Test status
Simulation time 746133196 ps
CPU time 16.73 seconds
Started Jan 21 10:13:19 PM PST 24
Finished Jan 21 10:13:39 PM PST 24
Peak memory 244964 kb
Host smart-cb3b309e-c361-437d-a1ac-07ab82006900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080217896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.4080217896
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.3628798970
Short name T1005
Test name
Test status
Simulation time 303316889 ps
CPU time 6.87 seconds
Started Jan 21 10:13:11 PM PST 24
Finished Jan 21 10:13:19 PM PST 24
Peak memory 238720 kb
Host smart-d6aea7b8-0725-4a24-82c5-3089ad56c800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628798970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3628798970
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.2902862541
Short name T154
Test name
Test status
Simulation time 223480559 ps
CPU time 4.94 seconds
Started Jan 21 10:13:16 PM PST 24
Finished Jan 21 10:13:23 PM PST 24
Peak memory 238788 kb
Host smart-d17547fb-e3c6-45c4-bfd5-87a483a85a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902862541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.2902862541
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.44527160
Short name T931
Test name
Test status
Simulation time 2376760695 ps
CPU time 4.65 seconds
Started Jan 21 10:13:15 PM PST 24
Finished Jan 21 10:13:22 PM PST 24
Peak memory 238852 kb
Host smart-0c981d4a-8cbc-4b3d-81a3-3e68fee5e149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44527160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.44527160
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.3458445733
Short name T799
Test name
Test status
Simulation time 16353262654 ps
CPU time 128.86 seconds
Started Jan 21 10:13:19 PM PST 24
Finished Jan 21 10:15:31 PM PST 24
Peak memory 247000 kb
Host smart-d04f7fea-bdd3-45fc-9b57-3467561950ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458445733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.3458445733
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.811793434
Short name T914
Test name
Test status
Simulation time 5361498749671 ps
CPU time 6443.33 seconds
Started Jan 21 10:13:13 PM PST 24
Finished Jan 22 12:00:40 AM PST 24
Peak memory 341136 kb
Host smart-01d72db4-2ecc-4ddd-a57d-51895ed1bc16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811793434 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.811793434
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2345343072
Short name T49
Test name
Test status
Simulation time 250617387 ps
CPU time 3.97 seconds
Started Jan 21 10:19:17 PM PST 24
Finished Jan 21 10:19:27 PM PST 24
Peak memory 238752 kb
Host smart-88de5f9b-4e9f-47ce-b603-09499c04b792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345343072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2345343072
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1951769190
Short name T957
Test name
Test status
Simulation time 582244131 ps
CPU time 4.36 seconds
Started Jan 21 10:19:10 PM PST 24
Finished Jan 21 10:19:21 PM PST 24
Peak memory 238876 kb
Host smart-1c326599-0b8b-4005-9b4e-d60ad0db4f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951769190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1951769190
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.1436015609
Short name T1030
Test name
Test status
Simulation time 229604103 ps
CPU time 3.48 seconds
Started Jan 21 10:19:17 PM PST 24
Finished Jan 21 10:19:25 PM PST 24
Peak memory 238748 kb
Host smart-6d846c1d-d3be-4300-b1d4-6b17279e20a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436015609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.1436015609
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.890236131
Short name T961
Test name
Test status
Simulation time 370794476 ps
CPU time 3.83 seconds
Started Jan 21 10:19:11 PM PST 24
Finished Jan 21 10:19:21 PM PST 24
Peak memory 232552 kb
Host smart-1397acfa-1a5a-4af3-aea7-3e9defc6f198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890236131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.890236131
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3415538134
Short name T600
Test name
Test status
Simulation time 128731964 ps
CPU time 4.96 seconds
Started Jan 21 10:19:09 PM PST 24
Finished Jan 21 10:19:21 PM PST 24
Peak memory 238772 kb
Host smart-1e544c8d-c177-4377-b315-4b7799622c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415538134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3415538134
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.3860795218
Short name T952
Test name
Test status
Simulation time 155303935 ps
CPU time 3.93 seconds
Started Jan 21 10:19:17 PM PST 24
Finished Jan 21 10:19:26 PM PST 24
Peak memory 241284 kb
Host smart-6b16dc3a-737b-4e8f-bd61-91837ecba491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860795218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.3860795218
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2919193472
Short name T648
Test name
Test status
Simulation time 2101097404 ps
CPU time 7.28 seconds
Started Jan 21 10:19:10 PM PST 24
Finished Jan 21 10:19:24 PM PST 24
Peak memory 238732 kb
Host smart-6f57969c-d6f2-4db9-844c-e38cb45b588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919193472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2919193472
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.2051196652
Short name T492
Test name
Test status
Simulation time 4151156539 ps
CPU time 11.36 seconds
Started Jan 21 10:19:17 PM PST 24
Finished Jan 21 10:19:34 PM PST 24
Peak memory 243964 kb
Host smart-55b20a7c-0503-4a98-96f8-539dfd2c420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051196652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.2051196652
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.1404370583
Short name T1229
Test name
Test status
Simulation time 202662389 ps
CPU time 4 seconds
Started Jan 21 10:19:09 PM PST 24
Finished Jan 21 10:19:20 PM PST 24
Peak memory 241320 kb
Host smart-f1854129-3300-4dcb-8712-d59262f248ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404370583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1404370583
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1166375445
Short name T534
Test name
Test status
Simulation time 1215981011 ps
CPU time 8.35 seconds
Started Jan 21 10:19:17 PM PST 24
Finished Jan 21 10:19:31 PM PST 24
Peak memory 238656 kb
Host smart-c612c7c7-36db-48d8-95a0-31b918220619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166375445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1166375445
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.3418067494
Short name T658
Test name
Test status
Simulation time 205198753 ps
CPU time 4.35 seconds
Started Jan 21 10:19:09 PM PST 24
Finished Jan 21 10:19:20 PM PST 24
Peak memory 241428 kb
Host smart-28eaab8c-8fd2-4ebb-961f-81ea52e5e0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418067494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3418067494
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.125622193
Short name T613
Test name
Test status
Simulation time 948518229 ps
CPU time 6.64 seconds
Started Jan 21 10:19:15 PM PST 24
Finished Jan 21 10:19:27 PM PST 24
Peak memory 238788 kb
Host smart-3d797901-969a-42ef-85ce-0b4117e94b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125622193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.125622193
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.1953225919
Short name T641
Test name
Test status
Simulation time 1587048524 ps
CPU time 4.61 seconds
Started Jan 21 10:19:16 PM PST 24
Finished Jan 21 10:19:25 PM PST 24
Peak memory 240816 kb
Host smart-a1c2e8c2-9069-4b58-8ff0-ee225bad8878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953225919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.1953225919
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.3147930845
Short name T771
Test name
Test status
Simulation time 513119293 ps
CPU time 5.27 seconds
Started Jan 21 10:19:20 PM PST 24
Finished Jan 21 10:19:31 PM PST 24
Peak memory 238712 kb
Host smart-d35f2ebf-7ffd-4098-967a-d60c4ce3afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147930845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3147930845
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.2901208895
Short name T513
Test name
Test status
Simulation time 121389377 ps
CPU time 4.42 seconds
Started Jan 21 10:19:18 PM PST 24
Finished Jan 21 10:19:28 PM PST 24
Peak memory 238744 kb
Host smart-163fbfc5-1ad9-4d08-84dd-c62e05918525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901208895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2901208895
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.846246868
Short name T791
Test name
Test status
Simulation time 146447423 ps
CPU time 4.72 seconds
Started Jan 21 10:19:18 PM PST 24
Finished Jan 21 10:19:28 PM PST 24
Peak memory 242352 kb
Host smart-e8dccf16-074d-40a3-a63f-95246d6486e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846246868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.846246868
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.205107457
Short name T652
Test name
Test status
Simulation time 679513139 ps
CPU time 4.52 seconds
Started Jan 21 10:19:19 PM PST 24
Finished Jan 21 10:19:29 PM PST 24
Peak memory 238724 kb
Host smart-0f04e387-2104-441e-af69-7903f65b24ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205107457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.205107457
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.565057365
Short name T319
Test name
Test status
Simulation time 192757981 ps
CPU time 3.09 seconds
Started Jan 21 10:19:21 PM PST 24
Finished Jan 21 10:19:30 PM PST 24
Peak memory 238660 kb
Host smart-7ee08264-d7a5-4f65-a6bd-58b014f53592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565057365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.565057365
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.247314217
Short name T1214
Test name
Test status
Simulation time 106696544 ps
CPU time 2.92 seconds
Started Jan 21 10:19:20 PM PST 24
Finished Jan 21 10:19:28 PM PST 24
Peak memory 238796 kb
Host smart-07b4bda0-b6b3-4dac-8808-e01b66eac700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247314217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.247314217
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1085157651
Short name T527
Test name
Test status
Simulation time 769878648 ps
CPU time 1.96 seconds
Started Jan 21 10:13:25 PM PST 24
Finished Jan 21 10:13:31 PM PST 24
Peak memory 238580 kb
Host smart-f8b62bee-40fa-4936-93db-3855c7672798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085157651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1085157651
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.2156026318
Short name T1173
Test name
Test status
Simulation time 548076818 ps
CPU time 6.25 seconds
Started Jan 21 10:13:19 PM PST 24
Finished Jan 21 10:13:28 PM PST 24
Peak memory 238892 kb
Host smart-6e52f04e-37a2-488f-9603-f38f601355d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156026318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2156026318
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.319041721
Short name T918
Test name
Test status
Simulation time 469094552 ps
CPU time 6.83 seconds
Started Jan 21 10:13:17 PM PST 24
Finished Jan 21 10:13:27 PM PST 24
Peak memory 239020 kb
Host smart-a856581f-42ab-4196-a43c-d57005143e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319041721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.319041721
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.4178878256
Short name T1007
Test name
Test status
Simulation time 602976929 ps
CPU time 14.95 seconds
Started Jan 21 10:13:21 PM PST 24
Finished Jan 21 10:13:38 PM PST 24
Peak memory 244680 kb
Host smart-399a7a2d-a384-491e-b849-723173a95a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178878256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.4178878256
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1980548329
Short name T550
Test name
Test status
Simulation time 2487556124 ps
CPU time 7.7 seconds
Started Jan 21 10:13:17 PM PST 24
Finished Jan 21 10:13:28 PM PST 24
Peak memory 241892 kb
Host smart-afa566c7-7160-49bf-b8f5-67835243c0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980548329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1980548329
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.4005306266
Short name T721
Test name
Test status
Simulation time 7005987279 ps
CPU time 14.84 seconds
Started Jan 21 10:13:20 PM PST 24
Finished Jan 21 10:13:38 PM PST 24
Peak memory 238784 kb
Host smart-d631aa5e-dd4d-4d01-8b20-a57deab2b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005306266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.4005306266
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1546922358
Short name T911
Test name
Test status
Simulation time 813211598 ps
CPU time 12.69 seconds
Started Jan 21 10:13:14 PM PST 24
Finished Jan 21 10:13:29 PM PST 24
Peak memory 244200 kb
Host smart-0ebd828a-eb31-4e53-ab0b-5380940b509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546922358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1546922358
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.2265101217
Short name T373
Test name
Test status
Simulation time 383364315 ps
CPU time 4.77 seconds
Started Jan 21 10:13:18 PM PST 24
Finished Jan 21 10:13:26 PM PST 24
Peak memory 238908 kb
Host smart-0aa4bf12-9745-4c20-83ea-5ca9605c5cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265101217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2265101217
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.1457509146
Short name T1091
Test name
Test status
Simulation time 926585150 ps
CPU time 11.99 seconds
Started Jan 21 10:13:17 PM PST 24
Finished Jan 21 10:13:31 PM PST 24
Peak memory 243344 kb
Host smart-34a6f5f5-94b0-435a-8edb-a2bb31f89644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457509146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1457509146
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.3401513080
Short name T1113
Test name
Test status
Simulation time 3252092134 ps
CPU time 11.56 seconds
Started Jan 21 10:13:17 PM PST 24
Finished Jan 21 10:13:31 PM PST 24
Peak memory 242464 kb
Host smart-bff031d1-4dd0-4d91-96bc-bcf85d4d1e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401513080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3401513080
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3144988217
Short name T806
Test name
Test status
Simulation time 278578981 ps
CPU time 4.22 seconds
Started Jan 21 10:13:19 PM PST 24
Finished Jan 21 10:13:27 PM PST 24
Peak memory 243060 kb
Host smart-c9217141-ad09-43b2-a9a9-ee03d470831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144988217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3144988217
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.229287275
Short name T1047
Test name
Test status
Simulation time 13393714271 ps
CPU time 116.41 seconds
Started Jan 21 10:13:20 PM PST 24
Finished Jan 21 10:15:19 PM PST 24
Peak memory 243920 kb
Host smart-c5c0269a-86c7-4d28-bc94-bf383950da1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229287275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.
229287275
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.742483191
Short name T1262
Test name
Test status
Simulation time 350871645603 ps
CPU time 5219.45 seconds
Started Jan 21 10:13:23 PM PST 24
Finished Jan 21 11:40:25 PM PST 24
Peak memory 304524 kb
Host smart-cb6ad46e-850a-423b-9b3f-bcd46e6b731c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742483191 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.742483191
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.3948115259
Short name T380
Test name
Test status
Simulation time 3610357781 ps
CPU time 20.03 seconds
Started Jan 21 10:13:20 PM PST 24
Finished Jan 21 10:13:43 PM PST 24
Peak memory 244524 kb
Host smart-91bdf471-4d82-483e-9ae6-f2477c2eca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948115259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3948115259
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.1670387448
Short name T1105
Test name
Test status
Simulation time 162572217 ps
CPU time 3.57 seconds
Started Jan 21 10:19:16 PM PST 24
Finished Jan 21 10:19:25 PM PST 24
Peak memory 241192 kb
Host smart-dbd2326e-10c6-4a92-a5be-bd49515bfaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670387448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.1670387448
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.47712382
Short name T1185
Test name
Test status
Simulation time 161430658 ps
CPU time 4.19 seconds
Started Jan 21 10:19:16 PM PST 24
Finished Jan 21 10:19:25 PM PST 24
Peak memory 241188 kb
Host smart-a9ece917-51b1-42ec-8c90-7a8ad605f2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47712382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.47712382
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.1360814213
Short name T834
Test name
Test status
Simulation time 157274402 ps
CPU time 3.71 seconds
Started Jan 21 10:19:19 PM PST 24
Finished Jan 21 10:19:29 PM PST 24
Peak memory 241392 kb
Host smart-162b8b77-d22d-4a3b-8863-9e37aaaaa616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360814213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1360814213
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2932818068
Short name T822
Test name
Test status
Simulation time 481208113 ps
CPU time 6.34 seconds
Started Jan 21 10:19:19 PM PST 24
Finished Jan 21 10:19:32 PM PST 24
Peak memory 242704 kb
Host smart-41c02052-1def-40f6-a9af-9694647efdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932818068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2932818068
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.2787822685
Short name T686
Test name
Test status
Simulation time 255015424 ps
CPU time 3.89 seconds
Started Jan 21 10:19:15 PM PST 24
Finished Jan 21 10:19:24 PM PST 24
Peak memory 246912 kb
Host smart-898765b8-c601-4c5d-84db-2d84a7de42e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787822685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.2787822685
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.4068519826
Short name T107
Test name
Test status
Simulation time 149016982 ps
CPU time 6.58 seconds
Started Jan 21 10:19:21 PM PST 24
Finished Jan 21 10:19:33 PM PST 24
Peak memory 243244 kb
Host smart-bd43623d-d2af-4388-8d02-867696b2700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068519826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.4068519826
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.4268735656
Short name T949
Test name
Test status
Simulation time 211339234 ps
CPU time 3.74 seconds
Started Jan 21 10:19:33 PM PST 24
Finished Jan 21 10:19:40 PM PST 24
Peak memory 241356 kb
Host smart-d4cdd68a-45bc-407a-be64-78afc35cbac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268735656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.4268735656
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1194453226
Short name T312
Test name
Test status
Simulation time 147436928 ps
CPU time 4.07 seconds
Started Jan 21 10:19:31 PM PST 24
Finished Jan 21 10:19:40 PM PST 24
Peak memory 238716 kb
Host smart-55b62a6f-fa2d-475e-ad8a-d616f7c8db2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194453226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1194453226
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.2301773650
Short name T696
Test name
Test status
Simulation time 173311537 ps
CPU time 4.54 seconds
Started Jan 21 10:19:31 PM PST 24
Finished Jan 21 10:19:40 PM PST 24
Peak memory 241300 kb
Host smart-11701dda-a493-481d-a3a6-2a4bb7b91bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301773650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2301773650
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2886729289
Short name T156
Test name
Test status
Simulation time 136261662 ps
CPU time 3.52 seconds
Started Jan 21 10:19:30 PM PST 24
Finished Jan 21 10:19:39 PM PST 24
Peak memory 241912 kb
Host smart-3bda195b-bc3a-45b2-9445-3973ce215a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886729289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2886729289
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1627529979
Short name T947
Test name
Test status
Simulation time 2944700322 ps
CPU time 7.69 seconds
Started Jan 21 10:19:33 PM PST 24
Finished Jan 21 10:19:44 PM PST 24
Peak memory 242324 kb
Host smart-c6699d1b-3272-47a5-b20a-02b2af9eb622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627529979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1627529979
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1580384737
Short name T825
Test name
Test status
Simulation time 339522736 ps
CPU time 4.91 seconds
Started Jan 21 10:19:34 PM PST 24
Finished Jan 21 10:19:43 PM PST 24
Peak memory 238728 kb
Host smart-fc879f32-e174-4f8c-8ce0-d1b392f14905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580384737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1580384737
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.3487659079
Short name T715
Test name
Test status
Simulation time 877377900 ps
CPU time 6.93 seconds
Started Jan 21 10:19:29 PM PST 24
Finished Jan 21 10:19:41 PM PST 24
Peak memory 243488 kb
Host smart-2e5ec72e-0d58-4e9b-afa5-f3dd41c36e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487659079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.3487659079
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.1135944440
Short name T851
Test name
Test status
Simulation time 157260149 ps
CPU time 4.31 seconds
Started Jan 21 10:19:27 PM PST 24
Finished Jan 21 10:19:37 PM PST 24
Peak memory 238760 kb
Host smart-bc838c46-4023-4e01-9d0f-ae2f030b2f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135944440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1135944440
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3660728553
Short name T620
Test name
Test status
Simulation time 4716471788 ps
CPU time 10.1 seconds
Started Jan 21 10:19:34 PM PST 24
Finished Jan 21 10:19:48 PM PST 24
Peak memory 238964 kb
Host smart-367075e8-c7df-42af-87dc-9849b7da5b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660728553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3660728553
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.94789749
Short name T976
Test name
Test status
Simulation time 446478011 ps
CPU time 4.58 seconds
Started Jan 21 10:19:30 PM PST 24
Finished Jan 21 10:19:40 PM PST 24
Peak memory 241328 kb
Host smart-9cac4d44-e416-4a96-972a-b99c004cb086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94789749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.94789749
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.732551981
Short name T1050
Test name
Test status
Simulation time 355349986 ps
CPU time 2.89 seconds
Started Jan 21 10:19:34 PM PST 24
Finished Jan 21 10:19:41 PM PST 24
Peak memory 238884 kb
Host smart-a4f137f8-e8c1-4994-9d0e-db47c9306b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732551981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.732551981
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2677686536
Short name T150
Test name
Test status
Simulation time 376084460 ps
CPU time 4.78 seconds
Started Jan 21 10:19:32 PM PST 24
Finished Jan 21 10:19:41 PM PST 24
Peak memory 241268 kb
Host smart-7269b864-3ae8-4322-a8a4-7c5e428fe9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677686536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2677686536
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.3576635937
Short name T590
Test name
Test status
Simulation time 656594080 ps
CPU time 5.59 seconds
Started Jan 21 10:19:32 PM PST 24
Finished Jan 21 10:19:42 PM PST 24
Peak memory 243004 kb
Host smart-d7171147-4ecc-4984-b903-5717b3e6a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576635937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.3576635937
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.2261567573
Short name T1292
Test name
Test status
Simulation time 93563289 ps
CPU time 2.11 seconds
Started Jan 21 10:13:30 PM PST 24
Finished Jan 21 10:13:35 PM PST 24
Peak memory 239584 kb
Host smart-d4cc2fb8-9f9e-46f9-85e6-2958b4487a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261567573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2261567573
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2345082861
Short name T71
Test name
Test status
Simulation time 879684414 ps
CPU time 12.07 seconds
Started Jan 21 10:13:23 PM PST 24
Finished Jan 21 10:13:38 PM PST 24
Peak memory 238744 kb
Host smart-8ae2c608-6651-4ccb-9e9b-a832905aa3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345082861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2345082861
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.1792094915
Short name T752
Test name
Test status
Simulation time 4877943908 ps
CPU time 12.54 seconds
Started Jan 21 10:13:28 PM PST 24
Finished Jan 21 10:13:44 PM PST 24
Peak memory 245368 kb
Host smart-94e9dbc4-0431-4d10-9dd2-ddf311e52e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792094915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1792094915
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.1884884286
Short name T553
Test name
Test status
Simulation time 981384784 ps
CPU time 8.27 seconds
Started Jan 21 10:13:25 PM PST 24
Finished Jan 21 10:13:38 PM PST 24
Peak memory 243156 kb
Host smart-9335b32d-b850-483a-b5cf-b35a923829e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884884286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.1884884286
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.1988867813
Short name T1029
Test name
Test status
Simulation time 125514295 ps
CPU time 4.42 seconds
Started Jan 21 10:13:20 PM PST 24
Finished Jan 21 10:13:27 PM PST 24
Peak memory 241016 kb
Host smart-fa04cf0a-6c5c-4545-b29c-c1b31eb9ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988867813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1988867813
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.1450786085
Short name T1022
Test name
Test status
Simulation time 2898432081 ps
CPU time 21.25 seconds
Started Jan 21 10:13:30 PM PST 24
Finished Jan 21 10:13:55 PM PST 24
Peak memory 238896 kb
Host smart-b3217c2e-cf6d-423e-9544-3c9bae0ff36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450786085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.1450786085
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.1023524128
Short name T928
Test name
Test status
Simulation time 574229094 ps
CPU time 5.84 seconds
Started Jan 21 10:13:29 PM PST 24
Finished Jan 21 10:13:39 PM PST 24
Peak memory 238776 kb
Host smart-e57ddee3-347c-4b70-8590-b4c347ea285d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023524128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.1023524128
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.1109784717
Short name T912
Test name
Test status
Simulation time 436406067 ps
CPU time 3.9 seconds
Started Jan 21 10:13:31 PM PST 24
Finished Jan 21 10:13:38 PM PST 24
Peak memory 238736 kb
Host smart-a3063510-9b22-450f-a6b2-7093cdd50fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109784717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.1109784717
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.3412112705
Short name T875
Test name
Test status
Simulation time 977987262 ps
CPU time 22.07 seconds
Started Jan 21 10:13:22 PM PST 24
Finished Jan 21 10:13:47 PM PST 24
Peak memory 238792 kb
Host smart-21489d9e-ae6e-471f-8e0e-e5f7bd1490b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412112705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.3412112705
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.2361949645
Short name T872
Test name
Test status
Simulation time 206906767 ps
CPU time 3.82 seconds
Started Jan 21 10:13:28 PM PST 24
Finished Jan 21 10:13:36 PM PST 24
Peak memory 238664 kb
Host smart-280296ba-0e2a-4847-9e3f-d86d059be966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361949645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2361949645
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.1228992695
Short name T108
Test name
Test status
Simulation time 436414873 ps
CPU time 4.84 seconds
Started Jan 21 10:13:24 PM PST 24
Finished Jan 21 10:13:32 PM PST 24
Peak memory 238724 kb
Host smart-53bdb256-967e-4ab0-a39f-6618479d0bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228992695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.1228992695
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1683713702
Short name T1078
Test name
Test status
Simulation time 965381633655 ps
CPU time 3520 seconds
Started Jan 21 10:13:29 PM PST 24
Finished Jan 21 11:12:14 PM PST 24
Peak memory 883148 kb
Host smart-5e7be3f1-d96c-484f-8a5a-4a0903fb71c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683713702 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.1683713702
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.4117966757
Short name T1152
Test name
Test status
Simulation time 269922891 ps
CPU time 6.42 seconds
Started Jan 21 10:13:30 PM PST 24
Finished Jan 21 10:13:40 PM PST 24
Peak memory 246940 kb
Host smart-b4bf6a47-9ea9-4cd2-9818-5ec2d283b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117966757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.4117966757
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.1446384188
Short name T1285
Test name
Test status
Simulation time 2210854642 ps
CPU time 4.85 seconds
Started Jan 21 10:19:32 PM PST 24
Finished Jan 21 10:19:41 PM PST 24
Peak memory 241044 kb
Host smart-f48dc4cf-2142-4fd6-b254-28eacaa4fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446384188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.1446384188
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3435451736
Short name T968
Test name
Test status
Simulation time 180589157 ps
CPU time 3.79 seconds
Started Jan 21 10:19:31 PM PST 24
Finished Jan 21 10:19:39 PM PST 24
Peak memory 241672 kb
Host smart-413b8f58-28cc-4fe7-a152-421185f14e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435451736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3435451736
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.2123835206
Short name T561
Test name
Test status
Simulation time 303003369 ps
CPU time 4 seconds
Started Jan 21 10:19:43 PM PST 24
Finished Jan 21 10:19:50 PM PST 24
Peak memory 238472 kb
Host smart-b9353d89-083e-4357-a30e-4e7c0893ba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123835206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2123835206
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.3245724239
Short name T1246
Test name
Test status
Simulation time 81717081 ps
CPU time 2.6 seconds
Started Jan 21 10:19:29 PM PST 24
Finished Jan 21 10:19:37 PM PST 24
Peak memory 241332 kb
Host smart-a81f34e2-1a7d-4eaf-a2ed-b32c1596f16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245724239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3245724239
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.435146351
Short name T36
Test name
Test status
Simulation time 295571342 ps
CPU time 5.05 seconds
Started Jan 21 10:19:35 PM PST 24
Finished Jan 21 10:19:43 PM PST 24
Peak memory 240680 kb
Host smart-60765140-6394-46de-a3c7-6ab000c9a1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435146351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.435146351
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.430782334
Short name T747
Test name
Test status
Simulation time 790168335 ps
CPU time 6.15 seconds
Started Jan 21 10:19:45 PM PST 24
Finished Jan 21 10:19:54 PM PST 24
Peak memory 243012 kb
Host smart-863ab285-5e27-478d-be26-3cd8abe1c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430782334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.430782334
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.4103802798
Short name T1256
Test name
Test status
Simulation time 435097651 ps
CPU time 4.57 seconds
Started Jan 21 10:19:45 PM PST 24
Finished Jan 21 10:19:52 PM PST 24
Peak memory 238748 kb
Host smart-e40b7fdd-77d3-4a0b-994d-c4c3d3448a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103802798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.4103802798
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.3112301628
Short name T1164
Test name
Test status
Simulation time 3411170167 ps
CPU time 9.49 seconds
Started Jan 21 10:19:45 PM PST 24
Finished Jan 21 10:19:57 PM PST 24
Peak memory 243664 kb
Host smart-e590d58c-e349-4b69-9d75-3c8dc07263cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112301628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3112301628
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2421154635
Short name T166
Test name
Test status
Simulation time 147727324 ps
CPU time 4.1 seconds
Started Jan 21 10:19:34 PM PST 24
Finished Jan 21 10:19:42 PM PST 24
Peak memory 241236 kb
Host smart-656de483-9248-42af-a19f-e695d33e2e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421154635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2421154635
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.2246512884
Short name T1055
Test name
Test status
Simulation time 728470459 ps
CPU time 7.13 seconds
Started Jan 21 10:19:40 PM PST 24
Finished Jan 21 10:19:52 PM PST 24
Peak memory 238712 kb
Host smart-36253268-38a9-499e-8469-b009ef7f13ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246512884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2246512884
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2837387076
Short name T1288
Test name
Test status
Simulation time 494193261 ps
CPU time 4.91 seconds
Started Jan 21 10:19:34 PM PST 24
Finished Jan 21 10:19:43 PM PST 24
Peak memory 238792 kb
Host smart-a86f30b3-f8ce-4488-959d-9b9d8b0809c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837387076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2837387076
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.2217866889
Short name T174
Test name
Test status
Simulation time 267133575 ps
CPU time 5.01 seconds
Started Jan 21 10:19:40 PM PST 24
Finished Jan 21 10:19:50 PM PST 24
Peak memory 243684 kb
Host smart-2f31a416-52a3-4a1f-8825-d5fc95cd06d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217866889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2217866889
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3243500698
Short name T839
Test name
Test status
Simulation time 184880670 ps
CPU time 3.65 seconds
Started Jan 21 10:19:37 PM PST 24
Finished Jan 21 10:19:44 PM PST 24
Peak memory 241256 kb
Host smart-6f953703-067d-4795-b551-62487fcfc9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243500698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3243500698
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.3581072158
Short name T535
Test name
Test status
Simulation time 803647045 ps
CPU time 9.26 seconds
Started Jan 21 10:19:45 PM PST 24
Finished Jan 21 10:19:57 PM PST 24
Peak memory 244584 kb
Host smart-01d79df0-a4f1-41b3-bcd2-95d31a84f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581072158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3581072158
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.3054886761
Short name T833
Test name
Test status
Simulation time 440723458 ps
CPU time 4.31 seconds
Started Jan 21 10:19:45 PM PST 24
Finished Jan 21 10:19:52 PM PST 24
Peak memory 240680 kb
Host smart-e95abeeb-d51d-431d-9916-02836a9cd118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054886761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3054886761
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.4165941576
Short name T934
Test name
Test status
Simulation time 405985075 ps
CPU time 3.7 seconds
Started Jan 21 10:19:43 PM PST 24
Finished Jan 21 10:19:50 PM PST 24
Peak memory 238540 kb
Host smart-027f32bd-3b95-4b47-85e9-f7fa5fbf0823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165941576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.4165941576
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1856580753
Short name T552
Test name
Test status
Simulation time 124613746 ps
CPU time 3.13 seconds
Started Jan 21 10:19:43 PM PST 24
Finished Jan 21 10:19:50 PM PST 24
Peak memory 241112 kb
Host smart-19669671-95f0-4ae1-a9b9-18b1c57d4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856580753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1856580753
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.2166250341
Short name T5
Test name
Test status
Simulation time 178605971 ps
CPU time 2.38 seconds
Started Jan 21 10:19:40 PM PST 24
Finished Jan 21 10:19:47 PM PST 24
Peak memory 240888 kb
Host smart-3957b398-a6fe-43a0-a7fb-5e44fb8c2284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166250341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.2166250341
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.271664596
Short name T994
Test name
Test status
Simulation time 133732976 ps
CPU time 3.69 seconds
Started Jan 21 10:19:32 PM PST 24
Finished Jan 21 10:19:40 PM PST 24
Peak memory 238600 kb
Host smart-5a369f3c-e630-40b0-93ed-d25629190de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271664596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.271664596
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.254793394
Short name T483
Test name
Test status
Simulation time 134086723 ps
CPU time 3.68 seconds
Started Jan 21 10:55:09 PM PST 24
Finished Jan 21 10:55:15 PM PST 24
Peak memory 242864 kb
Host smart-bc71937c-050b-491c-9e65-1ba2de59cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254793394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.254793394
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.161770917
Short name T804
Test name
Test status
Simulation time 609448869 ps
CPU time 2.33 seconds
Started Jan 21 10:13:41 PM PST 24
Finished Jan 21 10:13:47 PM PST 24
Peak memory 230564 kb
Host smart-a577a296-a2b4-4105-87b6-ce388f800bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161770917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.161770917
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.4051836976
Short name T72
Test name
Test status
Simulation time 1338747380 ps
CPU time 16.1 seconds
Started Jan 21 10:13:35 PM PST 24
Finished Jan 21 10:13:53 PM PST 24
Peak memory 238676 kb
Host smart-69598871-56fd-4064-a640-52122f6607f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051836976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.4051836976
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.405344090
Short name T612
Test name
Test status
Simulation time 871010091 ps
CPU time 10.26 seconds
Started Jan 21 10:13:38 PM PST 24
Finished Jan 21 10:13:51 PM PST 24
Peak memory 243584 kb
Host smart-840d63e6-166a-4ec6-9ddd-96431aff2a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405344090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.405344090
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.458718049
Short name T1084
Test name
Test status
Simulation time 618394752 ps
CPU time 12.22 seconds
Started Jan 21 10:13:34 PM PST 24
Finished Jan 21 10:13:48 PM PST 24
Peak memory 243736 kb
Host smart-94930f38-5a43-4c17-bdf3-ba1ef44c4d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458718049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.458718049
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.2123035995
Short name T810
Test name
Test status
Simulation time 169489331 ps
CPU time 3.33 seconds
Started Jan 21 10:13:27 PM PST 24
Finished Jan 21 10:13:35 PM PST 24
Peak memory 246924 kb
Host smart-467bc556-be6d-4134-b730-86ad1a5e5cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123035995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2123035995
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3221103105
Short name T132
Test name
Test status
Simulation time 2187867579 ps
CPU time 19.64 seconds
Started Jan 21 10:13:40 PM PST 24
Finished Jan 21 10:14:04 PM PST 24
Peak memory 247104 kb
Host smart-6759a491-fd77-4a96-988b-5e75d3580c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221103105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3221103105
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.3867781371
Short name T377
Test name
Test status
Simulation time 547945790 ps
CPU time 13.38 seconds
Started Jan 21 10:13:41 PM PST 24
Finished Jan 21 10:13:59 PM PST 24
Peak memory 238772 kb
Host smart-d07ba19c-6375-49e5-b303-f1f5e69919b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867781371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3867781371
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1816394587
Short name T547
Test name
Test status
Simulation time 350737131 ps
CPU time 2.52 seconds
Started Jan 21 10:13:32 PM PST 24
Finished Jan 21 10:13:37 PM PST 24
Peak memory 241160 kb
Host smart-bb6b0fcd-79f3-4590-8651-94900aca357a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816394587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1816394587
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.2412233413
Short name T1244
Test name
Test status
Simulation time 1462843806 ps
CPU time 18.56 seconds
Started Jan 21 10:13:26 PM PST 24
Finished Jan 21 10:13:48 PM PST 24
Peak memory 238780 kb
Host smart-8510fa1a-b356-4807-b131-9c7e23e18413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412233413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.2412233413
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2379439317
Short name T471
Test name
Test status
Simulation time 397627857 ps
CPU time 3.7 seconds
Started Jan 21 10:13:32 PM PST 24
Finished Jan 21 10:13:38 PM PST 24
Peak memory 240812 kb
Host smart-c5c71c67-37e4-4040-a1f7-baf01346eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379439317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2379439317
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.894467233
Short name T736
Test name
Test status
Simulation time 14140370969 ps
CPU time 151.07 seconds
Started Jan 21 10:13:38 PM PST 24
Finished Jan 21 10:16:13 PM PST 24
Peak memory 247088 kb
Host smart-d9b34257-ae89-4fd0-b60e-e81f33248ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894467233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.
894467233
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2401586298
Short name T983
Test name
Test status
Simulation time 513414583157 ps
CPU time 2494.14 seconds
Started Jan 21 10:13:36 PM PST 24
Finished Jan 21 10:55:12 PM PST 24
Peak memory 259864 kb
Host smart-2b135beb-a5b0-4013-94db-50d31522472f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401586298 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.2401586298
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1276138824
Short name T1120
Test name
Test status
Simulation time 1338736806 ps
CPU time 12.91 seconds
Started Jan 21 10:13:42 PM PST 24
Finished Jan 21 10:14:01 PM PST 24
Peak memory 238320 kb
Host smart-8977df52-ed13-4dce-a0ed-2846c677ef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276138824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1276138824
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.1128579011
Short name T489
Test name
Test status
Simulation time 112151346 ps
CPU time 4.41 seconds
Started Jan 21 10:19:35 PM PST 24
Finished Jan 21 10:19:43 PM PST 24
Peak memory 241364 kb
Host smart-a42fa495-e414-4509-b8b2-7a80051ffaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128579011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1128579011
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.741676301
Short name T682
Test name
Test status
Simulation time 244082039 ps
CPU time 3.34 seconds
Started Jan 21 10:32:50 PM PST 24
Finished Jan 21 10:33:01 PM PST 24
Peak memory 241416 kb
Host smart-955225a4-5448-4b68-91d6-0242d38b9385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741676301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.741676301
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.448453314
Short name T944
Test name
Test status
Simulation time 94220850 ps
CPU time 3.27 seconds
Started Jan 21 10:19:40 PM PST 24
Finished Jan 21 10:19:48 PM PST 24
Peak memory 241024 kb
Host smart-03b85daf-d8fe-48fd-bbdf-e9c3ab61e56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448453314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.448453314
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2998115373
Short name T444
Test name
Test status
Simulation time 184549653 ps
CPU time 4.47 seconds
Started Jan 21 10:19:42 PM PST 24
Finished Jan 21 10:19:50 PM PST 24
Peak memory 246852 kb
Host smart-d5f058d4-c79e-4a42-9538-8447d22f8d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998115373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2998115373
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1271027716
Short name T56
Test name
Test status
Simulation time 526648422 ps
CPU time 5.09 seconds
Started Jan 21 10:19:42 PM PST 24
Finished Jan 21 10:19:51 PM PST 24
Peak memory 241408 kb
Host smart-18cabf82-1701-46b8-8bd8-0598ac2d3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271027716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1271027716
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1230645845
Short name T948
Test name
Test status
Simulation time 1315914802 ps
CPU time 3.79 seconds
Started Jan 21 10:19:42 PM PST 24
Finished Jan 21 10:19:50 PM PST 24
Peak memory 238708 kb
Host smart-d3a350f6-bf57-42e1-898a-7a0922b8b0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230645845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1230645845
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.2495096362
Short name T486
Test name
Test status
Simulation time 209952724 ps
CPU time 3.83 seconds
Started Jan 21 10:19:44 PM PST 24
Finished Jan 21 10:19:51 PM PST 24
Peak memory 238760 kb
Host smart-bbd462ac-aae4-4c4d-bcc3-803a452ef778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495096362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2495096362
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3621092063
Short name T1192
Test name
Test status
Simulation time 115283746 ps
CPU time 2.72 seconds
Started Jan 21 10:19:41 PM PST 24
Finished Jan 21 10:19:48 PM PST 24
Peak memory 241668 kb
Host smart-42f10914-33f5-4e1c-a312-80888c15584c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621092063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3621092063
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.1991928674
Short name T521
Test name
Test status
Simulation time 2493330604 ps
CPU time 5.45 seconds
Started Jan 21 10:19:42 PM PST 24
Finished Jan 21 10:19:51 PM PST 24
Peak memory 238728 kb
Host smart-051e35fd-15b7-4feb-9f83-c23f02f4a89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991928674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.1991928674
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1194592254
Short name T743
Test name
Test status
Simulation time 792426483 ps
CPU time 5.18 seconds
Started Jan 21 10:19:40 PM PST 24
Finished Jan 21 10:19:50 PM PST 24
Peak memory 238776 kb
Host smart-4307fd54-e855-44b5-a7aa-b22c5d754fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194592254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1194592254
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.1895369002
Short name T549
Test name
Test status
Simulation time 234067220 ps
CPU time 3.81 seconds
Started Jan 21 10:19:41 PM PST 24
Finished Jan 21 10:19:49 PM PST 24
Peak memory 238776 kb
Host smart-8cb1ef84-b76e-4446-b40d-0de7866db2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895369002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1895369002
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.130642620
Short name T812
Test name
Test status
Simulation time 1981905044 ps
CPU time 6.16 seconds
Started Jan 21 10:19:52 PM PST 24
Finished Jan 21 10:20:05 PM PST 24
Peak memory 238724 kb
Host smart-633d0f56-9f79-45cf-adfb-cf100ac3cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130642620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.130642620
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.1305685107
Short name T991
Test name
Test status
Simulation time 102417446 ps
CPU time 3.76 seconds
Started Jan 21 10:19:49 PM PST 24
Finished Jan 21 10:19:59 PM PST 24
Peak memory 241336 kb
Host smart-5389f1f3-6f2b-46ee-92bb-50fdadf96d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305685107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.1305685107
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.3755115418
Short name T860
Test name
Test status
Simulation time 116989250 ps
CPU time 3.51 seconds
Started Jan 21 10:19:47 PM PST 24
Finished Jan 21 10:19:55 PM PST 24
Peak memory 238780 kb
Host smart-0d73573b-5c24-41f7-8f05-7d23010ede60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755115418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3755115418
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.1803935166
Short name T126
Test name
Test status
Simulation time 2447534183 ps
CPU time 4.4 seconds
Started Jan 21 10:19:55 PM PST 24
Finished Jan 21 10:20:12 PM PST 24
Peak memory 238796 kb
Host smart-1586b5c7-4416-48cc-9eb4-3c74b2dea233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803935166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1803935166
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.1037452309
Short name T1279
Test name
Test status
Simulation time 116210184 ps
CPU time 2.84 seconds
Started Jan 21 10:19:47 PM PST 24
Finished Jan 21 10:19:55 PM PST 24
Peak memory 241504 kb
Host smart-70d91500-333a-47c4-8ffe-9f5144ba7d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037452309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1037452309
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.716379956
Short name T646
Test name
Test status
Simulation time 616976189 ps
CPU time 5.39 seconds
Started Jan 21 11:20:07 PM PST 24
Finished Jan 21 11:20:14 PM PST 24
Peak memory 242836 kb
Host smart-c812b92f-90d3-4a69-a6e4-e2953cdb6daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716379956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.716379956
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.795809994
Short name T873
Test name
Test status
Simulation time 221048538 ps
CPU time 3.59 seconds
Started Jan 21 10:19:51 PM PST 24
Finished Jan 21 10:20:02 PM PST 24
Peak memory 238756 kb
Host smart-3dc61c88-be96-4d6b-9855-7cdfd1af3bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795809994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.795809994
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.890565324
Short name T1082
Test name
Test status
Simulation time 778223861 ps
CPU time 5.98 seconds
Started Jan 21 10:19:46 PM PST 24
Finished Jan 21 10:19:55 PM PST 24
Peak memory 242316 kb
Host smart-9eebb1cc-5beb-40b7-9bf3-988663aed552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890565324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.890565324
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.3849484185
Short name T1245
Test name
Test status
Simulation time 422643228 ps
CPU time 3.04 seconds
Started Jan 21 10:13:41 PM PST 24
Finished Jan 21 10:13:48 PM PST 24
Peak memory 239552 kb
Host smart-702485ff-e9df-43f8-ae9c-d5a3f3711289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849484185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3849484185
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.1790504202
Short name T998
Test name
Test status
Simulation time 525829385 ps
CPU time 13.12 seconds
Started Jan 21 10:13:41 PM PST 24
Finished Jan 21 10:13:58 PM PST 24
Peak memory 238676 kb
Host smart-da0d0d00-de4e-476e-a027-2abba2484c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790504202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1790504202
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.830632665
Short name T926
Test name
Test status
Simulation time 1854527609 ps
CPU time 11.68 seconds
Started Jan 21 10:13:37 PM PST 24
Finished Jan 21 10:13:51 PM PST 24
Peak memory 246908 kb
Host smart-3247d2cf-da19-4285-a495-2bfef74a17dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830632665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.830632665
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.4110436260
Short name T1188
Test name
Test status
Simulation time 1459007564 ps
CPU time 21.3 seconds
Started Jan 21 10:13:38 PM PST 24
Finished Jan 21 10:14:03 PM PST 24
Peak memory 238728 kb
Host smart-10afa96c-9f49-4034-8c3f-22e819954cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110436260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.4110436260
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3685010816
Short name T1240
Test name
Test status
Simulation time 1445775310 ps
CPU time 4.12 seconds
Started Jan 21 10:13:34 PM PST 24
Finished Jan 21 10:13:40 PM PST 24
Peak memory 238732 kb
Host smart-0668f09b-f0d2-4c51-95fb-4364767fc013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685010816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3685010816
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1656611254
Short name T1163
Test name
Test status
Simulation time 11963995534 ps
CPU time 22.82 seconds
Started Jan 21 10:13:40 PM PST 24
Finished Jan 21 10:14:07 PM PST 24
Peak memory 238956 kb
Host smart-935e41db-9b3d-43fc-aed1-f9881c79eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656611254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1656611254
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.47751681
Short name T1259
Test name
Test status
Simulation time 796203778 ps
CPU time 12.89 seconds
Started Jan 21 10:13:38 PM PST 24
Finished Jan 21 10:13:54 PM PST 24
Peak memory 238752 kb
Host smart-8749599d-1cf5-40f2-a009-319c68dc4a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47751681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.47751681
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.670736451
Short name T1069
Test name
Test status
Simulation time 3734404460 ps
CPU time 11.32 seconds
Started Jan 21 10:13:42 PM PST 24
Finished Jan 21 10:13:58 PM PST 24
Peak memory 245104 kb
Host smart-ef19e4d3-888b-4d67-83c1-11c7436fc8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670736451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.670736451
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.697730149
Short name T668
Test name
Test status
Simulation time 883945136 ps
CPU time 16.43 seconds
Started Jan 21 10:13:40 PM PST 24
Finished Jan 21 10:14:01 PM PST 24
Peak memory 238752 kb
Host smart-5c80ae25-6cab-47e6-8793-371b60b8b93b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697730149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.697730149
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.3211581761
Short name T239
Test name
Test status
Simulation time 1672100625 ps
CPU time 5.59 seconds
Started Jan 21 10:13:41 PM PST 24
Finished Jan 21 10:13:51 PM PST 24
Peak memory 243648 kb
Host smart-c2bf3322-628e-45ab-8c1b-4ad143d0938b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211581761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3211581761
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.925386841
Short name T505
Test name
Test status
Simulation time 172313475 ps
CPU time 4.44 seconds
Started Jan 21 10:13:42 PM PST 24
Finished Jan 21 10:13:53 PM PST 24
Peak memory 244916 kb
Host smart-b9fe2746-aa04-450f-885c-a97b1702c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925386841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.925386841
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.2196666280
Short name T1154
Test name
Test status
Simulation time 3302577152 ps
CPU time 60.94 seconds
Started Jan 21 10:32:53 PM PST 24
Finished Jan 21 10:34:00 PM PST 24
Peak memory 247136 kb
Host smart-ca2112ca-b9fb-4ef8-b850-69d1b72cf47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196666280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.2196666280
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.3491130950
Short name T1003
Test name
Test status
Simulation time 39998916442 ps
CPU time 464.83 seconds
Started Jan 21 10:13:42 PM PST 24
Finished Jan 21 10:21:33 PM PST 24
Peak memory 278292 kb
Host smart-7d0dccbe-d8e6-45e8-9926-44d139cfd038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491130950 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.3491130950
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.2461768650
Short name T476
Test name
Test status
Simulation time 240760001 ps
CPU time 3.23 seconds
Started Jan 21 10:13:42 PM PST 24
Finished Jan 21 10:13:50 PM PST 24
Peak memory 241492 kb
Host smart-aacefa78-ea67-4c67-854c-0754b98eac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461768650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.2461768650
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.3793974911
Short name T653
Test name
Test status
Simulation time 598923113 ps
CPU time 4.77 seconds
Started Jan 21 10:19:49 PM PST 24
Finished Jan 21 10:20:01 PM PST 24
Peak memory 238692 kb
Host smart-a16bfe3d-c98a-4a2e-9c65-b4553ae693ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793974911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3793974911
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.2378064132
Short name T977
Test name
Test status
Simulation time 254693864 ps
CPU time 6.17 seconds
Started Jan 21 10:19:52 PM PST 24
Finished Jan 21 10:20:05 PM PST 24
Peak memory 238768 kb
Host smart-60588e91-8de6-440e-9ab8-4b02aef12772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378064132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.2378064132
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3728688883
Short name T997
Test name
Test status
Simulation time 1761948617 ps
CPU time 7.3 seconds
Started Jan 21 10:19:53 PM PST 24
Finished Jan 21 10:20:06 PM PST 24
Peak memory 238720 kb
Host smart-77c972ed-cb21-4f15-b55f-545f994e4de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728688883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3728688883
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.638300615
Short name T522
Test name
Test status
Simulation time 255552652 ps
CPU time 3.55 seconds
Started Jan 21 10:19:55 PM PST 24
Finished Jan 21 10:20:11 PM PST 24
Peak memory 238696 kb
Host smart-03ea4542-fa1a-4ea6-abe1-1540bf3420b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638300615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.638300615
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.856970246
Short name T683
Test name
Test status
Simulation time 360907765 ps
CPU time 5.34 seconds
Started Jan 21 10:19:48 PM PST 24
Finished Jan 21 10:20:00 PM PST 24
Peak memory 238740 kb
Host smart-9f67a11d-839d-4354-9f59-411843040e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856970246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.856970246
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.1286467050
Short name T772
Test name
Test status
Simulation time 616556652 ps
CPU time 4.95 seconds
Started Jan 21 10:19:54 PM PST 24
Finished Jan 21 10:20:11 PM PST 24
Peak memory 242980 kb
Host smart-12627535-cd9d-48ef-afbb-3160ed5aeeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286467050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1286467050
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.736254228
Short name T61
Test name
Test status
Simulation time 296526709 ps
CPU time 3.54 seconds
Started Jan 21 10:19:58 PM PST 24
Finished Jan 21 10:20:13 PM PST 24
Peak memory 240752 kb
Host smart-618714c7-dc7f-4084-b28d-32a5f8e378ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736254228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.736254228
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1141505003
Short name T92
Test name
Test status
Simulation time 2504610318 ps
CPU time 10.99 seconds
Started Jan 21 10:19:55 PM PST 24
Finished Jan 21 10:20:18 PM PST 24
Peak memory 238860 kb
Host smart-c4b2f59e-49bb-4811-a6ed-03656aa5e239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141505003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1141505003
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.1385243154
Short name T568
Test name
Test status
Simulation time 266337820 ps
CPU time 4.45 seconds
Started Jan 21 10:19:54 PM PST 24
Finished Jan 21 10:20:10 PM PST 24
Peak memory 238744 kb
Host smart-b95edecd-2652-4662-a9d4-58542d790aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385243154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1385243154
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.519239568
Short name T624
Test name
Test status
Simulation time 302416948 ps
CPU time 4.68 seconds
Started Jan 21 10:19:57 PM PST 24
Finished Jan 21 10:20:13 PM PST 24
Peak memory 242604 kb
Host smart-269fa88c-1fe5-4514-a7da-52927c34d85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519239568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.519239568
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.1167893766
Short name T514
Test name
Test status
Simulation time 353604740 ps
CPU time 4.28 seconds
Started Jan 21 10:19:57 PM PST 24
Finished Jan 21 10:20:12 PM PST 24
Peak memory 238656 kb
Host smart-1d6fa8ee-3dd6-4fda-8799-779d30ed84c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167893766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1167893766
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3824495397
Short name T669
Test name
Test status
Simulation time 1482828464 ps
CPU time 10.31 seconds
Started Jan 21 10:19:57 PM PST 24
Finished Jan 21 10:20:19 PM PST 24
Peak memory 245356 kb
Host smart-0edfd817-ed5f-4074-b034-1f2c36c336cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824495397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3824495397
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3114310057
Short name T722
Test name
Test status
Simulation time 164387822 ps
CPU time 4.21 seconds
Started Jan 21 10:19:55 PM PST 24
Finished Jan 21 10:20:11 PM PST 24
Peak memory 238772 kb
Host smart-b5527a00-a17a-420b-9cbd-c3f7aa1a4bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114310057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3114310057
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.3818782034
Short name T464
Test name
Test status
Simulation time 457375227 ps
CPU time 6.44 seconds
Started Jan 21 10:19:57 PM PST 24
Finished Jan 21 10:20:15 PM PST 24
Peak memory 243520 kb
Host smart-fd7565c5-a216-476f-b6b3-a1db01b41adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818782034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3818782034
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.3205705612
Short name T758
Test name
Test status
Simulation time 225763050 ps
CPU time 4.56 seconds
Started Jan 21 10:19:57 PM PST 24
Finished Jan 21 10:20:13 PM PST 24
Peak memory 238664 kb
Host smart-058b6d7d-f441-44ba-8b20-bda0fd7f89bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205705612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.3205705612
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.2375056344
Short name T205
Test name
Test status
Simulation time 323591137 ps
CPU time 4.56 seconds
Started Jan 21 10:19:54 PM PST 24
Finished Jan 21 10:20:10 PM PST 24
Peak memory 241272 kb
Host smart-c14318b3-c177-4ee7-a770-364217eaf999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375056344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2375056344
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.2914909485
Short name T43
Test name
Test status
Simulation time 256386348 ps
CPU time 3.42 seconds
Started Jan 21 10:20:01 PM PST 24
Finished Jan 21 10:20:14 PM PST 24
Peak memory 238788 kb
Host smart-62d36293-e176-4169-b232-27e14334ef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914909485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2914909485
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3245576776
Short name T1136
Test name
Test status
Simulation time 1219856021 ps
CPU time 4.08 seconds
Started Jan 21 10:19:57 PM PST 24
Finished Jan 21 10:20:13 PM PST 24
Peak memory 238772 kb
Host smart-99356c20-2998-424b-a328-715b6f754a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245576776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3245576776
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.1611747136
Short name T42
Test name
Test status
Simulation time 222741557 ps
CPU time 4.47 seconds
Started Jan 21 10:19:55 PM PST 24
Finished Jan 21 10:20:12 PM PST 24
Peak memory 238960 kb
Host smart-677ca27d-f039-4818-a1c8-0b36e37924a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611747136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1611747136
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.2226191883
Short name T867
Test name
Test status
Simulation time 1043699380 ps
CPU time 3.68 seconds
Started Jan 21 10:20:03 PM PST 24
Finished Jan 21 10:20:15 PM PST 24
Peak memory 241048 kb
Host smart-cb8011f6-41db-4b17-b205-025501b342b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226191883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.2226191883
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.856610098
Short name T649
Test name
Test status
Simulation time 263811122 ps
CPU time 1.93 seconds
Started Jan 21 10:13:45 PM PST 24
Finished Jan 21 10:13:54 PM PST 24
Peak memory 239652 kb
Host smart-bfd48bc7-2714-40c4-ba22-0e365f4f9145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856610098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.856610098
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1872984186
Short name T300
Test name
Test status
Simulation time 386162025 ps
CPU time 4.24 seconds
Started Jan 21 10:13:47 PM PST 24
Finished Jan 21 10:13:58 PM PST 24
Peak memory 243340 kb
Host smart-4c26c333-1364-4b35-86a5-00263b3221f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872984186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1872984186
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.3516069384
Short name T1126
Test name
Test status
Simulation time 167217734 ps
CPU time 4.69 seconds
Started Jan 21 10:13:47 PM PST 24
Finished Jan 21 10:13:59 PM PST 24
Peak memory 242600 kb
Host smart-56d3bfa9-def6-45d6-9ba3-c613a2a51428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516069384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.3516069384
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.2512029513
Short name T731
Test name
Test status
Simulation time 1299869533 ps
CPU time 15.07 seconds
Started Jan 21 10:13:50 PM PST 24
Finished Jan 21 10:14:10 PM PST 24
Peak memory 238852 kb
Host smart-fc08b863-d7aa-48d6-8e08-921fcabbcdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512029513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.2512029513
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1503040682
Short name T639
Test name
Test status
Simulation time 257497930 ps
CPU time 2.75 seconds
Started Jan 21 10:13:45 PM PST 24
Finished Jan 21 10:13:55 PM PST 24
Peak memory 243728 kb
Host smart-cc25a75e-5292-4037-80be-74b7187e9b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503040682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1503040682
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.3825498523
Short name T798
Test name
Test status
Simulation time 196895477 ps
CPU time 2.71 seconds
Started Jan 21 10:50:07 PM PST 24
Finished Jan 21 10:50:12 PM PST 24
Peak memory 242184 kb
Host smart-9e7af3d9-d304-45bf-a8e5-2e5f2598a1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825498523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3825498523
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.1427943317
Short name T1248
Test name
Test status
Simulation time 409976880 ps
CPU time 11.08 seconds
Started Jan 21 10:13:45 PM PST 24
Finished Jan 21 10:14:03 PM PST 24
Peak memory 238728 kb
Host smart-5afb3ac2-2b20-464b-94cf-ec110c75e6c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427943317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.1427943317
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.120494083
Short name T992
Test name
Test status
Simulation time 322196505 ps
CPU time 9.21 seconds
Started Jan 21 10:13:46 PM PST 24
Finished Jan 21 10:14:02 PM PST 24
Peak memory 245880 kb
Host smart-42034e70-4851-48be-b2da-6a8bb516f4e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120494083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.120494083
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.78170618
Short name T795
Test name
Test status
Simulation time 421546680 ps
CPU time 6.21 seconds
Started Jan 21 11:11:30 PM PST 24
Finished Jan 21 11:11:37 PM PST 24
Peak memory 238772 kb
Host smart-5909bb0c-395c-467b-beca-4f836cc27d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78170618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.78170618
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.1742332905
Short name T1006
Test name
Test status
Simulation time 8228952150 ps
CPU time 77.02 seconds
Started Jan 21 10:13:45 PM PST 24
Finished Jan 21 10:15:09 PM PST 24
Peak memory 247108 kb
Host smart-837ebe19-d237-48b9-bf55-7525745f10ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742332905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.1742332905
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.2165787343
Short name T267
Test name
Test status
Simulation time 381433513199 ps
CPU time 5345.56 seconds
Started Jan 21 10:13:47 PM PST 24
Finished Jan 21 11:43:00 PM PST 24
Peak memory 707988 kb
Host smart-4e648ddc-0531-4244-acf9-763a2080d20a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165787343 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.2165787343
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.4196802487
Short name T1174
Test name
Test status
Simulation time 1108134764 ps
CPU time 12.24 seconds
Started Jan 21 10:13:46 PM PST 24
Finished Jan 21 10:14:05 PM PST 24
Peak memory 243584 kb
Host smart-b67a7676-0b84-441e-b675-3842adb6f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196802487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.4196802487
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.3123893126
Short name T988
Test name
Test status
Simulation time 2333096231 ps
CPU time 4.04 seconds
Started Jan 21 10:20:08 PM PST 24
Finished Jan 21 10:20:18 PM PST 24
Peak memory 238772 kb
Host smart-41b38a1e-4511-4041-ae51-93a392dffa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123893126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.3123893126
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.94980652
Short name T966
Test name
Test status
Simulation time 159645943 ps
CPU time 3.08 seconds
Started Jan 21 10:20:10 PM PST 24
Finished Jan 21 10:20:19 PM PST 24
Peak memory 238736 kb
Host smart-8107217d-be47-4c39-9a35-fbb753bba641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94980652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.94980652
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1813706445
Short name T559
Test name
Test status
Simulation time 154899961 ps
CPU time 4.24 seconds
Started Jan 21 10:20:08 PM PST 24
Finished Jan 21 10:20:18 PM PST 24
Peak memory 238736 kb
Host smart-0760d8fd-728f-4c7d-a62c-a735f56eb697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813706445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1813706445
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.528578821
Short name T1199
Test name
Test status
Simulation time 303959398 ps
CPU time 7.9 seconds
Started Jan 21 10:20:05 PM PST 24
Finished Jan 21 10:20:20 PM PST 24
Peak memory 238976 kb
Host smart-bd53e26c-9b63-4151-b767-52eafa33e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528578821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.528578821
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2025804144
Short name T1125
Test name
Test status
Simulation time 385511765 ps
CPU time 4.35 seconds
Started Jan 21 10:20:06 PM PST 24
Finished Jan 21 10:20:17 PM PST 24
Peak memory 240760 kb
Host smart-cc50e78d-04ad-49cb-94ec-a5a9d4e4f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025804144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2025804144
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.1784218458
Short name T811
Test name
Test status
Simulation time 395012341 ps
CPU time 6.09 seconds
Started Jan 21 10:20:08 PM PST 24
Finished Jan 21 10:20:21 PM PST 24
Peak memory 238848 kb
Host smart-77a750a3-645e-4f32-bc3c-f527956de157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784218458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1784218458
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.3547300039
Short name T490
Test name
Test status
Simulation time 448689786 ps
CPU time 3.97 seconds
Started Jan 21 10:20:09 PM PST 24
Finished Jan 21 10:20:19 PM PST 24
Peak memory 241136 kb
Host smart-87e048cd-b910-4576-9e2a-8517e9364f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547300039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3547300039
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.1688554249
Short name T1143
Test name
Test status
Simulation time 144365228 ps
CPU time 5.32 seconds
Started Jan 21 10:20:07 PM PST 24
Finished Jan 21 10:20:18 PM PST 24
Peak memory 238684 kb
Host smart-db46afe1-e758-4cb1-b5fe-c1efa3cf0495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688554249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1688554249
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.4293677751
Short name T449
Test name
Test status
Simulation time 1801143740 ps
CPU time 5.95 seconds
Started Jan 21 10:20:03 PM PST 24
Finished Jan 21 10:20:17 PM PST 24
Peak memory 238772 kb
Host smart-5f15a1c9-ec5c-47e9-9dba-08bb2699365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293677751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.4293677751
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.4113627082
Short name T974
Test name
Test status
Simulation time 149543278 ps
CPU time 4.3 seconds
Started Jan 21 10:20:09 PM PST 24
Finished Jan 21 10:20:20 PM PST 24
Peak memory 238916 kb
Host smart-c646f095-c22a-4719-9b94-deeee4ec176e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113627082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.4113627082
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3356588970
Short name T1243
Test name
Test status
Simulation time 806501306 ps
CPU time 10.17 seconds
Started Jan 21 10:20:08 PM PST 24
Finished Jan 21 10:20:25 PM PST 24
Peak memory 243708 kb
Host smart-8b450093-9612-4585-b6c0-3ef72c5263f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356588970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3356588970
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1831407262
Short name T127
Test name
Test status
Simulation time 461562280 ps
CPU time 4.04 seconds
Started Jan 21 10:20:21 PM PST 24
Finished Jan 21 10:20:31 PM PST 24
Peak memory 238684 kb
Host smart-d3673352-09a1-47cf-adf4-23f027d91b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831407262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1831407262
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.432520351
Short name T525
Test name
Test status
Simulation time 132436163 ps
CPU time 2.29 seconds
Started Jan 21 10:20:11 PM PST 24
Finished Jan 21 10:20:20 PM PST 24
Peak memory 240780 kb
Host smart-c5d3d414-7fd3-48ca-a45d-ed21e801d151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432520351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.432520351
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.1756786067
Short name T853
Test name
Test status
Simulation time 2503259203 ps
CPU time 6.08 seconds
Started Jan 21 10:20:15 PM PST 24
Finished Jan 21 10:20:29 PM PST 24
Peak memory 238832 kb
Host smart-1e326cfd-f5a3-4969-b0cc-eadf216ca7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756786067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.1756786067
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1011054061
Short name T1296
Test name
Test status
Simulation time 364100718 ps
CPU time 7.27 seconds
Started Jan 21 10:20:13 PM PST 24
Finished Jan 21 10:20:28 PM PST 24
Peak memory 242616 kb
Host smart-f5702130-ea47-46db-9d83-ee2da257fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011054061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1011054061
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.3035585348
Short name T162
Test name
Test status
Simulation time 269738595 ps
CPU time 4.38 seconds
Started Jan 21 10:20:14 PM PST 24
Finished Jan 21 10:20:27 PM PST 24
Peak memory 240760 kb
Host smart-69a8e201-db60-4a31-a882-dfd4dd6e78d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035585348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.3035585348
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2348671732
Short name T621
Test name
Test status
Simulation time 219564099 ps
CPU time 6.35 seconds
Started Jan 21 10:20:13 PM PST 24
Finished Jan 21 10:20:28 PM PST 24
Peak memory 238808 kb
Host smart-30634199-8e30-4505-a972-8bcfb6c88e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348671732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2348671732
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1839711805
Short name T85
Test name
Test status
Simulation time 848219505 ps
CPU time 6.39 seconds
Started Jan 21 10:20:11 PM PST 24
Finished Jan 21 10:20:24 PM PST 24
Peak memory 243500 kb
Host smart-4b64e2d8-3599-40b0-8346-0b873ffda413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839711805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1839711805
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.3871112975
Short name T155
Test name
Test status
Simulation time 605150642 ps
CPU time 2 seconds
Started Jan 21 10:11:50 PM PST 24
Finished Jan 21 10:11:55 PM PST 24
Peak memory 230456 kb
Host smart-bd204ae7-d437-4682-a244-19103e836c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871112975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.3871112975
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.1973292062
Short name T680
Test name
Test status
Simulation time 356380979 ps
CPU time 2.77 seconds
Started Jan 21 10:11:37 PM PST 24
Finished Jan 21 10:11:41 PM PST 24
Peak memory 246944 kb
Host smart-17be497c-4b7d-41c7-b54f-d7f64ac98e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973292062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1973292062
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3120785039
Short name T739
Test name
Test status
Simulation time 1412459080 ps
CPU time 8.98 seconds
Started Jan 21 10:11:48 PM PST 24
Finished Jan 21 10:12:00 PM PST 24
Peak memory 238740 kb
Host smart-26917519-7475-41f3-b6ec-3adf257587ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120785039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3120785039
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.564951587
Short name T524
Test name
Test status
Simulation time 224537468 ps
CPU time 9.77 seconds
Started Jan 21 10:11:40 PM PST 24
Finished Jan 21 10:11:52 PM PST 24
Peak memory 244776 kb
Host smart-0295c08d-8241-43d9-9423-db410015ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564951587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.564951587
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.59698902
Short name T355
Test name
Test status
Simulation time 994826644 ps
CPU time 10.29 seconds
Started Jan 21 10:11:40 PM PST 24
Finished Jan 21 10:11:52 PM PST 24
Peak memory 238792 kb
Host smart-925daa93-dbcc-4d11-b4fb-615625d4409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59698902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.59698902
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.952241473
Short name T51
Test name
Test status
Simulation time 639089791 ps
CPU time 4.47 seconds
Started Jan 21 10:11:42 PM PST 24
Finished Jan 21 10:11:49 PM PST 24
Peak memory 238736 kb
Host smart-a46889f0-9044-4a71-9448-c9789e80f35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952241473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.952241473
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.509443341
Short name T849
Test name
Test status
Simulation time 376550987 ps
CPU time 3.85 seconds
Started Jan 21 10:11:51 PM PST 24
Finished Jan 21 10:11:58 PM PST 24
Peak memory 243860 kb
Host smart-4ac44f5c-7f43-40b6-a55a-1e69937cae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509443341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.509443341
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.574997330
Short name T202
Test name
Test status
Simulation time 216221515 ps
CPU time 4.93 seconds
Started Jan 21 10:11:48 PM PST 24
Finished Jan 21 10:11:55 PM PST 24
Peak memory 238772 kb
Host smart-da5b3d60-ad22-416f-9199-8732b0d04111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574997330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.574997330
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2985474239
Short name T556
Test name
Test status
Simulation time 130420554 ps
CPU time 4.86 seconds
Started Jan 21 10:11:39 PM PST 24
Finished Jan 21 10:11:46 PM PST 24
Peak memory 238704 kb
Host smart-737f34ba-5659-4201-a6ea-51e006bcfb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985474239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2985474239
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.303185886
Short name T1275
Test name
Test status
Simulation time 1041310812 ps
CPU time 19.29 seconds
Started Jan 21 10:11:44 PM PST 24
Finished Jan 21 10:12:05 PM PST 24
Peak memory 242628 kb
Host smart-c5085bf1-c8c1-4eb3-81c3-4c215b840b5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303185886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.303185886
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.4269670937
Short name T953
Test name
Test status
Simulation time 301579938 ps
CPU time 6.99 seconds
Started Jan 21 10:11:55 PM PST 24
Finished Jan 21 10:12:04 PM PST 24
Peak memory 244084 kb
Host smart-e18b7fd7-2611-4af3-b8c0-ad7cfaa003f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4269670937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.4269670937
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3493465442
Short name T220
Test name
Test status
Simulation time 32979730976 ps
CPU time 152.8 seconds
Started Jan 21 10:11:50 PM PST 24
Finished Jan 21 10:14:26 PM PST 24
Peak memory 267720 kb
Host smart-0b835292-102e-4fba-a6cb-f126c19d8039
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493465442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3493465442
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1715004937
Short name T1046
Test name
Test status
Simulation time 230421552 ps
CPU time 5.71 seconds
Started Jan 21 10:11:44 PM PST 24
Finished Jan 21 10:11:52 PM PST 24
Peak memory 243460 kb
Host smart-7f1f0ee9-b556-43e7-ad05-fbc6d5b5a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715004937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1715004937
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.4089091397
Short name T1239
Test name
Test status
Simulation time 685958626715 ps
CPU time 5162.96 seconds
Started Jan 21 10:11:49 PM PST 24
Finished Jan 21 11:37:55 PM PST 24
Peak memory 303176 kb
Host smart-f4b61ce0-7442-4c55-8e0d-a66b60920986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089091397 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.4089091397
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.1306126354
Short name T814
Test name
Test status
Simulation time 1942111665 ps
CPU time 16.88 seconds
Started Jan 21 10:11:53 PM PST 24
Finished Jan 21 10:12:12 PM PST 24
Peak memory 238784 kb
Host smart-0186db1a-a723-486c-9743-74aa1b2821d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306126354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.1306126354
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.482230837
Short name T8
Test name
Test status
Simulation time 163459511 ps
CPU time 2.22 seconds
Started Jan 21 10:14:02 PM PST 24
Finished Jan 21 10:14:07 PM PST 24
Peak memory 239676 kb
Host smart-fb5f9f7f-efaa-4c01-a059-ced2cb6dcbc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482230837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.482230837
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.2995740903
Short name T228
Test name
Test status
Simulation time 2546764944 ps
CPU time 6.21 seconds
Started Jan 21 10:13:51 PM PST 24
Finished Jan 21 10:14:02 PM PST 24
Peak memory 238816 kb
Host smart-82869229-2d93-4d9f-8823-285b5799e60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995740903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2995740903
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.129397271
Short name T214
Test name
Test status
Simulation time 1017575301 ps
CPU time 8.85 seconds
Started Jan 21 10:13:49 PM PST 24
Finished Jan 21 10:14:04 PM PST 24
Peak memory 245500 kb
Host smart-4359d913-f2bd-4baf-99a1-2d7cac693957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129397271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.129397271
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3297545043
Short name T734
Test name
Test status
Simulation time 776145624 ps
CPU time 11.44 seconds
Started Jan 21 10:13:56 PM PST 24
Finished Jan 21 10:14:09 PM PST 24
Peak memory 246936 kb
Host smart-b1529f34-1a35-41e2-81fc-a3ab98a5b047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297545043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3297545043
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2753400421
Short name T1271
Test name
Test status
Simulation time 508386123 ps
CPU time 4.8 seconds
Started Jan 21 10:13:50 PM PST 24
Finished Jan 21 10:14:00 PM PST 24
Peak memory 240892 kb
Host smart-416abca6-71af-4d0f-b7be-bff6917df663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753400421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2753400421
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3969403724
Short name T307
Test name
Test status
Simulation time 16084358653 ps
CPU time 25.47 seconds
Started Jan 21 10:14:02 PM PST 24
Finished Jan 21 10:14:31 PM PST 24
Peak memory 242216 kb
Host smart-05099d2b-66f7-4507-985b-f98c51cc7166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969403724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3969403724
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2727596253
Short name T1065
Test name
Test status
Simulation time 345227870 ps
CPU time 9.3 seconds
Started Jan 21 10:13:50 PM PST 24
Finished Jan 21 10:14:05 PM PST 24
Peak memory 244092 kb
Host smart-3623b180-aaaa-4a63-bf70-ec9957454d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727596253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2727596253
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.4268310559
Short name T313
Test name
Test status
Simulation time 118210436 ps
CPU time 4.26 seconds
Started Jan 21 10:14:02 PM PST 24
Finished Jan 21 10:14:09 PM PST 24
Peak memory 246884 kb
Host smart-9d0212f5-f493-48de-8c6b-1466d501f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268310559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.4268310559
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.1774112503
Short name T837
Test name
Test status
Simulation time 1037270041 ps
CPU time 20.2 seconds
Started Jan 21 10:13:54 PM PST 24
Finished Jan 21 10:14:17 PM PST 24
Peak memory 244496 kb
Host smart-972de259-6b3b-437d-bce9-5c31f6ee03ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774112503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.1774112503
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.1136578936
Short name T773
Test name
Test status
Simulation time 172150922 ps
CPU time 4.17 seconds
Started Jan 21 11:06:51 PM PST 24
Finished Jan 21 11:06:59 PM PST 24
Peak memory 241796 kb
Host smart-80cffffc-ce24-4cba-8f5c-eab33e436a58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136578936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1136578936
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.4173169599
Short name T910
Test name
Test status
Simulation time 1843316678 ps
CPU time 9.15 seconds
Started Jan 21 10:33:51 PM PST 24
Finished Jan 21 10:34:01 PM PST 24
Peak memory 238760 kb
Host smart-414f9e7e-22fd-47dc-98e3-86532e50b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173169599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.4173169599
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.285514189
Short name T1169
Test name
Test status
Simulation time 15355244546 ps
CPU time 157.53 seconds
Started Jan 21 10:45:30 PM PST 24
Finished Jan 21 10:48:10 PM PST 24
Peak memory 255328 kb
Host smart-c2790288-2edf-4e70-908b-e5e291ddfeeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285514189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.
285514189
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1662258521
Short name T277
Test name
Test status
Simulation time 4148626634741 ps
CPU time 10687.5 seconds
Started Jan 21 10:13:50 PM PST 24
Finished Jan 22 01:12:04 AM PST 24
Peak memory 301836 kb
Host smart-48d3112a-fbf1-4993-b2a2-bf13ebf610f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662258521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1662258521
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1618365268
Short name T544
Test name
Test status
Simulation time 2492410248 ps
CPU time 15.09 seconds
Started Jan 21 10:13:51 PM PST 24
Finished Jan 21 10:14:11 PM PST 24
Peak memory 247116 kb
Host smart-34b49c22-43a6-4a47-846f-ffea7947c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618365268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1618365268
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3004613792
Short name T854
Test name
Test status
Simulation time 557211616 ps
CPU time 3.62 seconds
Started Jan 21 10:20:11 PM PST 24
Finished Jan 21 10:20:21 PM PST 24
Peak memory 238700 kb
Host smart-ea3a265a-6a04-4dcc-9d13-ca19082de21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004613792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3004613792
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.3836689811
Short name T1282
Test name
Test status
Simulation time 490907737 ps
CPU time 5.38 seconds
Started Jan 21 10:20:22 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 240704 kb
Host smart-c655ec33-75a2-489b-97bd-67c52e79c5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836689811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3836689811
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.2294459790
Short name T1072
Test name
Test status
Simulation time 593006950 ps
CPU time 3.91 seconds
Started Jan 21 10:20:13 PM PST 24
Finished Jan 21 10:20:25 PM PST 24
Peak memory 238716 kb
Host smart-c7c0c047-f4e7-4300-8f69-27202be0e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294459790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.2294459790
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.1334562223
Short name T1274
Test name
Test status
Simulation time 684278142 ps
CPU time 4.79 seconds
Started Jan 21 10:20:22 PM PST 24
Finished Jan 21 10:20:32 PM PST 24
Peak memory 238576 kb
Host smart-212020ec-bc56-4cda-bedd-8d930d465354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334562223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1334562223
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.3835054202
Short name T1119
Test name
Test status
Simulation time 132467714 ps
CPU time 3.26 seconds
Started Jan 21 10:20:15 PM PST 24
Finished Jan 21 10:20:26 PM PST 24
Peak memory 238612 kb
Host smart-02e65cfc-cdf9-4241-8794-74c5f3cad996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835054202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3835054202
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.1382118163
Short name T780
Test name
Test status
Simulation time 349127387 ps
CPU time 4.36 seconds
Started Jan 21 10:20:15 PM PST 24
Finished Jan 21 10:20:27 PM PST 24
Peak memory 238712 kb
Host smart-518a5cbf-3301-471b-8c86-59922681404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382118163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1382118163
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.2881662292
Short name T972
Test name
Test status
Simulation time 154928053 ps
CPU time 4.06 seconds
Started Jan 21 10:20:15 PM PST 24
Finished Jan 21 10:20:27 PM PST 24
Peak memory 246940 kb
Host smart-844e2bf7-9923-430e-9e6d-694e7d133fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881662292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2881662292
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.3482442540
Short name T659
Test name
Test status
Simulation time 508876820 ps
CPU time 4.81 seconds
Started Jan 21 10:20:22 PM PST 24
Finished Jan 21 10:20:32 PM PST 24
Peak memory 238660 kb
Host smart-a0d8e566-bccc-43e8-b6f9-8ca06156251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482442540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.3482442540
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3689029745
Short name T24
Test name
Test status
Simulation time 231669265 ps
CPU time 3.65 seconds
Started Jan 21 10:20:26 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 241428 kb
Host smart-28ae2b9c-4998-471c-93f3-22f54d313e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689029745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3689029745
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.4066440063
Short name T1150
Test name
Test status
Simulation time 41241979 ps
CPU time 1.47 seconds
Started Jan 21 10:14:00 PM PST 24
Finished Jan 21 10:14:05 PM PST 24
Peak memory 230264 kb
Host smart-e3c135c6-495e-4d4d-ac32-31f14863e0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066440063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.4066440063
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.3089261607
Short name T64
Test name
Test status
Simulation time 1323508496 ps
CPU time 15.29 seconds
Started Jan 21 10:14:02 PM PST 24
Finished Jan 21 10:14:20 PM PST 24
Peak memory 238836 kb
Host smart-bb1e7d4d-0875-4818-8b9e-ad3e36d58bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089261607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3089261607
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.1545160425
Short name T803
Test name
Test status
Simulation time 2732255170 ps
CPU time 9.49 seconds
Started Jan 21 10:14:04 PM PST 24
Finished Jan 21 10:14:19 PM PST 24
Peak memory 244168 kb
Host smart-79b70c1d-9560-4581-bc6b-40f63c261192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545160425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.1545160425
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1434259049
Short name T1254
Test name
Test status
Simulation time 894073838 ps
CPU time 9.61 seconds
Started Jan 21 10:14:00 PM PST 24
Finished Jan 21 10:14:13 PM PST 24
Peak memory 238776 kb
Host smart-0c7cce4b-01a0-4c8b-be84-14c6081e04dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434259049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1434259049
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1803108506
Short name T86
Test name
Test status
Simulation time 125493995 ps
CPU time 4.16 seconds
Started Jan 21 10:50:00 PM PST 24
Finished Jan 21 10:50:06 PM PST 24
Peak memory 241456 kb
Host smart-0ed64035-e9ea-40b4-9378-4950c9faff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803108506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1803108506
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.1844500264
Short name T869
Test name
Test status
Simulation time 8615707187 ps
CPU time 16.52 seconds
Started Jan 21 10:14:03 PM PST 24
Finished Jan 21 10:14:25 PM PST 24
Peak memory 238876 kb
Host smart-c7bb0b8b-c2a4-440e-9c7b-bc53953d4b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844500264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1844500264
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.2974162858
Short name T366
Test name
Test status
Simulation time 565123722 ps
CPU time 8.27 seconds
Started Jan 21 10:30:38 PM PST 24
Finished Jan 21 10:30:52 PM PST 24
Peak memory 238740 kb
Host smart-9448732b-f4e6-41ee-8603-4d654142889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974162858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2974162858
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.2960396502
Short name T1087
Test name
Test status
Simulation time 206871006 ps
CPU time 4.62 seconds
Started Jan 21 10:14:01 PM PST 24
Finished Jan 21 10:14:08 PM PST 24
Peak memory 241364 kb
Host smart-1b50f9c0-75ef-4b00-8a6d-072a0a3eb55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960396502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.2960396502
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.2657617752
Short name T1016
Test name
Test status
Simulation time 267069207 ps
CPU time 7.21 seconds
Started Jan 21 10:13:56 PM PST 24
Finished Jan 21 10:14:05 PM PST 24
Peak memory 243016 kb
Host smart-fe4c1710-224d-4d86-b6c4-b552a6a162ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657617752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2657617752
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1135899559
Short name T330
Test name
Test status
Simulation time 913100049 ps
CPU time 8.33 seconds
Started Jan 21 10:14:05 PM PST 24
Finished Jan 21 10:14:18 PM PST 24
Peak memory 238748 kb
Host smart-74b212a6-6bc8-4bb2-a94d-eec0e388aa28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135899559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1135899559
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.3912876897
Short name T1212
Test name
Test status
Simulation time 216692556 ps
CPU time 3.99 seconds
Started Jan 21 10:13:51 PM PST 24
Finished Jan 21 10:13:59 PM PST 24
Peak memory 244176 kb
Host smart-be38fb1c-a480-4a97-9fc0-e9ae1632e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912876897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.3912876897
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.2678861137
Short name T1148
Test name
Test status
Simulation time 58995571450 ps
CPU time 155.83 seconds
Started Jan 21 10:22:21 PM PST 24
Finished Jan 21 10:25:08 PM PST 24
Peak memory 255308 kb
Host smart-f6e718dd-2c93-491b-af4d-959d4e163ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678861137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.2678861137
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.3155366064
Short name T592
Test name
Test status
Simulation time 257868746413 ps
CPU time 2001.09 seconds
Started Jan 21 10:14:02 PM PST 24
Finished Jan 21 10:47:27 PM PST 24
Peak memory 255232 kb
Host smart-faca5667-e40b-459f-a181-39c1679b6554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155366064 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.3155366064
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.3185705857
Short name T602
Test name
Test status
Simulation time 10193062780 ps
CPU time 15.79 seconds
Started Jan 21 10:14:01 PM PST 24
Finished Jan 21 10:14:20 PM PST 24
Peak memory 244868 kb
Host smart-200d45a5-2197-479b-89eb-080137797d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185705857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3185705857
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1503844790
Short name T681
Test name
Test status
Simulation time 294841040 ps
CPU time 3.59 seconds
Started Jan 21 10:20:26 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 238632 kb
Host smart-a89f2c98-07e6-4d29-8881-7dfaa50aa8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503844790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1503844790
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.3565213171
Short name T151
Test name
Test status
Simulation time 411400812 ps
CPU time 4.1 seconds
Started Jan 21 10:20:25 PM PST 24
Finished Jan 21 10:20:32 PM PST 24
Peak memory 241252 kb
Host smart-0205622f-ea9b-4136-8849-b195dbc592f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565213171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.3565213171
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1070639792
Short name T60
Test name
Test status
Simulation time 134684330 ps
CPU time 4.09 seconds
Started Jan 21 10:20:22 PM PST 24
Finished Jan 21 10:20:32 PM PST 24
Peak memory 241280 kb
Host smart-d9a7ef99-68a4-4d25-8fa6-833ea8ed71f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070639792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1070639792
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.1807981547
Short name T960
Test name
Test status
Simulation time 166416485 ps
CPU time 4.89 seconds
Started Jan 21 10:20:17 PM PST 24
Finished Jan 21 10:20:30 PM PST 24
Peak memory 238772 kb
Host smart-6cd72d34-7a5a-4fe7-ab2e-1b2f978fa80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807981547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1807981547
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.2766528082
Short name T866
Test name
Test status
Simulation time 2011548093 ps
CPU time 4.42 seconds
Started Jan 21 10:20:21 PM PST 24
Finished Jan 21 10:20:31 PM PST 24
Peak memory 238796 kb
Host smart-97ce157a-c1b0-45fb-94ae-e7cf474c113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766528082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2766528082
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3573961120
Short name T954
Test name
Test status
Simulation time 250957719 ps
CPU time 4.16 seconds
Started Jan 21 10:20:24 PM PST 24
Finished Jan 21 10:20:32 PM PST 24
Peak memory 241108 kb
Host smart-114d66e3-feba-486a-ba6e-c5f20948ed46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573961120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3573961120
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.2896604099
Short name T1073
Test name
Test status
Simulation time 599765494 ps
CPU time 4.65 seconds
Started Jan 21 10:49:56 PM PST 24
Finished Jan 21 10:50:02 PM PST 24
Peak memory 240876 kb
Host smart-770ecedc-87e9-4832-ba78-7f6b1d76976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896604099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2896604099
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.1051306839
Short name T932
Test name
Test status
Simulation time 422258100 ps
CPU time 4.66 seconds
Started Jan 21 10:20:26 PM PST 24
Finished Jan 21 10:20:34 PM PST 24
Peak memory 241004 kb
Host smart-99e2d0d1-288b-497c-a715-6749c8bbb3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051306839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1051306839
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.4215221331
Short name T593
Test name
Test status
Simulation time 137163984 ps
CPU time 3.93 seconds
Started Jan 21 10:40:36 PM PST 24
Finished Jan 21 10:40:48 PM PST 24
Peak memory 238712 kb
Host smart-98b33ec2-7fe6-4995-815b-e09556164383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215221331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.4215221331
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.1620882782
Short name T1293
Test name
Test status
Simulation time 578441296 ps
CPU time 4.05 seconds
Started Jan 21 10:49:13 PM PST 24
Finished Jan 21 10:49:20 PM PST 24
Peak memory 238884 kb
Host smart-415bc598-9d9c-42e9-bc55-90942157b0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620882782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1620882782
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.2594392372
Short name T887
Test name
Test status
Simulation time 81662718 ps
CPU time 1.93 seconds
Started Jan 21 10:14:10 PM PST 24
Finished Jan 21 10:14:16 PM PST 24
Peak memory 238564 kb
Host smart-59d6b7c4-e4d2-40e2-8411-79cada7a718b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594392372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2594392372
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3533277565
Short name T584
Test name
Test status
Simulation time 155880742 ps
CPU time 3.55 seconds
Started Jan 21 10:14:09 PM PST 24
Finished Jan 21 10:14:17 PM PST 24
Peak memory 238768 kb
Host smart-91e6ea89-9fb1-49fa-96d9-c6583d9fc479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533277565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3533277565
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.1003297822
Short name T598
Test name
Test status
Simulation time 5921119331 ps
CPU time 21.27 seconds
Started Jan 21 10:14:05 PM PST 24
Finished Jan 21 10:14:31 PM PST 24
Peak memory 246940 kb
Host smart-8ddcfaf7-59b8-4264-ad64-629ffb677ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003297822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1003297822
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2461000638
Short name T740
Test name
Test status
Simulation time 3511390089 ps
CPU time 19.49 seconds
Started Jan 21 10:14:03 PM PST 24
Finished Jan 21 10:14:28 PM PST 24
Peak memory 238772 kb
Host smart-44e5f81e-ba28-4342-9dd0-e0c41e562dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461000638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2461000638
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.908900990
Short name T554
Test name
Test status
Simulation time 1956497246 ps
CPU time 4.41 seconds
Started Jan 21 10:14:03 PM PST 24
Finished Jan 21 10:14:11 PM PST 24
Peak memory 240996 kb
Host smart-f3d2cd2a-1e07-4c0e-b481-29899a85cfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908900990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.908900990
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.189480317
Short name T633
Test name
Test status
Simulation time 2788120813 ps
CPU time 24.59 seconds
Started Jan 21 10:14:09 PM PST 24
Finished Jan 21 10:14:39 PM PST 24
Peak memory 238936 kb
Host smart-06f4e7bf-13ed-4997-8670-36e270b887b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189480317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.189480317
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.853033786
Short name T1263
Test name
Test status
Simulation time 1575074202 ps
CPU time 5.69 seconds
Started Jan 21 10:13:58 PM PST 24
Finished Jan 21 10:14:05 PM PST 24
Peak memory 241380 kb
Host smart-c05076e1-a0b1-4021-9097-7b9102b4136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853033786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.853033786
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.2321055933
Short name T924
Test name
Test status
Simulation time 171924761 ps
CPU time 3.41 seconds
Started Jan 21 10:14:01 PM PST 24
Finished Jan 21 10:14:07 PM PST 24
Peak memory 238792 kb
Host smart-238817c2-9a87-4ba4-b5ce-42309cb63399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321055933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2321055933
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.2635818755
Short name T801
Test name
Test status
Simulation time 95156539 ps
CPU time 4 seconds
Started Jan 21 10:14:13 PM PST 24
Finished Jan 21 10:14:21 PM PST 24
Peak memory 241680 kb
Host smart-14f90d15-d099-4288-9bce-4951d3f00c38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635818755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2635818755
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.2032924559
Short name T510
Test name
Test status
Simulation time 1740443755 ps
CPU time 3.71 seconds
Started Jan 21 10:14:02 PM PST 24
Finished Jan 21 10:14:09 PM PST 24
Peak memory 241572 kb
Host smart-68b28005-3489-44ea-b09b-822d4d8c6247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032924559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2032924559
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.2487598761
Short name T18
Test name
Test status
Simulation time 480844485100 ps
CPU time 4027.27 seconds
Started Jan 21 10:14:13 PM PST 24
Finished Jan 21 11:21:24 PM PST 24
Peak memory 352524 kb
Host smart-405c44ff-2d02-4b37-8c60-240e5b661128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487598761 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.2487598761
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.2792186265
Short name T1110
Test name
Test status
Simulation time 819777816 ps
CPU time 14.21 seconds
Started Jan 21 10:14:06 PM PST 24
Finished Jan 21 10:14:25 PM PST 24
Peak memory 244348 kb
Host smart-e2385abb-38c4-4494-a40f-5292cf8f3499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792186265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2792186265
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.1378253410
Short name T48
Test name
Test status
Simulation time 228473739 ps
CPU time 3.21 seconds
Started Jan 21 11:19:29 PM PST 24
Finished Jan 21 11:19:33 PM PST 24
Peak memory 241376 kb
Host smart-293e9c78-7c45-4575-af9e-c2a3418c572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378253410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1378253410
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.3447286280
Short name T124
Test name
Test status
Simulation time 475074268 ps
CPU time 5.26 seconds
Started Jan 21 10:20:28 PM PST 24
Finished Jan 21 10:20:36 PM PST 24
Peak memory 241348 kb
Host smart-726cda3c-4554-4f55-a9bc-839bd34be0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447286280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3447286280
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.3918620954
Short name T733
Test name
Test status
Simulation time 483593908 ps
CPU time 4.18 seconds
Started Jan 21 10:20:26 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 241108 kb
Host smart-c1eca7aa-39af-4b28-b800-f70480db127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918620954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3918620954
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.4140070788
Short name T706
Test name
Test status
Simulation time 1933286779 ps
CPU time 6.09 seconds
Started Jan 21 10:20:28 PM PST 24
Finished Jan 21 10:20:37 PM PST 24
Peak memory 240588 kb
Host smart-f0574189-b968-49fb-9709-21624045aa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140070788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.4140070788
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.1367446543
Short name T878
Test name
Test status
Simulation time 2154392797 ps
CPU time 7.45 seconds
Started Jan 21 10:20:30 PM PST 24
Finished Jan 21 10:20:40 PM PST 24
Peak memory 238844 kb
Host smart-df1fec9d-86d5-458a-8b80-d7d43e39cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367446543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1367446543
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.3451747049
Short name T231
Test name
Test status
Simulation time 607500458 ps
CPU time 4.19 seconds
Started Jan 21 10:20:25 PM PST 24
Finished Jan 21 10:20:32 PM PST 24
Peak memory 238740 kb
Host smart-d3e70dc4-e9c1-46ed-99eb-30c4efa04a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451747049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3451747049
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3486785344
Short name T144
Test name
Test status
Simulation time 2130024223 ps
CPU time 5.18 seconds
Started Jan 21 10:20:29 PM PST 24
Finished Jan 21 10:20:37 PM PST 24
Peak memory 238732 kb
Host smart-04460d96-6ef3-4d17-be06-9c69e4e894af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486785344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3486785344
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1311638607
Short name T1002
Test name
Test status
Simulation time 123435404 ps
CPU time 4.62 seconds
Started Jan 21 10:20:26 PM PST 24
Finished Jan 21 10:20:33 PM PST 24
Peak memory 241544 kb
Host smart-4a3c05a1-cdb4-41e0-be01-471801000940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311638607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1311638607
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.150387680
Short name T523
Test name
Test status
Simulation time 1820423674 ps
CPU time 5.19 seconds
Started Jan 21 10:20:29 PM PST 24
Finished Jan 21 10:20:37 PM PST 24
Peak memory 241312 kb
Host smart-3df98e33-d57c-465f-80f1-9580c133260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150387680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.150387680
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3293149729
Short name T863
Test name
Test status
Simulation time 53147056 ps
CPU time 1.63 seconds
Started Jan 21 10:57:26 PM PST 24
Finished Jan 21 10:57:31 PM PST 24
Peak memory 239600 kb
Host smart-7e80b1ca-9c45-4a58-a423-15a40870a9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293149729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3293149729
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.2915673925
Short name T308
Test name
Test status
Simulation time 502845206 ps
CPU time 7.27 seconds
Started Jan 21 10:14:18 PM PST 24
Finished Jan 21 10:14:27 PM PST 24
Peak memory 238792 kb
Host smart-dd059af4-ed5d-4657-91ea-adc09631a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915673925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.2915673925
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3903700818
Short name T470
Test name
Test status
Simulation time 839772145 ps
CPU time 10.86 seconds
Started Jan 21 10:14:07 PM PST 24
Finished Jan 21 10:14:22 PM PST 24
Peak memory 238816 kb
Host smart-fd79638e-4dea-402e-b33d-694e7ab29b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903700818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3903700818
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.835053117
Short name T576
Test name
Test status
Simulation time 312788741 ps
CPU time 3.71 seconds
Started Jan 21 10:14:08 PM PST 24
Finished Jan 21 10:14:16 PM PST 24
Peak memory 241368 kb
Host smart-5f3bbaf7-2595-4974-b329-442f05ece16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835053117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.835053117
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1396847541
Short name T169
Test name
Test status
Simulation time 217405689 ps
CPU time 3.47 seconds
Started Jan 21 10:14:11 PM PST 24
Finished Jan 21 10:14:19 PM PST 24
Peak memory 241148 kb
Host smart-d3677914-f096-4acd-8e2d-042a7bd841d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396847541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1396847541
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.312423701
Short name T845
Test name
Test status
Simulation time 271375038 ps
CPU time 5.95 seconds
Started Jan 21 10:14:21 PM PST 24
Finished Jan 21 10:14:29 PM PST 24
Peak memory 243100 kb
Host smart-09b9a86c-b4b3-4cfd-bcac-b0bc7ac5b672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312423701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.312423701
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.545863284
Short name T354
Test name
Test status
Simulation time 4503548321 ps
CPU time 16.25 seconds
Started Jan 21 10:14:23 PM PST 24
Finished Jan 21 10:14:41 PM PST 24
Peak memory 238844 kb
Host smart-1b5f860a-ffbd-44d3-b84b-47f2c5f357ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545863284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.545863284
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.1465908604
Short name T384
Test name
Test status
Simulation time 504245720 ps
CPU time 3.59 seconds
Started Jan 21 10:14:19 PM PST 24
Finished Jan 21 10:14:24 PM PST 24
Peak memory 241452 kb
Host smart-6efb6f13-838c-4091-a8e6-a5cf0fe1090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465908604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.1465908604
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.641062128
Short name T1253
Test name
Test status
Simulation time 562187391 ps
CPU time 16.97 seconds
Started Jan 21 10:14:13 PM PST 24
Finished Jan 21 10:14:34 PM PST 24
Peak memory 238692 kb
Host smart-93563d54-de02-4e18-8f9e-108105cd3e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641062128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.641062128
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.2573589684
Short name T331
Test name
Test status
Simulation time 461033874 ps
CPU time 5.69 seconds
Started Jan 21 10:14:22 PM PST 24
Finished Jan 21 10:14:30 PM PST 24
Peak memory 238800 kb
Host smart-6de91326-0f57-4adc-85c4-bda06000f028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573589684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2573589684
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.4214274832
Short name T818
Test name
Test status
Simulation time 135451134 ps
CPU time 3.26 seconds
Started Jan 21 10:14:05 PM PST 24
Finished Jan 21 10:14:13 PM PST 24
Peak memory 240984 kb
Host smart-c7b6c7d6-9578-42ab-b858-94bf38319809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214274832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.4214274832
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.851023176
Short name T765
Test name
Test status
Simulation time 40737093601 ps
CPU time 144.48 seconds
Started Jan 21 10:14:21 PM PST 24
Finished Jan 21 10:16:47 PM PST 24
Peak memory 242608 kb
Host smart-c6d3c990-3a5d-4177-ba27-c277bd8aa4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851023176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.
851023176
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.3059817935
Short name T311
Test name
Test status
Simulation time 2792874065924 ps
CPU time 4765.25 seconds
Started Jan 21 10:14:24 PM PST 24
Finished Jan 21 11:33:52 PM PST 24
Peak memory 920336 kb
Host smart-37de12a8-bdbb-4641-b608-3b0ceb54ee36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059817935 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.3059817935
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.1335257995
Short name T1085
Test name
Test status
Simulation time 364159077 ps
CPU time 8.67 seconds
Started Jan 21 10:14:18 PM PST 24
Finished Jan 21 10:14:28 PM PST 24
Peak memory 244540 kb
Host smart-665eedd4-21da-4e75-9a94-056c7f2ce84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335257995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1335257995
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.205292784
Short name T841
Test name
Test status
Simulation time 121053491 ps
CPU time 3.93 seconds
Started Jan 21 10:20:28 PM PST 24
Finished Jan 21 10:20:34 PM PST 24
Peak memory 238744 kb
Host smart-0a0e9733-cc1f-4436-b6f7-b30bd9751082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205292784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.205292784
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.222622968
Short name T82
Test name
Test status
Simulation time 246477399 ps
CPU time 3.46 seconds
Started Jan 21 10:20:29 PM PST 24
Finished Jan 21 10:20:35 PM PST 24
Peak memory 238784 kb
Host smart-763d2596-7248-4f43-9b63-250775f6f74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222622968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.222622968
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.3998958632
Short name T694
Test name
Test status
Simulation time 1917767984 ps
CPU time 6.33 seconds
Started Jan 21 10:20:27 PM PST 24
Finished Jan 21 10:20:36 PM PST 24
Peak memory 241208 kb
Host smart-063bde03-c586-45dd-9640-3882b83da155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998958632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3998958632
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.834724233
Short name T821
Test name
Test status
Simulation time 244446203 ps
CPU time 3.63 seconds
Started Jan 21 10:20:28 PM PST 24
Finished Jan 21 10:20:34 PM PST 24
Peak memory 238708 kb
Host smart-d38f2701-b5e9-47d1-bc8c-259a075afbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834724233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.834724233
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.4092250617
Short name T562
Test name
Test status
Simulation time 204259672 ps
CPU time 4.23 seconds
Started Jan 21 10:20:28 PM PST 24
Finished Jan 21 10:20:34 PM PST 24
Peak memory 238684 kb
Host smart-0bed2d5d-098e-4093-a785-3d7a50b9945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092250617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.4092250617
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.3438474053
Short name T167
Test name
Test status
Simulation time 495530181 ps
CPU time 3.8 seconds
Started Jan 21 10:20:30 PM PST 24
Finished Jan 21 10:20:37 PM PST 24
Peak memory 240908 kb
Host smart-c8c36bbf-ca30-4a74-ad6c-24028fcaf1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438474053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.3438474053
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.432669374
Short name T1020
Test name
Test status
Simulation time 120682350 ps
CPU time 3.74 seconds
Started Jan 21 10:20:25 PM PST 24
Finished Jan 21 10:20:32 PM PST 24
Peak memory 241192 kb
Host smart-9de219b9-121b-4250-9d6c-83281cc03df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432669374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.432669374
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.3932766710
Short name T141
Test name
Test status
Simulation time 144484358 ps
CPU time 4.08 seconds
Started Jan 21 10:20:29 PM PST 24
Finished Jan 21 10:20:36 PM PST 24
Peak memory 241552 kb
Host smart-7b81cccb-a3b9-40c0-a9a6-369c94db21f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932766710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3932766710
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2476365941
Short name T793
Test name
Test status
Simulation time 182689329 ps
CPU time 1.65 seconds
Started Jan 21 10:14:30 PM PST 24
Finished Jan 21 10:14:34 PM PST 24
Peak memory 230472 kb
Host smart-f1c7f740-ff60-420a-aa88-35317d02355a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476365941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2476365941
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.997272025
Short name T30
Test name
Test status
Simulation time 910252673 ps
CPU time 6.37 seconds
Started Jan 21 10:14:17 PM PST 24
Finished Jan 21 10:14:25 PM PST 24
Peak memory 238792 kb
Host smart-b50c4db2-0c27-48b3-8e18-310e97c1cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997272025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.997272025
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.1569711789
Short name T1093
Test name
Test status
Simulation time 2243342933 ps
CPU time 10.43 seconds
Started Jan 21 10:14:20 PM PST 24
Finished Jan 21 10:14:33 PM PST 24
Peak memory 243476 kb
Host smart-67fc29c7-ff1f-4ca8-8e34-71173b872f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569711789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.1569711789
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.1708300216
Short name T855
Test name
Test status
Simulation time 669467615 ps
CPU time 7.49 seconds
Started Jan 21 10:14:17 PM PST 24
Finished Jan 21 10:14:26 PM PST 24
Peak memory 247056 kb
Host smart-d7feac96-ac26-4f11-9efa-f7c934a3478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708300216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1708300216
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.2022854983
Short name T472
Test name
Test status
Simulation time 104605484 ps
CPU time 3.95 seconds
Started Jan 21 10:14:20 PM PST 24
Finished Jan 21 10:14:27 PM PST 24
Peak memory 240708 kb
Host smart-103c245e-d51b-4205-b978-3fdaf227287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022854983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2022854983
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.740122321
Short name T305
Test name
Test status
Simulation time 3800308610 ps
CPU time 15.57 seconds
Started Jan 21 10:14:16 PM PST 24
Finished Jan 21 10:14:34 PM PST 24
Peak memory 238828 kb
Host smart-bd3cb785-ad21-4ee9-bb70-ff891279b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740122321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.740122321
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.3364959142
Short name T1147
Test name
Test status
Simulation time 386986669 ps
CPU time 4.77 seconds
Started Jan 21 10:14:23 PM PST 24
Finished Jan 21 10:14:30 PM PST 24
Peak memory 241612 kb
Host smart-c8925671-604e-41a3-8480-404c9702541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364959142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3364959142
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1749559770
Short name T506
Test name
Test status
Simulation time 214690446 ps
CPU time 3.31 seconds
Started Jan 21 10:14:26 PM PST 24
Finished Jan 21 10:14:32 PM PST 24
Peak memory 238804 kb
Host smart-021896cc-dc6c-40fe-a2d9-b44c0611da2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749559770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1749559770
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.4266648583
Short name T539
Test name
Test status
Simulation time 354566393 ps
CPU time 5.23 seconds
Started Jan 21 10:14:15 PM PST 24
Finished Jan 21 10:14:22 PM PST 24
Peak memory 238732 kb
Host smart-811f5524-7fe6-4fe0-a593-178f5e2d8da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266648583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.4266648583
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.2712001915
Short name T748
Test name
Test status
Simulation time 261399028 ps
CPU time 3.99 seconds
Started Jan 21 10:14:32 PM PST 24
Finished Jan 21 10:14:38 PM PST 24
Peak memory 238752 kb
Host smart-71c40057-e583-43be-821c-533398a18add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712001915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2712001915
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.2663547116
Short name T1184
Test name
Test status
Simulation time 491122874 ps
CPU time 5.88 seconds
Started Jan 21 10:14:26 PM PST 24
Finished Jan 21 10:14:34 PM PST 24
Peak memory 238728 kb
Host smart-a3c7628e-126d-439c-a904-cd800472cdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663547116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2663547116
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2921089793
Short name T938
Test name
Test status
Simulation time 4949450206 ps
CPU time 30.42 seconds
Started Jan 21 10:14:28 PM PST 24
Finished Jan 21 10:15:01 PM PST 24
Peak memory 239884 kb
Host smart-02fb2b1b-525e-4544-9330-1479d8ad3661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921089793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2921089793
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.944902615
Short name T1102
Test name
Test status
Simulation time 216540875889 ps
CPU time 4292.49 seconds
Started Jan 21 10:14:26 PM PST 24
Finished Jan 21 11:26:01 PM PST 24
Peak memory 289988 kb
Host smart-267b91d4-12bb-496e-90f8-d83ecdfd9901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944902615 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.944902615
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.3867211632
Short name T371
Test name
Test status
Simulation time 1101935954 ps
CPU time 13.67 seconds
Started Jan 21 10:14:31 PM PST 24
Finished Jan 21 10:14:47 PM PST 24
Peak memory 238960 kb
Host smart-b17a0956-68de-4421-b813-51b895b83f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867211632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3867211632
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.242500695
Short name T512
Test name
Test status
Simulation time 138537273 ps
CPU time 3.75 seconds
Started Jan 21 10:20:34 PM PST 24
Finished Jan 21 10:20:41 PM PST 24
Peak memory 238784 kb
Host smart-fb54f87e-4084-439b-b611-436008228088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242500695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.242500695
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.938891579
Short name T1197
Test name
Test status
Simulation time 175971627 ps
CPU time 4.41 seconds
Started Jan 21 10:20:34 PM PST 24
Finished Jan 21 10:20:42 PM PST 24
Peak memory 238792 kb
Host smart-ebdbde35-b517-401f-818b-3d3198e020da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938891579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.938891579
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.2610922005
Short name T1045
Test name
Test status
Simulation time 139674828 ps
CPU time 3.94 seconds
Started Jan 21 10:20:35 PM PST 24
Finished Jan 21 10:20:41 PM PST 24
Peak memory 238712 kb
Host smart-072a31c5-b22d-45ea-bd62-b948ccbfdea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610922005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2610922005
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.2265915688
Short name T709
Test name
Test status
Simulation time 255307138 ps
CPU time 3.32 seconds
Started Jan 21 10:20:33 PM PST 24
Finished Jan 21 10:20:40 PM PST 24
Peak memory 238704 kb
Host smart-9931860f-d5dd-4930-be35-776011b89dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265915688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2265915688
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1986166164
Short name T565
Test name
Test status
Simulation time 1685434236 ps
CPU time 5.41 seconds
Started Jan 21 10:20:35 PM PST 24
Finished Jan 21 10:20:43 PM PST 24
Peak memory 240720 kb
Host smart-e823bd5b-8101-4ff0-ab76-770f66a2c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986166164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1986166164
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.2807312551
Short name T1090
Test name
Test status
Simulation time 206247842 ps
CPU time 3.97 seconds
Started Jan 21 10:20:32 PM PST 24
Finished Jan 21 10:20:40 PM PST 24
Peak memory 240960 kb
Host smart-f29ea042-fd1b-4089-b74e-9bcab9b0fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807312551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2807312551
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.1796586781
Short name T956
Test name
Test status
Simulation time 220698607 ps
CPU time 4.27 seconds
Started Jan 21 10:20:42 PM PST 24
Finished Jan 21 10:20:54 PM PST 24
Peak memory 246928 kb
Host smart-c2439dad-b476-47c5-b26e-99268d8c9d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796586781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1796586781
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.1808045021
Short name T179
Test name
Test status
Simulation time 189588118 ps
CPU time 4.89 seconds
Started Jan 21 10:20:34 PM PST 24
Finished Jan 21 10:20:42 PM PST 24
Peak memory 238820 kb
Host smart-7c850f87-4d2f-43bd-8e68-69ab1ad9a5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808045021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.1808045021
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.409124435
Short name T536
Test name
Test status
Simulation time 238101967 ps
CPU time 3.49 seconds
Started Jan 21 10:20:42 PM PST 24
Finished Jan 21 10:20:53 PM PST 24
Peak memory 238772 kb
Host smart-c7b468a4-75bc-47dd-9730-bec14da96367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409124435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.409124435
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.2219407561
Short name T750
Test name
Test status
Simulation time 199111054 ps
CPU time 2.07 seconds
Started Jan 21 10:14:24 PM PST 24
Finished Jan 21 10:14:29 PM PST 24
Peak memory 239664 kb
Host smart-b297fc54-804a-4e59-b5fa-a22071907829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219407561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2219407561
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.700280427
Short name T1252
Test name
Test status
Simulation time 2796046987 ps
CPU time 16.3 seconds
Started Jan 21 10:14:27 PM PST 24
Finished Jan 21 10:14:46 PM PST 24
Peak memory 238876 kb
Host smart-03115394-3e68-4cbc-9b3d-f74674a52a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700280427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.700280427
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1726917874
Short name T574
Test name
Test status
Simulation time 760529803 ps
CPU time 9.45 seconds
Started Jan 21 10:14:24 PM PST 24
Finished Jan 21 10:14:35 PM PST 24
Peak memory 243260 kb
Host smart-289e109f-bd97-4ff9-a4fb-7dde0115be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726917874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1726917874
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.1845897648
Short name T690
Test name
Test status
Simulation time 444815625 ps
CPU time 9.27 seconds
Started Jan 21 10:14:30 PM PST 24
Finished Jan 21 10:14:42 PM PST 24
Peak memory 244680 kb
Host smart-01ce5c4e-3a48-4445-90f4-5c704544008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845897648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1845897648
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.986523256
Short name T1283
Test name
Test status
Simulation time 144624118 ps
CPU time 4.21 seconds
Started Jan 21 10:14:29 PM PST 24
Finished Jan 21 10:14:36 PM PST 24
Peak memory 242924 kb
Host smart-abbee7db-c36f-4328-8cfc-207bda99a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986523256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.986523256
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3240831213
Short name T930
Test name
Test status
Simulation time 11374235480 ps
CPU time 29.45 seconds
Started Jan 21 10:14:30 PM PST 24
Finished Jan 21 10:15:02 PM PST 24
Peak memory 247092 kb
Host smart-e70cd4de-fd22-4a31-a1d1-d17b86e8e481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240831213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3240831213
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.1634117081
Short name T1140
Test name
Test status
Simulation time 5574106167 ps
CPU time 13.84 seconds
Started Jan 21 10:14:25 PM PST 24
Finished Jan 21 10:14:41 PM PST 24
Peak memory 238840 kb
Host smart-9735a5b6-7ebe-4651-947e-ec7364389cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634117081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.1634117081
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.1900858614
Short name T204
Test name
Test status
Simulation time 282519802 ps
CPU time 4.04 seconds
Started Jan 21 10:14:31 PM PST 24
Finished Jan 21 10:14:37 PM PST 24
Peak memory 241348 kb
Host smart-de4ab637-cd7a-42e4-b7a8-d08ef205fcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900858614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1900858614
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.1123818559
Short name T783
Test name
Test status
Simulation time 484200362 ps
CPU time 15.54 seconds
Started Jan 21 10:14:32 PM PST 24
Finished Jan 21 10:14:49 PM PST 24
Peak memory 238736 kb
Host smart-c18c3bba-ecc9-4f37-837c-e0fb00304487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123818559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1123818559
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.277577519
Short name T545
Test name
Test status
Simulation time 711163404 ps
CPU time 5.31 seconds
Started Jan 21 10:14:29 PM PST 24
Finished Jan 21 10:14:37 PM PST 24
Peak memory 238976 kb
Host smart-37578cf6-1044-49aa-90e8-3e42bd58e27b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277577519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.277577519
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1241200560
Short name T993
Test name
Test status
Simulation time 4412041426 ps
CPU time 8.55 seconds
Started Jan 21 10:14:24 PM PST 24
Finished Jan 21 10:14:35 PM PST 24
Peak memory 243948 kb
Host smart-dd3a5ecd-c090-4642-b7da-0bbc74c8e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241200560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1241200560
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.4181477336
Short name T874
Test name
Test status
Simulation time 250204060431 ps
CPU time 2639.38 seconds
Started Jan 21 10:14:36 PM PST 24
Finished Jan 21 10:58:39 PM PST 24
Peak memory 930140 kb
Host smart-d103572c-7cc5-434f-8833-e624b7633f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181477336 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.4181477336
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2867820736
Short name T478
Test name
Test status
Simulation time 1931033795 ps
CPU time 3.49 seconds
Started Jan 21 10:14:25 PM PST 24
Finished Jan 21 10:14:31 PM PST 24
Peak memory 243608 kb
Host smart-382d4d2c-7a16-416e-a4a9-659c86ea6d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867820736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2867820736
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.2869840764
Short name T929
Test name
Test status
Simulation time 356054643 ps
CPU time 5.23 seconds
Started Jan 21 10:20:35 PM PST 24
Finished Jan 21 10:20:43 PM PST 24
Peak memory 241496 kb
Host smart-b9e25173-bbe2-4c0d-9074-c7050d7edbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869840764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2869840764
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.4132915663
Short name T761
Test name
Test status
Simulation time 490868112 ps
CPU time 4.48 seconds
Started Jan 21 10:20:35 PM PST 24
Finished Jan 21 10:20:42 PM PST 24
Peak memory 241144 kb
Host smart-cbd2de75-83d7-4d0a-b327-dbfe9be550c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132915663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.4132915663
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.979206746
Short name T594
Test name
Test status
Simulation time 2661053387 ps
CPU time 6.46 seconds
Started Jan 21 10:20:33 PM PST 24
Finished Jan 21 10:20:43 PM PST 24
Peak memory 241276 kb
Host smart-d1578e6d-cd67-47b8-b233-8275063680ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979206746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.979206746
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.4183186470
Short name T1095
Test name
Test status
Simulation time 173751250 ps
CPU time 4.45 seconds
Started Jan 21 10:20:52 PM PST 24
Finished Jan 21 10:21:16 PM PST 24
Peak memory 241144 kb
Host smart-70a77f43-8e05-447c-81fd-79c1627f79dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183186470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.4183186470
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.4136146424
Short name T58
Test name
Test status
Simulation time 138274814 ps
CPU time 3.3 seconds
Started Jan 21 10:20:40 PM PST 24
Finished Jan 21 10:20:50 PM PST 24
Peak memory 238776 kb
Host smart-0f6518e4-9efd-43ca-8d64-c21cbf92192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136146424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.4136146424
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.871169500
Short name T789
Test name
Test status
Simulation time 242302927 ps
CPU time 4.43 seconds
Started Jan 21 10:20:52 PM PST 24
Finished Jan 21 10:21:16 PM PST 24
Peak memory 238748 kb
Host smart-953117a9-58aa-492b-b3a5-8746bc47c831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871169500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.871169500
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.3115498181
Short name T1033
Test name
Test status
Simulation time 140062407 ps
CPU time 3.9 seconds
Started Jan 21 10:20:44 PM PST 24
Finished Jan 21 10:20:57 PM PST 24
Peak memory 246860 kb
Host smart-3c24c92f-7e0a-4e84-8784-b510f98ba14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115498181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3115498181
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.3486151402
Short name T469
Test name
Test status
Simulation time 193100231 ps
CPU time 3.48 seconds
Started Jan 21 10:20:41 PM PST 24
Finished Jan 21 10:20:52 PM PST 24
Peak memory 238764 kb
Host smart-79be6e9c-0e70-4d76-bca7-fe9f6b110bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486151402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3486151402
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.143580020
Short name T1038
Test name
Test status
Simulation time 489882905 ps
CPU time 4.09 seconds
Started Jan 21 10:20:48 PM PST 24
Finished Jan 21 10:21:12 PM PST 24
Peak memory 238728 kb
Host smart-900f90a5-6a24-437d-a9ea-25a28975fa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143580020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.143580020
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2375665323
Short name T1297
Test name
Test status
Simulation time 535357898 ps
CPU time 4.51 seconds
Started Jan 21 10:20:45 PM PST 24
Finished Jan 21 10:21:03 PM PST 24
Peak memory 238708 kb
Host smart-94b0411c-b0ac-4feb-8985-892de695b0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375665323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2375665323
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3066217488
Short name T515
Test name
Test status
Simulation time 41117766 ps
CPU time 1.53 seconds
Started Jan 21 10:14:31 PM PST 24
Finished Jan 21 10:14:35 PM PST 24
Peak memory 230516 kb
Host smart-b3908704-f64b-4090-b0a4-930aa4c41a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066217488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3066217488
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.2449086455
Short name T73
Test name
Test status
Simulation time 576590945 ps
CPU time 11 seconds
Started Jan 21 10:14:30 PM PST 24
Finished Jan 21 10:14:43 PM PST 24
Peak memory 244124 kb
Host smart-3313deba-dc73-401a-a062-7720277ae970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449086455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.2449086455
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.3731302866
Short name T615
Test name
Test status
Simulation time 466632814 ps
CPU time 6.57 seconds
Started Jan 21 10:14:30 PM PST 24
Finished Jan 21 10:14:40 PM PST 24
Peak memory 243648 kb
Host smart-00ed360d-18c0-4c6b-8639-b1cc9ed7e0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731302866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3731302866
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.2750542367
Short name T742
Test name
Test status
Simulation time 356667814 ps
CPU time 8.94 seconds
Started Jan 21 10:14:37 PM PST 24
Finished Jan 21 10:14:49 PM PST 24
Peak memory 238744 kb
Host smart-0727a271-8197-4e10-bf41-25b626720c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750542367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2750542367
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.3247166098
Short name T919
Test name
Test status
Simulation time 168103427 ps
CPU time 4.2 seconds
Started Jan 21 10:14:24 PM PST 24
Finished Jan 21 10:14:30 PM PST 24
Peak memory 238776 kb
Host smart-81ab95ee-1518-4b86-9f66-5f0781cb9388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247166098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3247166098
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.1512796732
Short name T1139
Test name
Test status
Simulation time 678835946 ps
CPU time 11.55 seconds
Started Jan 21 10:14:35 PM PST 24
Finished Jan 21 10:14:49 PM PST 24
Peak memory 238616 kb
Host smart-772ca787-5163-45e4-88c7-42a198dd9536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512796732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1512796732
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2367879617
Short name T695
Test name
Test status
Simulation time 8877934024 ps
CPU time 19.52 seconds
Started Jan 21 10:14:30 PM PST 24
Finished Jan 21 10:14:52 PM PST 24
Peak memory 238844 kb
Host smart-99030195-99c2-43d4-8c6e-2827e5d74c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367879617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2367879617
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2652192931
Short name T820
Test name
Test status
Simulation time 362006579 ps
CPU time 5 seconds
Started Jan 21 10:14:32 PM PST 24
Finished Jan 21 10:14:39 PM PST 24
Peak memory 242948 kb
Host smart-7d963370-414c-4ab1-aa63-f58a3659dc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652192931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2652192931
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.1952352870
Short name T1121
Test name
Test status
Simulation time 2478053601 ps
CPU time 16.69 seconds
Started Jan 21 10:14:29 PM PST 24
Finished Jan 21 10:14:48 PM PST 24
Peak memory 238892 kb
Host smart-9feecd69-7854-43f7-942d-22b94ae6ffcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952352870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.1952352870
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1501312795
Short name T339
Test name
Test status
Simulation time 296834257 ps
CPU time 6.79 seconds
Started Jan 21 10:14:38 PM PST 24
Finished Jan 21 10:14:47 PM PST 24
Peak memory 238728 kb
Host smart-899d975f-8062-4197-83c3-1ca0b8cac8f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501312795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1501312795
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.3465626995
Short name T1210
Test name
Test status
Simulation time 631490792 ps
CPU time 9.84 seconds
Started Jan 21 10:14:30 PM PST 24
Finished Jan 21 10:14:43 PM PST 24
Peak memory 238792 kb
Host smart-433ab2f2-b4b2-41fd-9eef-b060af871821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465626995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3465626995
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.509451686
Short name T227
Test name
Test status
Simulation time 1521368078 ps
CPU time 21.61 seconds
Started Jan 21 10:14:43 PM PST 24
Finished Jan 21 10:15:17 PM PST 24
Peak memory 238792 kb
Host smart-33530963-336a-4130-8670-44b3178007a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509451686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
509451686
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.4272573320
Short name T213
Test name
Test status
Simulation time 442107673924 ps
CPU time 3472.34 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 11:12:48 PM PST 24
Peak memory 262852 kb
Host smart-5003a839-09c4-4d7e-affa-b14e0aadfa4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272573320 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.4272573320
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.750918433
Short name T546
Test name
Test status
Simulation time 1490148705 ps
CPU time 3.53 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 10:14:59 PM PST 24
Peak memory 243660 kb
Host smart-72d1198b-11e0-4f5b-ba2a-a947cf34c855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750918433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.750918433
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2733324917
Short name T1286
Test name
Test status
Simulation time 165798432 ps
CPU time 3.51 seconds
Started Jan 21 10:20:47 PM PST 24
Finished Jan 21 10:21:06 PM PST 24
Peak memory 241152 kb
Host smart-d96c9a15-9f6e-4e10-a663-2ea71c31d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733324917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2733324917
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.300862890
Short name T1266
Test name
Test status
Simulation time 142166535 ps
CPU time 3.84 seconds
Started Jan 21 10:56:47 PM PST 24
Finished Jan 21 10:56:51 PM PST 24
Peak memory 238804 kb
Host smart-5ac59eca-3e51-47f0-aec3-8c30b9578aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300862890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.300862890
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.2458794793
Short name T225
Test name
Test status
Simulation time 360641552 ps
CPU time 4.83 seconds
Started Jan 21 10:20:52 PM PST 24
Finished Jan 21 10:21:16 PM PST 24
Peak memory 238772 kb
Host smart-c38b17f0-285e-4c04-8f43-2b05dcf22595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458794793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2458794793
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.3407967810
Short name T491
Test name
Test status
Simulation time 295613770 ps
CPU time 4.19 seconds
Started Jan 21 10:55:25 PM PST 24
Finished Jan 21 10:55:31 PM PST 24
Peak memory 238772 kb
Host smart-6d381b97-9973-4df4-98d0-5b67c1b101f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407967810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3407967810
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2753142207
Short name T581
Test name
Test status
Simulation time 138194153 ps
CPU time 5.11 seconds
Started Jan 21 10:20:45 PM PST 24
Finished Jan 21 10:20:59 PM PST 24
Peak memory 241372 kb
Host smart-0d18b378-345f-4a99-aee1-ac337e7d6b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753142207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2753142207
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1128480463
Short name T942
Test name
Test status
Simulation time 2949769739 ps
CPU time 6.96 seconds
Started Jan 21 10:42:04 PM PST 24
Finished Jan 21 10:42:12 PM PST 24
Peak memory 243500 kb
Host smart-3e80e75f-0c50-459b-b31b-56f0af54adc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128480463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1128480463
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.2796281506
Short name T623
Test name
Test status
Simulation time 506621913 ps
CPU time 4.52 seconds
Started Jan 21 10:54:46 PM PST 24
Finished Jan 21 10:54:52 PM PST 24
Peak memory 241300 kb
Host smart-c5fd5556-751a-4eeb-bafa-5fd05613b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796281506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.2796281506
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.858749556
Short name T125
Test name
Test status
Simulation time 482968592 ps
CPU time 3.48 seconds
Started Jan 21 10:46:19 PM PST 24
Finished Jan 21 10:46:24 PM PST 24
Peak memory 238812 kb
Host smart-dab584f3-1ca5-4700-a465-4fdf64277df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858749556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.858749556
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.748083350
Short name T745
Test name
Test status
Simulation time 86601423 ps
CPU time 3.1 seconds
Started Jan 21 10:20:52 PM PST 24
Finished Jan 21 10:21:14 PM PST 24
Peak memory 238684 kb
Host smart-e3ff1cce-2adb-4beb-8a0c-0b4fb8381685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748083350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.748083350
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.2184661038
Short name T235
Test name
Test status
Simulation time 258560364 ps
CPU time 3.83 seconds
Started Jan 21 10:57:07 PM PST 24
Finished Jan 21 10:57:11 PM PST 24
Peak memory 238784 kb
Host smart-5668a077-5c0a-402b-b59c-23dfbf362651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184661038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2184661038
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.3379094469
Short name T768
Test name
Test status
Simulation time 104017633 ps
CPU time 1.76 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 10:14:57 PM PST 24
Peak memory 239624 kb
Host smart-a76afe24-2ae5-4896-b527-82fef4e243d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379094469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.3379094469
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.880545051
Short name T34
Test name
Test status
Simulation time 509933678 ps
CPU time 9.96 seconds
Started Jan 21 10:14:40 PM PST 24
Finished Jan 21 10:15:03 PM PST 24
Peak memory 238764 kb
Host smart-fef487b5-2f3f-434e-a441-df38defb249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880545051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.880545051
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.1034147082
Short name T676
Test name
Test status
Simulation time 536088992 ps
CPU time 8.83 seconds
Started Jan 21 10:14:43 PM PST 24
Finished Jan 21 10:15:04 PM PST 24
Peak memory 244796 kb
Host smart-c034c656-874c-4442-864e-b5adcd959328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034147082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1034147082
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.3904933800
Short name T175
Test name
Test status
Simulation time 1131366517 ps
CPU time 21.74 seconds
Started Jan 21 10:14:44 PM PST 24
Finished Jan 21 10:15:17 PM PST 24
Peak memory 244072 kb
Host smart-1e2b094c-4f91-4694-9af8-ca8b725d331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904933800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3904933800
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2613380776
Short name T941
Test name
Test status
Simulation time 1580692066 ps
CPU time 15.49 seconds
Started Jan 21 10:14:44 PM PST 24
Finished Jan 21 10:15:11 PM PST 24
Peak memory 238668 kb
Host smart-6b7a31c2-148a-49d5-9171-39807a80233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613380776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2613380776
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.4051993732
Short name T1278
Test name
Test status
Simulation time 3465901123 ps
CPU time 9.34 seconds
Started Jan 21 10:14:41 PM PST 24
Finished Jan 21 10:15:03 PM PST 24
Peak memory 238724 kb
Host smart-9a61b0ef-2103-48f9-941b-729031626c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051993732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.4051993732
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.4102036945
Short name T775
Test name
Test status
Simulation time 1864349109 ps
CPU time 7.46 seconds
Started Jan 21 10:14:35 PM PST 24
Finished Jan 21 10:14:45 PM PST 24
Peak memory 238648 kb
Host smart-4194dca5-39b8-4064-95f1-2b140c332823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102036945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.4102036945
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.3254258744
Short name T1042
Test name
Test status
Simulation time 1993352112 ps
CPU time 15.03 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 10:15:10 PM PST 24
Peak memory 238516 kb
Host smart-cc44831d-e446-4690-b272-34a30e497dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254258744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.3254258744
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.3435274007
Short name T984
Test name
Test status
Simulation time 232704955 ps
CPU time 6.25 seconds
Started Jan 21 10:14:41 PM PST 24
Finished Jan 21 10:15:01 PM PST 24
Peak memory 238792 kb
Host smart-cb73ce1f-ef5e-4fad-bf69-7acb4af32638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435274007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.3435274007
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.612927610
Short name T1280
Test name
Test status
Simulation time 1524286474 ps
CPU time 9.36 seconds
Started Jan 21 10:14:35 PM PST 24
Finished Jan 21 10:14:46 PM PST 24
Peak memory 238760 kb
Host smart-ca927cfd-c06b-4c60-9941-f0f2a47fa3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612927610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.612927610
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.3647046612
Short name T920
Test name
Test status
Simulation time 11448458689 ps
CPU time 93.01 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 10:16:28 PM PST 24
Peak memory 247104 kb
Host smart-e283a46b-239c-42e7-af33-aeee1ad2dd9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647046612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.3647046612
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.199885553
Short name T756
Test name
Test status
Simulation time 2046976145 ps
CPU time 14.67 seconds
Started Jan 21 10:14:48 PM PST 24
Finished Jan 21 10:15:13 PM PST 24
Peak memory 238744 kb
Host smart-d9a64b9d-8841-4482-b510-9ad22e3eb8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199885553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.199885553
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1801580899
Short name T237
Test name
Test status
Simulation time 504907168 ps
CPU time 4.04 seconds
Started Jan 21 10:20:51 PM PST 24
Finished Jan 21 10:21:15 PM PST 24
Peak memory 241012 kb
Host smart-cf42a957-ae21-427d-974b-8b5af7af5802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801580899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1801580899
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.3272504170
Short name T66
Test name
Test status
Simulation time 264799132 ps
CPU time 5.01 seconds
Started Jan 21 11:37:38 PM PST 24
Finished Jan 21 11:37:44 PM PST 24
Peak memory 238860 kb
Host smart-a3681b58-45bd-4f2e-9a50-6a15f7ec24bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272504170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3272504170
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.3914151330
Short name T893
Test name
Test status
Simulation time 116316714 ps
CPU time 3.98 seconds
Started Jan 21 10:20:59 PM PST 24
Finished Jan 21 10:21:19 PM PST 24
Peak memory 238676 kb
Host smart-a0dee81d-9a72-403d-83e2-8c4501a0c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914151330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3914151330
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.4293280905
Short name T147
Test name
Test status
Simulation time 2459137758 ps
CPU time 7.12 seconds
Started Jan 21 10:20:53 PM PST 24
Finished Jan 21 10:21:19 PM PST 24
Peak memory 241256 kb
Host smart-7281cf5c-2ac5-4ba9-b56b-880df2886692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293280905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.4293280905
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.2821165709
Short name T925
Test name
Test status
Simulation time 156742183 ps
CPU time 3.46 seconds
Started Jan 21 10:20:54 PM PST 24
Finished Jan 21 10:21:16 PM PST 24
Peak memory 246964 kb
Host smart-540a6ba9-3f72-45e9-a924-dad07009c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821165709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2821165709
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1137118425
Short name T1242
Test name
Test status
Simulation time 360073652 ps
CPU time 4.44 seconds
Started Jan 21 10:20:59 PM PST 24
Finished Jan 21 10:21:19 PM PST 24
Peak memory 238708 kb
Host smart-6612009c-5c39-41aa-a670-ca9777b96494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137118425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1137118425
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.20303726
Short name T1067
Test name
Test status
Simulation time 127917446 ps
CPU time 3.45 seconds
Started Jan 21 10:20:59 PM PST 24
Finished Jan 21 10:21:18 PM PST 24
Peak memory 238676 kb
Host smart-de5d01da-e8d8-49e1-afde-80925edd1742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20303726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.20303726
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.1570118094
Short name T757
Test name
Test status
Simulation time 120411130 ps
CPU time 3.47 seconds
Started Jan 21 10:21:02 PM PST 24
Finished Jan 21 10:21:19 PM PST 24
Peak memory 238776 kb
Host smart-ffff8b69-6f32-42c4-bc3f-1eaa3f944e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570118094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1570118094
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.3700154137
Short name T1074
Test name
Test status
Simulation time 1619102964 ps
CPU time 4.49 seconds
Started Jan 21 10:20:56 PM PST 24
Finished Jan 21 10:21:18 PM PST 24
Peak memory 238616 kb
Host smart-dcc2dc5b-d0f7-40fa-b333-d10f8fbf5eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700154137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3700154137
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.2399903630
Short name T538
Test name
Test status
Simulation time 51761180 ps
CPU time 1.69 seconds
Started Jan 21 10:14:48 PM PST 24
Finished Jan 21 10:15:00 PM PST 24
Peak memory 239696 kb
Host smart-2376a269-19ba-4ce4-b8d1-dc7cbcfc45f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399903630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.2399903630
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.2529675269
Short name T1158
Test name
Test status
Simulation time 654356704 ps
CPU time 15.62 seconds
Started Jan 21 10:14:41 PM PST 24
Finished Jan 21 10:15:11 PM PST 24
Peak memory 238812 kb
Host smart-6cb51648-75b0-41ba-b546-76fe0975f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529675269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2529675269
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2055312153
Short name T760
Test name
Test status
Simulation time 600858367 ps
CPU time 8.62 seconds
Started Jan 21 10:14:43 PM PST 24
Finished Jan 21 10:15:04 PM PST 24
Peak memory 238796 kb
Host smart-8779352c-4c0c-45cf-a0c0-5d77b72da941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055312153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2055312153
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.2997810123
Short name T104
Test name
Test status
Simulation time 422716735 ps
CPU time 8.3 seconds
Started Jan 21 10:14:43 PM PST 24
Finished Jan 21 10:15:04 PM PST 24
Peak memory 245852 kb
Host smart-79087e64-3b6d-4878-9d9f-c6d74affe8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997810123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2997810123
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3474448811
Short name T1247
Test name
Test status
Simulation time 147466948 ps
CPU time 5.24 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 10:15:00 PM PST 24
Peak memory 238744 kb
Host smart-7aa69706-dcd3-48a7-bcdb-abc177ca56af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474448811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3474448811
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.927906215
Short name T543
Test name
Test status
Simulation time 2014760287 ps
CPU time 14.22 seconds
Started Jan 21 10:35:43 PM PST 24
Finished Jan 21 10:36:07 PM PST 24
Peak memory 245656 kb
Host smart-1144ffcc-2123-4528-9e0f-62693a256126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927906215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.927906215
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3472809216
Short name T970
Test name
Test status
Simulation time 329922466 ps
CPU time 7.58 seconds
Started Jan 21 10:14:48 PM PST 24
Finished Jan 21 10:15:05 PM PST 24
Peak memory 238748 kb
Host smart-116504d5-949d-42d1-a849-2c0887176c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472809216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3472809216
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.2240665423
Short name T678
Test name
Test status
Simulation time 164780473 ps
CPU time 2.8 seconds
Started Jan 21 10:14:42 PM PST 24
Finished Jan 21 10:14:58 PM PST 24
Peak memory 238588 kb
Host smart-dc7e1ed5-d4ac-478f-b88a-87d6edead8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240665423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2240665423
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.1604548028
Short name T617
Test name
Test status
Simulation time 398669564 ps
CPU time 6.83 seconds
Started Jan 21 10:14:43 PM PST 24
Finished Jan 21 10:15:02 PM PST 24
Peak memory 238788 kb
Host smart-d3bf6048-2f8d-4010-93e8-e9a6e30a2046
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604548028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.1604548028
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2027667668
Short name T501
Test name
Test status
Simulation time 1603081745 ps
CPU time 3.8 seconds
Started Jan 21 10:14:47 PM PST 24
Finished Jan 21 10:15:02 PM PST 24
Peak memory 238836 kb
Host smart-956b7734-43d1-40e3-91c5-ad17299aaa05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027667668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2027667668
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.4129307134
Short name T836
Test name
Test status
Simulation time 260305971 ps
CPU time 2.73 seconds
Started Jan 21 10:14:41 PM PST 24
Finished Jan 21 10:14:57 PM PST 24
Peak memory 241148 kb
Host smart-930a18a4-e2a1-4fd1-8ec6-d126ca18322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129307134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.4129307134
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.4267801637
Short name T979
Test name
Test status
Simulation time 165592628 ps
CPU time 3.69 seconds
Started Jan 21 10:21:05 PM PST 24
Finished Jan 21 10:21:21 PM PST 24
Peak memory 238720 kb
Host smart-ac9f0ef1-8dc3-4727-befc-e4c2264cb428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267801637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.4267801637
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.4131217057
Short name T909
Test name
Test status
Simulation time 143961976 ps
CPU time 3.9 seconds
Started Jan 21 10:20:57 PM PST 24
Finished Jan 21 10:21:18 PM PST 24
Peak memory 238644 kb
Host smart-22765a13-0ae6-48cb-80fb-5c04432989d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131217057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.4131217057
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.3781417914
Short name T585
Test name
Test status
Simulation time 113242540 ps
CPU time 3.96 seconds
Started Jan 21 10:20:58 PM PST 24
Finished Jan 21 10:21:17 PM PST 24
Peak memory 240932 kb
Host smart-9c79d8f0-1269-4e60-8f93-1e1782998e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781417914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.3781417914
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1480024010
Short name T895
Test name
Test status
Simulation time 1492620009 ps
CPU time 4.11 seconds
Started Jan 21 10:20:56 PM PST 24
Finished Jan 21 10:21:18 PM PST 24
Peak memory 238808 kb
Host smart-634ea213-e88f-40bb-9417-f4e2f91122ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480024010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1480024010
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.1210552814
Short name T1151
Test name
Test status
Simulation time 268928389 ps
CPU time 4.88 seconds
Started Jan 21 10:21:05 PM PST 24
Finished Jan 21 10:21:22 PM PST 24
Peak memory 240736 kb
Host smart-369c720b-0682-47e0-9c86-1bfb4533ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210552814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1210552814
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3355169437
Short name T1257
Test name
Test status
Simulation time 298672481 ps
CPU time 4.1 seconds
Started Jan 21 10:20:58 PM PST 24
Finished Jan 21 10:21:18 PM PST 24
Peak memory 238916 kb
Host smart-d274b449-f734-42f0-9abf-203870973898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355169437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3355169437
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.1226608275
Short name T131
Test name
Test status
Simulation time 156167575 ps
CPU time 3.72 seconds
Started Jan 21 10:21:00 PM PST 24
Finished Jan 21 10:21:19 PM PST 24
Peak memory 238728 kb
Host smart-76d67904-7330-4bef-8f1e-03ce7f534b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226608275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1226608275
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.4207372470
Short name T65
Test name
Test status
Simulation time 632631914 ps
CPU time 4.87 seconds
Started Jan 21 10:20:56 PM PST 24
Finished Jan 21 10:21:19 PM PST 24
Peak memory 241324 kb
Host smart-c271f209-1c05-4f14-830a-45edc71ffde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207372470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.4207372470
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1685868308
Short name T880
Test name
Test status
Simulation time 221230780 ps
CPU time 4.32 seconds
Started Jan 21 10:21:07 PM PST 24
Finished Jan 21 10:21:23 PM PST 24
Peak memory 246872 kb
Host smart-5e4d5711-5f25-4dea-a12f-25021beed46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685868308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1685868308
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2991952740
Short name T905
Test name
Test status
Simulation time 694988729 ps
CPU time 2.11 seconds
Started Jan 21 10:14:56 PM PST 24
Finished Jan 21 10:15:21 PM PST 24
Peak memory 238756 kb
Host smart-889e1988-7b35-402c-97b4-717bcd2d3f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991952740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2991952740
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.1914156379
Short name T62
Test name
Test status
Simulation time 1871284604 ps
CPU time 10.25 seconds
Started Jan 21 10:14:48 PM PST 24
Finished Jan 21 10:15:08 PM PST 24
Peak memory 245104 kb
Host smart-ac38eb51-bbd6-4af8-9079-bd1256da4427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914156379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1914156379
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.2334738572
Short name T454
Test name
Test status
Simulation time 635089448 ps
CPU time 15.3 seconds
Started Jan 21 10:14:46 PM PST 24
Finished Jan 21 10:15:12 PM PST 24
Peak memory 238840 kb
Host smart-9d880ee7-82c9-47eb-990e-4ac39a3b95f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334738572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.2334738572
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3021636177
Short name T1134
Test name
Test status
Simulation time 268950670 ps
CPU time 7.28 seconds
Started Jan 21 10:14:57 PM PST 24
Finished Jan 21 10:15:27 PM PST 24
Peak memory 238660 kb
Host smart-6b91f07d-6dd5-4b63-a79a-34f5ed772cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021636177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3021636177
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.2884855800
Short name T557
Test name
Test status
Simulation time 441483086 ps
CPU time 4.97 seconds
Started Jan 21 10:23:24 PM PST 24
Finished Jan 21 10:23:35 PM PST 24
Peak memory 238736 kb
Host smart-df36b2ba-395c-482f-8c65-3fbe2dba2f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884855800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2884855800
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1006275505
Short name T542
Test name
Test status
Simulation time 5847678793 ps
CPU time 14 seconds
Started Jan 21 10:14:57 PM PST 24
Finished Jan 21 10:15:33 PM PST 24
Peak memory 238792 kb
Host smart-03245a95-fdd8-4bf2-b9a7-e1d11451d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006275505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1006275505
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.755629207
Short name T856
Test name
Test status
Simulation time 2713217595 ps
CPU time 19.23 seconds
Started Jan 21 10:14:57 PM PST 24
Finished Jan 21 10:15:39 PM PST 24
Peak memory 244244 kb
Host smart-5c1e3256-9cbb-4f9b-bef4-2ab2ab23bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755629207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.755629207
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.273853341
Short name T823
Test name
Test status
Simulation time 1007005052 ps
CPU time 7.09 seconds
Started Jan 21 10:14:45 PM PST 24
Finished Jan 21 10:15:03 PM PST 24
Peak memory 244148 kb
Host smart-3e062009-5212-4d79-b855-5477a3ba21e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273853341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.273853341
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1007744405
Short name T551
Test name
Test status
Simulation time 244099049 ps
CPU time 6.87 seconds
Started Jan 21 10:14:48 PM PST 24
Finished Jan 21 10:15:05 PM PST 24
Peak memory 238800 kb
Host smart-c504a9ad-eff6-4733-84a5-68149ef62516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1007744405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1007744405
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.1327008899
Short name T457
Test name
Test status
Simulation time 1740880350 ps
CPU time 5.07 seconds
Started Jan 21 10:14:57 PM PST 24
Finished Jan 21 10:15:24 PM PST 24
Peak memory 241488 kb
Host smart-d85fa99c-d6d2-45a9-8344-d7068843bb7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327008899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1327008899
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1312586092
Short name T788
Test name
Test status
Simulation time 298129575 ps
CPU time 6.61 seconds
Started Jan 21 10:14:50 PM PST 24
Finished Jan 21 10:15:05 PM PST 24
Peak memory 238784 kb
Host smart-9119b3e9-a6d0-4d59-b439-01c9e443e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312586092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1312586092
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.4015749175
Short name T365
Test name
Test status
Simulation time 10628937183 ps
CPU time 21.59 seconds
Started Jan 21 10:15:00 PM PST 24
Finished Jan 21 10:15:43 PM PST 24
Peak memory 238836 kb
Host smart-dc22a0d9-53a2-479a-b901-314aa0626f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015749175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.4015749175
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.2279004554
Short name T296
Test name
Test status
Simulation time 634704077310 ps
CPU time 7622.53 seconds
Started Jan 21 10:14:47 PM PST 24
Finished Jan 22 12:22:01 AM PST 24
Peak memory 290100 kb
Host smart-0cb71086-40b7-4ff5-b807-19298a2fec13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279004554 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.2279004554
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.2936076490
Short name T368
Test name
Test status
Simulation time 1486897979 ps
CPU time 16.81 seconds
Started Jan 21 10:14:48 PM PST 24
Finished Jan 21 10:15:15 PM PST 24
Peak memory 244248 kb
Host smart-1a34f220-0935-438c-b4af-97065e2bb5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936076490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2936076490
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2060021644
Short name T754
Test name
Test status
Simulation time 395288240 ps
CPU time 4.39 seconds
Started Jan 21 10:21:06 PM PST 24
Finished Jan 21 10:21:21 PM PST 24
Peak memory 238696 kb
Host smart-599a4771-58f6-48ac-a25e-84aab642d974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060021644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2060021644
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.3004121174
Short name T133
Test name
Test status
Simulation time 246104993 ps
CPU time 3.98 seconds
Started Jan 21 10:21:04 PM PST 24
Finished Jan 21 10:21:21 PM PST 24
Peak memory 238804 kb
Host smart-4267b29a-cb11-47cc-91e2-98df9aaa8350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004121174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3004121174
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3065562358
Short name T528
Test name
Test status
Simulation time 305401752 ps
CPU time 4.38 seconds
Started Jan 21 10:21:05 PM PST 24
Finished Jan 21 10:21:21 PM PST 24
Peak memory 238772 kb
Host smart-20d4a873-0722-4643-b217-4174461dea24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065562358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3065562358
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.76793806
Short name T145
Test name
Test status
Simulation time 335517281 ps
CPU time 3.15 seconds
Started Jan 21 10:21:06 PM PST 24
Finished Jan 21 10:21:20 PM PST 24
Peak memory 238796 kb
Host smart-32f4fad6-2a9f-482c-935c-e664efabec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76793806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.76793806
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.1852756515
Short name T50
Test name
Test status
Simulation time 131817347 ps
CPU time 3.44 seconds
Started Jan 21 10:21:08 PM PST 24
Finished Jan 21 10:21:23 PM PST 24
Peak memory 238732 kb
Host smart-68f492f5-5fea-4629-bd8c-dc1f5f398bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852756515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1852756515
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.4046056510
Short name T1114
Test name
Test status
Simulation time 211139003 ps
CPU time 4.34 seconds
Started Jan 21 10:21:07 PM PST 24
Finished Jan 21 10:21:23 PM PST 24
Peak memory 246888 kb
Host smart-cf304d2b-86b9-4e69-b4b4-dbe20cc26cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046056510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.4046056510
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.455400590
Short name T496
Test name
Test status
Simulation time 454003904 ps
CPU time 4.14 seconds
Started Jan 21 10:21:05 PM PST 24
Finished Jan 21 10:21:21 PM PST 24
Peak memory 238672 kb
Host smart-6ddee7df-c434-486b-87f9-64fcb50b33d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455400590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.455400590
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.1222451703
Short name T809
Test name
Test status
Simulation time 296637629 ps
CPU time 4.71 seconds
Started Jan 21 10:21:06 PM PST 24
Finished Jan 21 10:21:22 PM PST 24
Peak memory 241080 kb
Host smart-71a2aa61-d5b4-4506-8fee-a88d7e731765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222451703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1222451703
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.1258372519
Short name T1195
Test name
Test status
Simulation time 1407806239 ps
CPU time 4.03 seconds
Started Jan 21 10:21:09 PM PST 24
Finished Jan 21 10:21:24 PM PST 24
Peak memory 246924 kb
Host smart-f83283b4-10d3-4ff1-9a4b-9847cd1131bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258372519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1258372519
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.717816764
Short name T703
Test name
Test status
Simulation time 159950432 ps
CPU time 4.09 seconds
Started Jan 21 10:21:09 PM PST 24
Finished Jan 21 10:21:26 PM PST 24
Peak memory 238788 kb
Host smart-6be3ddff-cb80-4b25-a4cc-336869b98602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717816764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.717816764
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.612191350
Short name T475
Test name
Test status
Simulation time 139525603 ps
CPU time 1.89 seconds
Started Jan 21 10:11:59 PM PST 24
Finished Jan 21 10:12:03 PM PST 24
Peak memory 239616 kb
Host smart-77219ff6-e66e-459a-b192-1d562e0641a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612191350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.612191350
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.1544134162
Short name T1098
Test name
Test status
Simulation time 574424082 ps
CPU time 11.6 seconds
Started Jan 21 10:11:57 PM PST 24
Finished Jan 21 10:12:10 PM PST 24
Peak memory 238812 kb
Host smart-931659af-d97b-4cb6-ac7d-7be099377122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544134162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1544134162
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.3308939546
Short name T53
Test name
Test status
Simulation time 244872833 ps
CPU time 4.81 seconds
Started Jan 21 10:11:46 PM PST 24
Finished Jan 21 10:11:52 PM PST 24
Peak memory 238908 kb
Host smart-3f55a9d2-4730-47ed-bb08-d288c5acd891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308939546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3308939546
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.3565086424
Short name T904
Test name
Test status
Simulation time 690437127 ps
CPU time 8.13 seconds
Started Jan 21 10:11:51 PM PST 24
Finished Jan 21 10:12:02 PM PST 24
Peak memory 243536 kb
Host smart-39fadfc4-539f-42c4-9dd2-5b9cab5e191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565086424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3565086424
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.1485209733
Short name T106
Test name
Test status
Simulation time 201415588 ps
CPU time 3.54 seconds
Started Jan 21 10:11:48 PM PST 24
Finished Jan 21 10:11:54 PM PST 24
Peak memory 243736 kb
Host smart-2a96b2b0-12fc-4383-8935-8ada844ffa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485209733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1485209733
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.4282957084
Short name T67
Test name
Test status
Simulation time 111451662 ps
CPU time 4.63 seconds
Started Jan 21 10:11:50 PM PST 24
Finished Jan 21 10:11:58 PM PST 24
Peak memory 241140 kb
Host smart-dcf3bfac-3d05-4921-961c-78cf85b04e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282957084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.4282957084
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.4022869376
Short name T303
Test name
Test status
Simulation time 411415319 ps
CPU time 6.53 seconds
Started Jan 21 10:11:49 PM PST 24
Finished Jan 21 10:11:58 PM PST 24
Peak memory 238732 kb
Host smart-37311984-9b5d-4e0c-a128-3979db0224b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022869376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.4022869376
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1927813048
Short name T725
Test name
Test status
Simulation time 1994624988 ps
CPU time 5.43 seconds
Started Jan 21 10:11:48 PM PST 24
Finished Jan 21 10:11:56 PM PST 24
Peak memory 238752 kb
Host smart-9e3947d2-2c20-4ec1-800f-92ffe48a3685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927813048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1927813048
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2523359318
Short name T999
Test name
Test status
Simulation time 447228210 ps
CPU time 6.47 seconds
Started Jan 21 10:11:49 PM PST 24
Finished Jan 21 10:11:58 PM PST 24
Peak memory 243232 kb
Host smart-7860752b-3f2b-402c-841d-fd347eb12b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523359318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2523359318
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1162843972
Short name T1196
Test name
Test status
Simulation time 312420145 ps
CPU time 8.27 seconds
Started Jan 21 10:11:49 PM PST 24
Finished Jan 21 10:12:00 PM PST 24
Peak memory 238732 kb
Host smart-ce216445-60e0-4fb2-bbbb-c63d5cfa918e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162843972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1162843972
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.260884900
Short name T332
Test name
Test status
Simulation time 489607880 ps
CPU time 6.21 seconds
Started Jan 21 10:11:48 PM PST 24
Finished Jan 21 10:11:57 PM PST 24
Peak memory 238844 kb
Host smart-9a928bcc-61ca-4123-aa82-935678ece928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260884900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.260884900
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.2840108962
Short name T21
Test name
Test status
Simulation time 144348151502 ps
CPU time 160.93 seconds
Started Jan 21 10:12:01 PM PST 24
Finished Jan 21 10:14:44 PM PST 24
Peak memory 268812 kb
Host smart-3de89c70-7c62-4869-8a6a-f87682c4fe6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840108962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.2840108962
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.1927135090
Short name T541
Test name
Test status
Simulation time 144666351 ps
CPU time 3.21 seconds
Started Jan 21 10:11:49 PM PST 24
Finished Jan 21 10:11:54 PM PST 24
Peak memory 238844 kb
Host smart-68ea9787-081a-4bcc-a3a6-1fcfcd316cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927135090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1927135090
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.1635727467
Short name T859
Test name
Test status
Simulation time 2480036155 ps
CPU time 24.91 seconds
Started Jan 21 10:11:58 PM PST 24
Finished Jan 21 10:12:24 PM PST 24
Peak memory 238952 kb
Host smart-26672d1b-62a9-4ac7-9375-23904bd801ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635727467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1635727467
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.1000150230
Short name T575
Test name
Test status
Simulation time 210944896 ps
CPU time 1.86 seconds
Started Jan 21 10:14:55 PM PST 24
Finished Jan 21 10:15:19 PM PST 24
Peak memory 239624 kb
Host smart-d2a5990a-4ae7-490b-bcda-6869e0bb19e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000150230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1000150230
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.617645545
Short name T299
Test name
Test status
Simulation time 3737444743 ps
CPU time 8.6 seconds
Started Jan 21 10:15:02 PM PST 24
Finished Jan 21 10:15:31 PM PST 24
Peak memory 238808 kb
Host smart-65a506c3-e631-44ca-be62-f010bd069754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617645545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.617645545
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.663442070
Short name T587
Test name
Test status
Simulation time 886653443 ps
CPU time 5.44 seconds
Started Jan 21 10:15:01 PM PST 24
Finished Jan 21 10:15:27 PM PST 24
Peak memory 241996 kb
Host smart-8b713e44-c6f9-42b7-843c-bb4908e3a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663442070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.663442070
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.2178761138
Short name T157
Test name
Test status
Simulation time 249088744 ps
CPU time 5.92 seconds
Started Jan 21 10:14:57 PM PST 24
Finished Jan 21 10:15:25 PM PST 24
Peak memory 244012 kb
Host smart-95487a42-6ca4-43ca-b56a-f5951ffe49e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178761138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2178761138
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.3747699226
Short name T1205
Test name
Test status
Simulation time 171298829 ps
CPU time 4.27 seconds
Started Jan 21 10:15:01 PM PST 24
Finished Jan 21 10:15:26 PM PST 24
Peak memory 238744 kb
Host smart-e466890d-ba54-4a4e-9ebe-d1c432d0bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747699226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3747699226
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.1483442840
Short name T139
Test name
Test status
Simulation time 2780654274 ps
CPU time 21.77 seconds
Started Jan 21 10:15:03 PM PST 24
Finished Jan 21 10:15:44 PM PST 24
Peak memory 238864 kb
Host smart-4a95b45e-3e1d-45a8-a444-71d91393bd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483442840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1483442840
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.1710032159
Short name T1135
Test name
Test status
Simulation time 9957008215 ps
CPU time 19.95 seconds
Started Jan 21 10:14:55 PM PST 24
Finished Jan 21 10:15:37 PM PST 24
Peak memory 238836 kb
Host smart-0400db0b-3c62-489c-8ec3-6e938decac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710032159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1710032159
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.2151328292
Short name T468
Test name
Test status
Simulation time 975625705 ps
CPU time 6.96 seconds
Started Jan 21 10:15:00 PM PST 24
Finished Jan 21 10:15:28 PM PST 24
Peak memory 238864 kb
Host smart-cdcce9f4-5f86-4790-b455-912c48c2e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151328292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.2151328292
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.3902819086
Short name T784
Test name
Test status
Simulation time 846795565 ps
CPU time 7.71 seconds
Started Jan 21 10:14:59 PM PST 24
Finished Jan 21 10:15:28 PM PST 24
Peak memory 238804 kb
Host smart-d60af2b1-3289-4038-a794-ab8d7fc21f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902819086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3902819086
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.4071938226
Short name T445
Test name
Test status
Simulation time 322686757 ps
CPU time 4.94 seconds
Started Jan 21 10:15:03 PM PST 24
Finished Jan 21 10:15:28 PM PST 24
Peak memory 238696 kb
Host smart-994004a8-1cbf-4db6-960c-1d94b0ab47b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071938226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.4071938226
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.3384155171
Short name T88
Test name
Test status
Simulation time 368148157 ps
CPU time 4.45 seconds
Started Jan 21 10:14:59 PM PST 24
Finished Jan 21 10:15:26 PM PST 24
Peak memory 238896 kb
Host smart-37424ccf-b60b-4946-85f3-2f4c3f8b3cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384155171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3384155171
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.862932560
Short name T367
Test name
Test status
Simulation time 6795918059 ps
CPU time 24.52 seconds
Started Jan 21 10:14:58 PM PST 24
Finished Jan 21 10:15:45 PM PST 24
Peak memory 238812 kb
Host smart-37754955-70cb-42f0-8f43-ba6403af9b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862932560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.
862932560
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.6005871
Short name T216
Test name
Test status
Simulation time 1757367132551 ps
CPU time 8412.87 seconds
Started Jan 21 10:15:02 PM PST 24
Finished Jan 22 12:35:36 AM PST 24
Peak memory 1206648 kb
Host smart-39e9f938-20e5-4029-a27e-3f5a3f41e41f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6005871 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.6005871
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.3234214718
Short name T978
Test name
Test status
Simulation time 1584280165 ps
CPU time 13.93 seconds
Started Jan 21 10:14:55 PM PST 24
Finished Jan 21 10:15:32 PM PST 24
Peak memory 243944 kb
Host smart-2b94e161-1ec5-4cdb-98a3-42f914d41f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234214718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.3234214718
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.978290536
Short name T981
Test name
Test status
Simulation time 115383436 ps
CPU time 2.02 seconds
Started Jan 21 10:15:05 PM PST 24
Finished Jan 21 10:15:26 PM PST 24
Peak memory 230412 kb
Host smart-cd93dbe9-ac4c-4bdf-be9d-ee6271e04b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978290536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.978290536
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.154728087
Short name T1011
Test name
Test status
Simulation time 1004136978 ps
CPU time 8.87 seconds
Started Jan 21 10:15:10 PM PST 24
Finished Jan 21 10:15:35 PM PST 24
Peak memory 238660 kb
Host smart-20a0a414-6428-4a10-9157-dd670962ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154728087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.154728087
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.3035146720
Short name T1076
Test name
Test status
Simulation time 1858768490 ps
CPU time 13.38 seconds
Started Jan 21 10:15:07 PM PST 24
Finished Jan 21 10:15:40 PM PST 24
Peak memory 246980 kb
Host smart-a4879de2-c24a-484b-bd85-b11c3d26a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035146720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.3035146720
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.1906329884
Short name T372
Test name
Test status
Simulation time 14887743594 ps
CPU time 19.13 seconds
Started Jan 21 10:14:59 PM PST 24
Finished Jan 21 10:15:40 PM PST 24
Peak memory 247048 kb
Host smart-643023a7-3311-479f-b2f9-0a62d8eacac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906329884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1906329884
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.4243656573
Short name T134
Test name
Test status
Simulation time 1810081818 ps
CPU time 5.67 seconds
Started Jan 21 10:14:57 PM PST 24
Finished Jan 21 10:15:26 PM PST 24
Peak memory 238736 kb
Host smart-b8055d95-afb1-47a5-b7b9-0300d210fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243656573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.4243656573
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.204568918
Short name T865
Test name
Test status
Simulation time 470939801 ps
CPU time 10.01 seconds
Started Jan 21 10:15:07 PM PST 24
Finished Jan 21 10:15:35 PM PST 24
Peak memory 238744 kb
Host smart-7f7875ff-4e28-4fbc-87d6-b84925eda20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204568918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.204568918
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.2627008105
Short name T1059
Test name
Test status
Simulation time 376903921 ps
CPU time 7.5 seconds
Started Jan 21 10:15:05 PM PST 24
Finished Jan 21 10:15:32 PM PST 24
Peak memory 238772 kb
Host smart-c555b82e-c4eb-4c80-82aa-3d3705ade16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627008105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2627008105
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1309905505
Short name T767
Test name
Test status
Simulation time 484729828 ps
CPU time 5.22 seconds
Started Jan 21 10:14:55 PM PST 24
Finished Jan 21 10:15:22 PM PST 24
Peak memory 243584 kb
Host smart-f265ce33-1c05-4025-b1e7-c8898e4f4dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309905505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1309905505
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.149865316
Short name T526
Test name
Test status
Simulation time 799461399 ps
CPU time 10.8 seconds
Started Jan 21 10:14:58 PM PST 24
Finished Jan 21 10:15:31 PM PST 24
Peak memory 242756 kb
Host smart-908f71a3-6ff9-4853-ba98-d3d1b819f662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149865316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.149865316
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.4124786402
Short name T881
Test name
Test status
Simulation time 917095750 ps
CPU time 6.93 seconds
Started Jan 21 10:15:08 PM PST 24
Finished Jan 21 10:15:33 PM PST 24
Peak memory 243360 kb
Host smart-5aa53395-1b5d-4625-9906-42fc773238a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124786402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.4124786402
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.888942615
Short name T480
Test name
Test status
Simulation time 145980868 ps
CPU time 4.44 seconds
Started Jan 21 10:14:57 PM PST 24
Finished Jan 21 10:15:24 PM PST 24
Peak memory 246904 kb
Host smart-6dba43e2-2d56-4097-afaf-658a91a92d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888942615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.888942615
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.1176713802
Short name T375
Test name
Test status
Simulation time 284233840967 ps
CPU time 1561.07 seconds
Started Jan 21 10:15:04 PM PST 24
Finished Jan 21 10:41:25 PM PST 24
Peak memory 263180 kb
Host smart-26fc6f07-698d-4038-a46a-20ac1bf2d2f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176713802 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.1176713802
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.2303757504
Short name T946
Test name
Test status
Simulation time 4477791255 ps
CPU time 12.28 seconds
Started Jan 21 10:15:05 PM PST 24
Finished Jan 21 10:15:36 PM PST 24
Peak memory 247032 kb
Host smart-54ca0301-fa6d-4c89-84fc-82e7397eb453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303757504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2303757504
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.1669787006
Short name T630
Test name
Test status
Simulation time 145677731 ps
CPU time 1.54 seconds
Started Jan 21 10:15:13 PM PST 24
Finished Jan 21 10:15:32 PM PST 24
Peak memory 230528 kb
Host smart-05f942e2-f419-48ef-a75b-c3aa5a4c6192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669787006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1669787006
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1324734157
Short name T1231
Test name
Test status
Simulation time 92448212 ps
CPU time 2.56 seconds
Started Jan 21 10:15:14 PM PST 24
Finished Jan 21 10:15:35 PM PST 24
Peak memory 238772 kb
Host smart-ca607e54-4ce7-4e0e-9f72-2bae7a23288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324734157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1324734157
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.1723232938
Short name T304
Test name
Test status
Simulation time 856438393 ps
CPU time 12.38 seconds
Started Jan 21 10:15:14 PM PST 24
Finished Jan 21 10:15:46 PM PST 24
Peak memory 245840 kb
Host smart-82794086-4dcd-4fba-8b99-28218ffc9d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723232938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1723232938
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.1729509287
Short name T896
Test name
Test status
Simulation time 307619803 ps
CPU time 6.18 seconds
Started Jan 21 10:15:14 PM PST 24
Finished Jan 21 10:15:40 PM PST 24
Peak memory 241588 kb
Host smart-06821654-c5ca-45e9-b963-9dfe1e79489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729509287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1729509287
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.2057750670
Short name T1013
Test name
Test status
Simulation time 172166921 ps
CPU time 3.15 seconds
Started Jan 21 10:15:12 PM PST 24
Finished Jan 21 10:15:32 PM PST 24
Peak memory 238780 kb
Host smart-261c8490-01b8-449c-8487-6a3be2b69129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057750670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2057750670
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.2217101684
Short name T1209
Test name
Test status
Simulation time 3274879981 ps
CPU time 5.05 seconds
Started Jan 21 10:15:14 PM PST 24
Finished Jan 21 10:15:39 PM PST 24
Peak memory 238812 kb
Host smart-b595f48d-e1eb-4b54-8e81-0a6d924979e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217101684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2217101684
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.122076475
Short name T1027
Test name
Test status
Simulation time 7023093301 ps
CPU time 18.08 seconds
Started Jan 21 10:15:11 PM PST 24
Finished Jan 21 10:15:46 PM PST 24
Peak memory 238856 kb
Host smart-61dea663-c1ac-4e20-bdc5-7534afbccb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122076475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.122076475
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.249149859
Short name T601
Test name
Test status
Simulation time 488507935 ps
CPU time 5.37 seconds
Started Jan 21 10:15:13 PM PST 24
Finished Jan 21 10:15:38 PM PST 24
Peak memory 243256 kb
Host smart-c2086ff0-f662-413b-9b60-61f005589b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249149859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.249149859
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.2386764576
Short name T1064
Test name
Test status
Simulation time 790169489 ps
CPU time 18.36 seconds
Started Jan 21 10:15:09 PM PST 24
Finished Jan 21 10:15:45 PM PST 24
Peak memory 238744 kb
Host smart-a33b8d48-985e-4faf-9e9a-b0a6d1f0ddc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386764576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.2386764576
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1636582366
Short name T1219
Test name
Test status
Simulation time 292424189 ps
CPU time 4.41 seconds
Started Jan 21 10:15:08 PM PST 24
Finished Jan 21 10:15:30 PM PST 24
Peak memory 241228 kb
Host smart-076aec0c-66be-4306-8f6f-61703459fb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636582366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1636582366
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.318301107
Short name T782
Test name
Test status
Simulation time 3987901250 ps
CPU time 38.04 seconds
Started Jan 21 10:15:08 PM PST 24
Finished Jan 21 10:16:04 PM PST 24
Peak memory 239628 kb
Host smart-3c5fa62c-6b2c-4a15-b653-a6c6ab237b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318301107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
318301107
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.1801268471
Short name T294
Test name
Test status
Simulation time 728007333967 ps
CPU time 9977.73 seconds
Started Jan 21 10:15:19 PM PST 24
Finished Jan 22 01:01:57 AM PST 24
Peak memory 888924 kb
Host smart-22dca468-bdd9-442f-8004-3275e6fcc087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801268471 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.1801268471
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.3075970688
Short name T100
Test name
Test status
Simulation time 15454597300 ps
CPU time 42.99 seconds
Started Jan 21 10:15:14 PM PST 24
Finished Jan 21 10:16:16 PM PST 24
Peak memory 238856 kb
Host smart-d60677c8-dae4-43ae-b53a-89a9497f2fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075970688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3075970688
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.303327627
Short name T1162
Test name
Test status
Simulation time 67187346 ps
CPU time 1.78 seconds
Started Jan 21 10:15:18 PM PST 24
Finished Jan 21 10:15:40 PM PST 24
Peak memory 239708 kb
Host smart-109516b1-05ff-4ee7-a3cf-c9d419c6d58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303327627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.303327627
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.1813266511
Short name T616
Test name
Test status
Simulation time 1028399222 ps
CPU time 13.5 seconds
Started Jan 21 10:55:07 PM PST 24
Finished Jan 21 10:55:24 PM PST 24
Peak memory 238836 kb
Host smart-879d3eab-37fe-42a1-b58f-70c574d9ee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813266511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.1813266511
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.750980088
Short name T711
Test name
Test status
Simulation time 3653107397 ps
CPU time 11.27 seconds
Started Jan 21 10:15:18 PM PST 24
Finished Jan 21 10:15:49 PM PST 24
Peak memory 238860 kb
Host smart-add5f610-0ee8-4387-bcf8-d077dfc4e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750980088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.750980088
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.2266616220
Short name T632
Test name
Test status
Simulation time 182948233 ps
CPU time 4.06 seconds
Started Jan 21 10:15:12 PM PST 24
Finished Jan 21 10:15:34 PM PST 24
Peak memory 238668 kb
Host smart-7b4d7440-1afc-4b49-ba79-220a555593a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266616220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2266616220
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.659240009
Short name T1149
Test name
Test status
Simulation time 545811582 ps
CPU time 4.22 seconds
Started Jan 21 10:15:10 PM PST 24
Finished Jan 21 10:15:31 PM PST 24
Peak memory 241364 kb
Host smart-13576c3f-fe5e-456d-baa8-55b6ea9eac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659240009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.659240009
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.3480585151
Short name T119
Test name
Test status
Simulation time 931719734 ps
CPU time 10.83 seconds
Started Jan 21 10:15:14 PM PST 24
Finished Jan 21 10:15:45 PM PST 24
Peak memory 238780 kb
Host smart-599dfb05-8f0a-49d3-a83f-b7aacc8b0c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480585151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3480585151
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2361567385
Short name T1255
Test name
Test status
Simulation time 1359929744 ps
CPU time 14.52 seconds
Started Jan 21 10:15:21 PM PST 24
Finished Jan 21 10:15:54 PM PST 24
Peak memory 238788 kb
Host smart-a24d32d9-ea20-4d07-ac63-8df981fbc2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361567385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2361567385
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3658707732
Short name T699
Test name
Test status
Simulation time 183386268 ps
CPU time 4.77 seconds
Started Jan 21 10:15:13 PM PST 24
Finished Jan 21 10:15:36 PM PST 24
Peak memory 242468 kb
Host smart-9e78f54d-4f8d-4403-bf1a-08cf6102dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658707732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3658707732
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1285895645
Short name T588
Test name
Test status
Simulation time 701868875 ps
CPU time 15.33 seconds
Started Jan 21 10:15:12 PM PST 24
Finished Jan 21 10:15:45 PM PST 24
Peak memory 238784 kb
Host smart-08843349-845c-47c0-8c50-e59250550138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285895645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1285895645
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.549498591
Short name T945
Test name
Test status
Simulation time 116301051 ps
CPU time 3.75 seconds
Started Jan 21 10:15:22 PM PST 24
Finished Jan 21 10:15:44 PM PST 24
Peak memory 238852 kb
Host smart-11c32537-cb23-46a2-9496-c9b3d444b518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549498591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.549498591
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.83418328
Short name T737
Test name
Test status
Simulation time 160282859 ps
CPU time 3.95 seconds
Started Jan 21 10:15:10 PM PST 24
Finished Jan 21 10:15:31 PM PST 24
Peak memory 246944 kb
Host smart-6e4622ae-75e9-4622-9cb1-60487dbdce5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83418328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.83418328
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2609481647
Short name T1080
Test name
Test status
Simulation time 21874931122 ps
CPU time 92.6 seconds
Started Jan 21 10:15:21 PM PST 24
Finished Jan 21 10:17:12 PM PST 24
Peak memory 240324 kb
Host smart-dba4b2af-63a4-48ac-a969-ddc8101b216b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609481647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2609481647
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2658291546
Short name T269
Test name
Test status
Simulation time 373206645696 ps
CPU time 3992.54 seconds
Started Jan 21 10:15:22 PM PST 24
Finished Jan 21 11:22:14 PM PST 24
Peak memory 255324 kb
Host smart-1828f5dc-aae1-40d7-a610-b2f6ca5566c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658291546 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.2658291546
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.2157098004
Short name T785
Test name
Test status
Simulation time 7345096187 ps
CPU time 20.87 seconds
Started Jan 21 10:15:22 PM PST 24
Finished Jan 21 10:16:02 PM PST 24
Peak memory 238780 kb
Host smart-023c6047-1db5-427e-901a-e048215d1172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157098004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2157098004
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3252110463
Short name T517
Test name
Test status
Simulation time 845911715 ps
CPU time 2.72 seconds
Started Jan 21 10:15:22 PM PST 24
Finished Jan 21 10:15:44 PM PST 24
Peak memory 239576 kb
Host smart-6b42367d-fd9b-485c-958a-b2c38602b9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252110463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3252110463
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3379403885
Short name T902
Test name
Test status
Simulation time 1622290254 ps
CPU time 14.83 seconds
Started Jan 21 10:15:26 PM PST 24
Finished Jan 21 10:15:57 PM PST 24
Peak memory 238840 kb
Host smart-c252eb98-73e4-4d72-a4ae-418a401c7267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379403885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3379403885
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.2344742026
Short name T9
Test name
Test status
Simulation time 200168539 ps
CPU time 8.27 seconds
Started Jan 21 10:15:19 PM PST 24
Finished Jan 21 10:15:47 PM PST 24
Peak memory 243372 kb
Host smart-aff85074-97a4-4851-b36a-0d2af590a950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344742026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.2344742026
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.2651424682
Short name T714
Test name
Test status
Simulation time 946077546 ps
CPU time 5.93 seconds
Started Jan 21 10:15:25 PM PST 24
Finished Jan 21 10:15:48 PM PST 24
Peak memory 241024 kb
Host smart-fba19b09-d551-4014-bc43-a5b3faa664de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651424682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.2651424682
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.537667983
Short name T693
Test name
Test status
Simulation time 6809059871 ps
CPU time 14.39 seconds
Started Jan 21 10:15:22 PM PST 24
Finished Jan 21 10:15:55 PM PST 24
Peak memory 245612 kb
Host smart-cda9f29c-7b1b-45f2-b32c-0a61cc1b4b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537667983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.537667983
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.754971669
Short name T357
Test name
Test status
Simulation time 2912950554 ps
CPU time 16.43 seconds
Started Jan 21 10:15:19 PM PST 24
Finished Jan 21 10:15:55 PM PST 24
Peak memory 238904 kb
Host smart-51c25d5c-8b92-431b-8a9d-987749cd2cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754971669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.754971669
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.460286644
Short name T497
Test name
Test status
Simulation time 1383036400 ps
CPU time 4.66 seconds
Started Jan 21 10:15:20 PM PST 24
Finished Jan 21 10:15:44 PM PST 24
Peak memory 230616 kb
Host smart-f71802a1-7faa-4d21-919d-17a3ce382520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460286644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.460286644
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.1328376650
Short name T6
Test name
Test status
Simulation time 1058078433 ps
CPU time 15.14 seconds
Started Jan 21 10:15:21 PM PST 24
Finished Jan 21 10:15:55 PM PST 24
Peak memory 238796 kb
Host smart-27c3c50e-5662-43be-bd17-150ff91e5275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328376650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1328376650
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.3852259760
Short name T885
Test name
Test status
Simulation time 442223896 ps
CPU time 7.52 seconds
Started Jan 21 10:15:20 PM PST 24
Finished Jan 21 10:15:47 PM PST 24
Peak memory 243264 kb
Host smart-525271aa-978a-411d-8dc2-2a459abcd21a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852259760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.3852259760
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.819017952
Short name T817
Test name
Test status
Simulation time 122211029 ps
CPU time 2.79 seconds
Started Jan 21 10:15:21 PM PST 24
Finished Jan 21 10:15:43 PM PST 24
Peak memory 241216 kb
Host smart-c3a13e7d-19ae-41a4-a308-ea80e3a7ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819017952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.819017952
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.892461185
Short name T360
Test name
Test status
Simulation time 8593607986 ps
CPU time 52.44 seconds
Started Jan 21 10:15:23 PM PST 24
Finished Jan 21 10:16:34 PM PST 24
Peak memory 239976 kb
Host smart-12fd717c-2f40-48fd-8453-1ff2131153ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892461185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.
892461185
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.617621642
Short name T226
Test name
Test status
Simulation time 231246298 ps
CPU time 5.15 seconds
Started Jan 21 10:15:23 PM PST 24
Finished Jan 21 10:15:47 PM PST 24
Peak memory 238704 kb
Host smart-8473bfc7-ddc1-4521-bb4c-17591fcaa702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617621642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.617621642
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.745307831
Short name T458
Test name
Test status
Simulation time 65591600 ps
CPU time 1.89 seconds
Started Jan 21 10:15:26 PM PST 24
Finished Jan 21 10:15:44 PM PST 24
Peak memory 238988 kb
Host smart-4f41d2c8-d796-43ef-8351-9b65f26cea12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745307831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.745307831
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.381107747
Short name T852
Test name
Test status
Simulation time 442838274 ps
CPU time 10.83 seconds
Started Jan 21 10:15:25 PM PST 24
Finished Jan 21 10:15:53 PM PST 24
Peak memory 245232 kb
Host smart-71b8b8d3-e0c4-4584-86ba-db563bc59972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381107747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.381107747
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.1855775809
Short name T1031
Test name
Test status
Simulation time 612597429 ps
CPU time 10.83 seconds
Started Jan 21 10:15:25 PM PST 24
Finished Jan 21 10:15:53 PM PST 24
Peak memory 244964 kb
Host smart-32d02e01-3cf9-45a8-af29-61ff40b411d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855775809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1855775809
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1101680054
Short name T467
Test name
Test status
Simulation time 2055143943 ps
CPU time 5.44 seconds
Started Jan 21 10:15:18 PM PST 24
Finished Jan 21 10:15:44 PM PST 24
Peak memory 238680 kb
Host smart-e326bf42-5317-460a-bbda-f4aa44cd6b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101680054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1101680054
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.4285858127
Short name T792
Test name
Test status
Simulation time 760143811 ps
CPU time 14.57 seconds
Started Jan 21 11:11:46 PM PST 24
Finished Jan 21 11:12:01 PM PST 24
Peak memory 239984 kb
Host smart-478a098c-e362-48d4-b245-ad4aa7c36f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285858127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.4285858127
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.26919990
Short name T862
Test name
Test status
Simulation time 204380426 ps
CPU time 5.47 seconds
Started Jan 21 11:21:03 PM PST 24
Finished Jan 21 11:21:11 PM PST 24
Peak memory 238804 kb
Host smart-5e9602c4-5bc6-4dad-99c0-14dca3312628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26919990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.26919990
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.1328021299
Short name T1052
Test name
Test status
Simulation time 934670516 ps
CPU time 11.25 seconds
Started Jan 21 10:15:23 PM PST 24
Finished Jan 21 10:15:53 PM PST 24
Peak memory 243440 kb
Host smart-41489210-b315-40cd-a2a0-5132ca2b190e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328021299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1328021299
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.4164116116
Short name T732
Test name
Test status
Simulation time 401841700 ps
CPU time 6.62 seconds
Started Jan 21 10:15:27 PM PST 24
Finished Jan 21 10:15:50 PM PST 24
Peak memory 238696 kb
Host smart-da3d3c0d-8351-44cb-a420-efab4ea80db8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164116116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.4164116116
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1139046954
Short name T1041
Test name
Test status
Simulation time 1100260777 ps
CPU time 6.66 seconds
Started Jan 21 10:15:22 PM PST 24
Finished Jan 21 10:15:47 PM PST 24
Peak memory 246944 kb
Host smart-ec6b0a10-aa8b-458b-b8b8-786ebbfa1cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139046954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1139046954
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.3605434722
Short name T943
Test name
Test status
Simulation time 4029133664 ps
CPU time 22.89 seconds
Started Jan 21 10:15:24 PM PST 24
Finished Jan 21 10:16:05 PM PST 24
Peak memory 239824 kb
Host smart-0e1d5cd5-6afe-41fb-aeea-71026bdcec95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605434722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.3605434722
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3088359151
Short name T1186
Test name
Test status
Simulation time 1951113106879 ps
CPU time 3282.68 seconds
Started Jan 21 10:15:25 PM PST 24
Finished Jan 21 11:10:25 PM PST 24
Peak memory 276104 kb
Host smart-b5f50872-aa9f-4fd5-80d8-e210f10c31cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088359151 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.3088359151
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.4225223141
Short name T877
Test name
Test status
Simulation time 8413828977 ps
CPU time 24.39 seconds
Started Jan 21 10:15:29 PM PST 24
Finished Jan 21 10:16:08 PM PST 24
Peak memory 244188 kb
Host smart-89c8ed3e-9e72-4796-a960-4ca7c8ae07a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225223141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.4225223141
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.586468513
Short name T460
Test name
Test status
Simulation time 70557911 ps
CPU time 1.62 seconds
Started Jan 21 10:15:42 PM PST 24
Finished Jan 21 10:15:50 PM PST 24
Peak memory 230520 kb
Host smart-79b65636-6b59-4a31-905e-588390d3f2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586468513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.586468513
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.2095679495
Short name T47
Test name
Test status
Simulation time 2188515406 ps
CPU time 10.81 seconds
Started Jan 21 10:15:46 PM PST 24
Finished Jan 21 10:16:02 PM PST 24
Peak memory 238952 kb
Host smart-3cb089bd-ff22-4321-b626-77cceab56e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095679495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2095679495
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.248617686
Short name T1284
Test name
Test status
Simulation time 399679591 ps
CPU time 9.62 seconds
Started Jan 21 10:15:43 PM PST 24
Finished Jan 21 10:15:58 PM PST 24
Peak memory 244500 kb
Host smart-21e8cc14-7e7a-47eb-84cb-813bda640c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248617686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.248617686
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1372544955
Short name T702
Test name
Test status
Simulation time 1651177248 ps
CPU time 9.29 seconds
Started Jan 21 10:15:39 PM PST 24
Finished Jan 21 10:15:57 PM PST 24
Peak memory 238760 kb
Host smart-ae155d63-89ce-45cf-8708-90433504bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372544955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1372544955
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3169857161
Short name T76
Test name
Test status
Simulation time 315257518 ps
CPU time 4.07 seconds
Started Jan 21 10:15:28 PM PST 24
Finished Jan 21 10:15:47 PM PST 24
Peak memory 240724 kb
Host smart-edc3fae1-9ec4-4484-afed-55ad1c21b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169857161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3169857161
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.1767625231
Short name T1172
Test name
Test status
Simulation time 13542509720 ps
CPU time 22.83 seconds
Started Jan 21 10:15:44 PM PST 24
Finished Jan 21 10:16:13 PM PST 24
Peak memory 247060 kb
Host smart-a903ff18-3d82-4259-8211-541e595b4d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767625231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1767625231
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1565410424
Short name T717
Test name
Test status
Simulation time 918228502 ps
CPU time 7.11 seconds
Started Jan 21 10:15:39 PM PST 24
Finished Jan 21 10:15:55 PM PST 24
Peak memory 244020 kb
Host smart-aaa7e5f1-e3cf-408e-bbbe-cf40358de7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565410424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1565410424
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.3674396196
Short name T1088
Test name
Test status
Simulation time 500094532 ps
CPU time 3.59 seconds
Started Jan 21 10:15:44 PM PST 24
Finished Jan 21 10:15:54 PM PST 24
Peak memory 241044 kb
Host smart-2c2a699f-7d82-473c-b1e3-0c4d173aa61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674396196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3674396196
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.1464762620
Short name T481
Test name
Test status
Simulation time 379138132 ps
CPU time 7.35 seconds
Started Jan 21 11:22:15 PM PST 24
Finished Jan 21 11:22:31 PM PST 24
Peak memory 238768 kb
Host smart-2d8cd2d7-1ac9-42ef-be96-e4d1c6c86355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464762620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1464762620
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.138996488
Short name T755
Test name
Test status
Simulation time 2025215673 ps
CPU time 6.15 seconds
Started Jan 21 10:15:42 PM PST 24
Finished Jan 21 10:15:55 PM PST 24
Peak memory 238732 kb
Host smart-78dd21c2-c86c-46dc-86c2-234698566cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138996488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.138996488
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3985722378
Short name T1178
Test name
Test status
Simulation time 228425383 ps
CPU time 2.92 seconds
Started Jan 21 10:15:30 PM PST 24
Finished Jan 21 10:15:47 PM PST 24
Peak memory 240668 kb
Host smart-4ec3db4f-1016-4bae-84a3-2f5a24fe9905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985722378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3985722378
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.639028969
Short name T1094
Test name
Test status
Simulation time 28490749409 ps
CPU time 70.56 seconds
Started Jan 21 10:15:40 PM PST 24
Finished Jan 21 10:16:59 PM PST 24
Peak memory 246992 kb
Host smart-0db7aa37-8534-406f-bf48-236eba979085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639028969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.
639028969
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.3125751888
Short name T290
Test name
Test status
Simulation time 340549709076 ps
CPU time 2930.6 seconds
Started Jan 21 10:15:40 PM PST 24
Finished Jan 21 11:04:39 PM PST 24
Peak memory 260756 kb
Host smart-87fb367a-f5b2-45ed-a091-b2c7eabc2ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125751888 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.3125751888
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.455008576
Short name T1100
Test name
Test status
Simulation time 10397210948 ps
CPU time 15.37 seconds
Started Jan 21 10:15:41 PM PST 24
Finished Jan 21 10:16:04 PM PST 24
Peak memory 238932 kb
Host smart-2e3c3b45-1460-4b17-bf0e-801e497539b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455008576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.455008576
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.3707409802
Short name T474
Test name
Test status
Simulation time 75295046 ps
CPU time 1.52 seconds
Started Jan 21 10:15:53 PM PST 24
Finished Jan 21 10:16:00 PM PST 24
Peak memory 230252 kb
Host smart-615a29bf-c250-421c-8ba6-d48073e81769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707409802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3707409802
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.301001933
Short name T493
Test name
Test status
Simulation time 1029235406 ps
CPU time 8.07 seconds
Started Jan 21 10:15:47 PM PST 24
Finished Jan 21 10:16:01 PM PST 24
Peak memory 244304 kb
Host smart-d09669a4-9300-41a9-ab01-8d491f1eccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301001933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.301001933
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.80716277
Short name T1044
Test name
Test status
Simulation time 830288713 ps
CPU time 16.03 seconds
Started Jan 21 10:15:48 PM PST 24
Finished Jan 21 10:16:10 PM PST 24
Peak memory 246960 kb
Host smart-2a17a2d8-5b0c-440d-b49d-9ea9bd60cc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80716277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.80716277
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3794012237
Short name T890
Test name
Test status
Simulation time 402438895 ps
CPU time 4.79 seconds
Started Jan 21 10:15:51 PM PST 24
Finished Jan 21 10:16:02 PM PST 24
Peak memory 241148 kb
Host smart-7a09c00e-6080-4dfa-972e-22df6853ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794012237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3794012237
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.4058044967
Short name T827
Test name
Test status
Simulation time 471007124 ps
CPU time 5.45 seconds
Started Jan 21 10:15:45 PM PST 24
Finished Jan 21 10:15:56 PM PST 24
Peak memory 243796 kb
Host smart-d851a451-0af6-40b5-8c2c-28067d59be3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058044967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.4058044967
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.408744703
Short name T726
Test name
Test status
Simulation time 289166825 ps
CPU time 7.48 seconds
Started Jan 21 10:15:44 PM PST 24
Finished Jan 21 10:15:58 PM PST 24
Peak memory 244200 kb
Host smart-082471a6-0f35-4342-b54c-2a5f59895317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408744703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.408744703
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2350836707
Short name T779
Test name
Test status
Simulation time 3049843344 ps
CPU time 6.78 seconds
Started Jan 21 10:15:44 PM PST 24
Finished Jan 21 10:15:57 PM PST 24
Peak memory 243036 kb
Host smart-844a1e23-a5de-4911-8fb1-49b59525e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350836707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2350836707
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.1855479042
Short name T353
Test name
Test status
Simulation time 2848122627 ps
CPU time 8.09 seconds
Started Jan 21 10:15:48 PM PST 24
Finished Jan 21 10:16:03 PM PST 24
Peak memory 238856 kb
Host smart-dcc21b66-45f1-4aa4-aa9e-2d143fa6489d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855479042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.1855479042
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.2078020528
Short name T1258
Test name
Test status
Simulation time 259588004 ps
CPU time 3.16 seconds
Started Jan 21 10:15:45 PM PST 24
Finished Jan 21 10:15:54 PM PST 24
Peak memory 238788 kb
Host smart-6855fe7e-f9d5-47f0-8150-35b10ceb133c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078020528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.2078020528
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.4274776337
Short name T10
Test name
Test status
Simulation time 1805610194 ps
CPU time 5.19 seconds
Started Jan 21 10:15:44 PM PST 24
Finished Jan 21 10:15:55 PM PST 24
Peak memory 238784 kb
Host smart-ed67c804-f32b-4fa9-ba2e-8216c485375c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274776337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.4274776337
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2598211760
Short name T922
Test name
Test status
Simulation time 13654466645 ps
CPU time 145.97 seconds
Started Jan 21 10:15:51 PM PST 24
Finished Jan 21 10:18:23 PM PST 24
Peak memory 255212 kb
Host smart-1769bdab-c848-4738-aa3c-0ffb91fa60ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598211760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2598211760
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.2005335095
Short name T1222
Test name
Test status
Simulation time 215958649208 ps
CPU time 3019.53 seconds
Started Jan 21 10:15:44 PM PST 24
Finished Jan 21 11:06:09 PM PST 24
Peak memory 264764 kb
Host smart-a3f3b660-a268-4998-a402-9a7b127388be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005335095 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.2005335095
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3060852558
Short name T173
Test name
Test status
Simulation time 902369248 ps
CPU time 10.85 seconds
Started Jan 21 10:15:44 PM PST 24
Finished Jan 21 10:16:00 PM PST 24
Peak memory 243540 kb
Host smart-cb90c8d0-74ce-45bf-9021-17bda6feb416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060852558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3060852558
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.2603699904
Short name T1177
Test name
Test status
Simulation time 751065155 ps
CPU time 2.23 seconds
Started Jan 21 10:16:00 PM PST 24
Finished Jan 21 10:16:09 PM PST 24
Peak memory 239660 kb
Host smart-7e5fdaf0-fc39-45a7-ab97-f607c6844754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603699904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2603699904
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.257386794
Short name T889
Test name
Test status
Simulation time 119000573 ps
CPU time 3.02 seconds
Started Jan 21 10:15:48 PM PST 24
Finished Jan 21 10:15:58 PM PST 24
Peak memory 238956 kb
Host smart-c5a1b766-2fae-48d5-9abb-35a0d9e31676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257386794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.257386794
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2204860138
Short name T1054
Test name
Test status
Simulation time 967285180 ps
CPU time 15.53 seconds
Started Jan 21 10:15:50 PM PST 24
Finished Jan 21 10:16:12 PM PST 24
Peak memory 238872 kb
Host smart-a31220c9-3546-4b22-883f-b757745f0a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204860138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2204860138
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.2982291519
Short name T1010
Test name
Test status
Simulation time 2194214127 ps
CPU time 14.65 seconds
Started Jan 21 10:15:50 PM PST 24
Finished Jan 21 10:16:11 PM PST 24
Peak memory 242452 kb
Host smart-2a713c8e-0dbf-4a55-965d-99bb1179142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982291519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.2982291519
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.1035366281
Short name T692
Test name
Test status
Simulation time 219954682 ps
CPU time 4.2 seconds
Started Jan 21 10:15:50 PM PST 24
Finished Jan 21 10:16:01 PM PST 24
Peak memory 240712 kb
Host smart-73e8f10a-49fe-45d1-9b66-123935ba0a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035366281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1035366281
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.1646842404
Short name T634
Test name
Test status
Simulation time 3207328728 ps
CPU time 18.51 seconds
Started Jan 21 10:15:47 PM PST 24
Finished Jan 21 10:16:11 PM PST 24
Peak memory 240212 kb
Host smart-3c870050-463e-44e8-916b-c863509f256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646842404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1646842404
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.3715111658
Short name T903
Test name
Test status
Simulation time 2340775746 ps
CPU time 47.05 seconds
Started Jan 21 10:15:52 PM PST 24
Finished Jan 21 10:16:45 PM PST 24
Peak memory 244060 kb
Host smart-8e8cabe2-dc49-4e4c-b257-0af9eb7939b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715111658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3715111658
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.1007504141
Short name T316
Test name
Test status
Simulation time 375169289 ps
CPU time 5.13 seconds
Started Jan 21 10:55:55 PM PST 24
Finished Jan 21 10:56:02 PM PST 24
Peak memory 238896 kb
Host smart-1fef6da9-2719-4d72-82ce-a18d316f247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007504141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.1007504141
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1422854201
Short name T1138
Test name
Test status
Simulation time 1424524971 ps
CPU time 13.44 seconds
Started Jan 21 10:15:48 PM PST 24
Finished Jan 21 10:16:08 PM PST 24
Peak memory 238976 kb
Host smart-a8358bca-dff1-4f10-90ba-6f3a6d954dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422854201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1422854201
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.1960015496
Short name T218
Test name
Test status
Simulation time 301093516 ps
CPU time 5.07 seconds
Started Jan 21 10:15:49 PM PST 24
Finished Jan 21 10:16:01 PM PST 24
Peak memory 238776 kb
Host smart-f096aae9-7fe7-4565-9fd9-b2c8e9e40ba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960015496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1960015496
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.2660142316
Short name T832
Test name
Test status
Simulation time 2223087367 ps
CPU time 8.76 seconds
Started Jan 21 10:15:52 PM PST 24
Finished Jan 21 10:16:07 PM PST 24
Peak memory 238860 kb
Host smart-ddf6f0ae-591e-4072-8bad-42814c472488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660142316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2660142316
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3024069012
Short name T609
Test name
Test status
Simulation time 702851228 ps
CPU time 9.3 seconds
Started Jan 21 10:15:58 PM PST 24
Finished Jan 21 10:16:15 PM PST 24
Peak memory 238888 kb
Host smart-ceaa0a58-c453-4843-8929-9827665be3aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024069012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3024069012
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.556737329
Short name T786
Test name
Test status
Simulation time 307174174604 ps
CPU time 4067.61 seconds
Started Jan 21 10:15:56 PM PST 24
Finished Jan 21 11:23:50 PM PST 24
Peak memory 273940 kb
Host smart-fb25be92-cac2-4d85-b23f-73457118db55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556737329 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.556737329
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.4281297484
Short name T345
Test name
Test status
Simulation time 9937179695 ps
CPU time 23.94 seconds
Started Jan 21 10:15:58 PM PST 24
Finished Jan 21 10:16:28 PM PST 24
Peak memory 238812 kb
Host smart-1c693c1a-a855-4bf5-be67-43d911133b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281297484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.4281297484
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.1273569661
Short name T1191
Test name
Test status
Simulation time 930252376 ps
CPU time 2.18 seconds
Started Jan 21 10:16:08 PM PST 24
Finished Jan 21 10:16:20 PM PST 24
Peak memory 238636 kb
Host smart-64297b32-eecb-45b1-b8a4-20beb1667e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273569661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1273569661
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.4060809364
Short name T940
Test name
Test status
Simulation time 1269796581 ps
CPU time 15.57 seconds
Started Jan 21 10:15:55 PM PST 24
Finished Jan 21 10:16:17 PM PST 24
Peak memory 238724 kb
Host smart-3bc0a0f1-d30d-4067-8dc3-67511d30f3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060809364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.4060809364
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.2382356111
Short name T223
Test name
Test status
Simulation time 186465040 ps
CPU time 7.87 seconds
Started Jan 21 10:15:59 PM PST 24
Finished Jan 21 10:16:14 PM PST 24
Peak memory 243660 kb
Host smart-b038e5d6-e7cc-4442-b414-7a0c7e1d1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382356111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2382356111
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.3602260237
Short name T350
Test name
Test status
Simulation time 12388931099 ps
CPU time 41.37 seconds
Started Jan 21 10:15:55 PM PST 24
Finished Jan 21 10:16:43 PM PST 24
Peak memory 238800 kb
Host smart-172e1d73-a6f0-4580-838e-5bd77040fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602260237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3602260237
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.4132844926
Short name T148
Test name
Test status
Simulation time 523071014 ps
CPU time 4.41 seconds
Started Jan 21 10:15:56 PM PST 24
Finished Jan 21 10:16:07 PM PST 24
Peak memory 241356 kb
Host smart-71b8e00c-0a3f-4585-bff0-422d818289cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132844926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.4132844926
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.3868279540
Short name T1160
Test name
Test status
Simulation time 1952665432 ps
CPU time 23.73 seconds
Started Jan 21 11:24:50 PM PST 24
Finished Jan 21 11:25:14 PM PST 24
Peak memory 247100 kb
Host smart-3dc9a6d3-baa3-4158-9281-63c7c433aa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868279540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.3868279540
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.1645742580
Short name T879
Test name
Test status
Simulation time 469726121 ps
CPU time 10.01 seconds
Started Jan 21 10:35:47 PM PST 24
Finished Jan 21 10:36:04 PM PST 24
Peak memory 238736 kb
Host smart-838863bf-25d6-4751-83d2-e218f4bafe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645742580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.1645742580
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.1498378577
Short name T625
Test name
Test status
Simulation time 1640770187 ps
CPU time 5.13 seconds
Started Jan 21 10:16:00 PM PST 24
Finished Jan 21 10:16:12 PM PST 24
Peak memory 241660 kb
Host smart-96dcbb91-cdcc-4147-a621-29cc071ae163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498378577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1498378577
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.3508904307
Short name T567
Test name
Test status
Simulation time 265858644 ps
CPU time 4.91 seconds
Started Jan 21 10:16:00 PM PST 24
Finished Jan 21 10:16:12 PM PST 24
Peak memory 238708 kb
Host smart-c0b4b75e-3e4a-4760-83d4-af84a1dc60d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508904307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.3508904307
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.1372698045
Short name T338
Test name
Test status
Simulation time 262985071 ps
CPU time 8.15 seconds
Started Jan 21 10:16:03 PM PST 24
Finished Jan 21 10:16:18 PM PST 24
Peak memory 243632 kb
Host smart-ad50145a-fedf-447b-a2bb-1584eb8b8599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372698045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1372698045
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.2602696409
Short name T1122
Test name
Test status
Simulation time 3323911251 ps
CPU time 5.71 seconds
Started Jan 21 10:16:00 PM PST 24
Finished Jan 21 10:16:13 PM PST 24
Peak memory 238828 kb
Host smart-afe437e7-0c05-4584-8f52-d00fe00b2eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602696409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2602696409
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.1203567824
Short name T753
Test name
Test status
Simulation time 3583494777 ps
CPU time 37.81 seconds
Started Jan 21 10:16:07 PM PST 24
Finished Jan 21 10:16:56 PM PST 24
Peak memory 247120 kb
Host smart-8a464465-9da9-4c92-9107-8f749860c1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203567824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.1203567824
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.952045698
Short name T650
Test name
Test status
Simulation time 673557873362 ps
CPU time 6007.19 seconds
Started Jan 21 11:00:32 PM PST 24
Finished Jan 22 12:40:43 AM PST 24
Peak memory 360940 kb
Host smart-dfc59cbe-6859-4b3f-a1dd-d173b0f44442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952045698 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.952045698
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.934943488
Short name T103
Test name
Test status
Simulation time 714616870 ps
CPU time 13.88 seconds
Started Jan 21 10:15:56 PM PST 24
Finished Jan 21 10:16:16 PM PST 24
Peak memory 238676 kb
Host smart-82706388-7b23-4701-8279-1d879663ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934943488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.934943488
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.1298823563
Short name T1117
Test name
Test status
Simulation time 237261676 ps
CPU time 1.9 seconds
Started Jan 21 10:12:04 PM PST 24
Finished Jan 21 10:12:09 PM PST 24
Peak memory 239716 kb
Host smart-129d75eb-5a83-4441-b589-970964c2fc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298823563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1298823563
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.1329092186
Short name T97
Test name
Test status
Simulation time 2447720152 ps
CPU time 10.27 seconds
Started Jan 21 10:11:58 PM PST 24
Finished Jan 21 10:12:10 PM PST 24
Peak memory 243904 kb
Host smart-cc61cb06-6637-4509-b740-8f5d07ca0cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329092186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.1329092186
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.2874662693
Short name T671
Test name
Test status
Simulation time 1695147221 ps
CPU time 14.83 seconds
Started Jan 21 10:12:05 PM PST 24
Finished Jan 21 10:12:22 PM PST 24
Peak memory 245612 kb
Host smart-94665641-4569-4f9b-b641-49d9b6c4ec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874662693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.2874662693
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.1488647487
Short name T951
Test name
Test status
Simulation time 986008908 ps
CPU time 5.82 seconds
Started Jan 21 10:11:55 PM PST 24
Finished Jan 21 10:12:03 PM PST 24
Peak memory 242652 kb
Host smart-56b30d3a-112b-4fdc-b228-43cf82e9c503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488647487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.1488647487
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1921942798
Short name T1236
Test name
Test status
Simulation time 781313306 ps
CPU time 14.04 seconds
Started Jan 21 10:11:56 PM PST 24
Finished Jan 21 10:12:12 PM PST 24
Peak memory 245348 kb
Host smart-8c4918f3-68d8-4b8f-837c-6d90d519d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921942798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1921942798
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.1559150751
Short name T1153
Test name
Test status
Simulation time 308615337 ps
CPU time 3.91 seconds
Started Jan 21 10:11:59 PM PST 24
Finished Jan 21 10:12:05 PM PST 24
Peak memory 238684 kb
Host smart-737a79de-a801-48da-ab42-7d1b91619a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559150751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1559150751
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.1323291585
Short name T1181
Test name
Test status
Simulation time 228741775 ps
CPU time 5.05 seconds
Started Jan 21 10:12:02 PM PST 24
Finished Jan 21 10:12:09 PM PST 24
Peak memory 238720 kb
Host smart-1af14376-f1ae-4ca1-82cc-ef2a6cad5646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323291585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1323291585
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3662553101
Short name T161
Test name
Test status
Simulation time 1195970314 ps
CPU time 8.88 seconds
Started Jan 21 10:12:03 PM PST 24
Finished Jan 21 10:12:15 PM PST 24
Peak memory 244052 kb
Host smart-dde583a9-8074-4afa-9dd4-069759746412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662553101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3662553101
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.315247951
Short name T700
Test name
Test status
Simulation time 148496922 ps
CPU time 5.47 seconds
Started Jan 21 10:12:00 PM PST 24
Finished Jan 21 10:12:08 PM PST 24
Peak memory 245096 kb
Host smart-1d1b3310-ccc9-43ae-9b24-94368e8a1870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315247951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.315247951
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2188538018
Short name T529
Test name
Test status
Simulation time 2083829037 ps
CPU time 14.98 seconds
Started Jan 21 10:11:59 PM PST 24
Finished Jan 21 10:12:17 PM PST 24
Peak memory 238744 kb
Host smart-72ad8a99-5c6b-40d2-901e-942eadb634c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188538018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2188538018
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.541848683
Short name T963
Test name
Test status
Simulation time 728315918 ps
CPU time 6.11 seconds
Started Jan 21 10:12:02 PM PST 24
Finished Jan 21 10:12:10 PM PST 24
Peak memory 243308 kb
Host smart-5b64cce6-344a-49ab-9b0f-474afac0ee25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541848683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.541848683
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.1517919182
Short name T661
Test name
Test status
Simulation time 220741659 ps
CPU time 3.49 seconds
Started Jan 21 10:12:00 PM PST 24
Finished Jan 21 10:12:06 PM PST 24
Peak memory 238664 kb
Host smart-b748e2b5-6d49-42e0-ba0c-c69f24d9367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517919182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1517919182
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.856992866
Short name T1075
Test name
Test status
Simulation time 1717938051 ps
CPU time 41.61 seconds
Started Jan 21 10:12:02 PM PST 24
Finished Jan 21 10:12:45 PM PST 24
Peak memory 246896 kb
Host smart-b25af965-da63-49cd-964e-eaab5fa2b902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856992866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.856992866
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.2653808907
Short name T520
Test name
Test status
Simulation time 229514712529 ps
CPU time 2582.77 seconds
Started Jan 21 10:12:00 PM PST 24
Finished Jan 21 10:55:06 PM PST 24
Peak memory 264988 kb
Host smart-4458ef97-d742-4c62-afa6-dd1a5f9f4410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653808907 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.2653808907
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.410056267
Short name T1124
Test name
Test status
Simulation time 81277081 ps
CPU time 1.75 seconds
Started Jan 21 10:25:02 PM PST 24
Finished Jan 21 10:25:07 PM PST 24
Peak memory 239640 kb
Host smart-6d9cf136-ef5b-4a9f-90f6-86b1b6d44307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410056267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.410056267
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1453762372
Short name T130
Test name
Test status
Simulation time 555575769 ps
CPU time 6.43 seconds
Started Jan 21 10:16:14 PM PST 24
Finished Jan 21 10:16:27 PM PST 24
Peak memory 246916 kb
Host smart-cbd5b123-30aa-4dc3-adf2-87c63ad981a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453762372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1453762372
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.2096608333
Short name T1026
Test name
Test status
Simulation time 396439903 ps
CPU time 10.41 seconds
Started Jan 21 10:16:05 PM PST 24
Finished Jan 21 10:16:25 PM PST 24
Peak memory 246956 kb
Host smart-ee586827-9117-4586-9834-fc7d9a76a2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096608333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2096608333
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.2350105923
Short name T858
Test name
Test status
Simulation time 718238531 ps
CPU time 14.9 seconds
Started Jan 21 10:16:05 PM PST 24
Finished Jan 21 10:16:29 PM PST 24
Peak memory 238780 kb
Host smart-5fc5214c-308d-49fc-a814-42f949e04b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350105923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2350105923
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.2008503624
Short name T1001
Test name
Test status
Simulation time 542511009 ps
CPU time 4.62 seconds
Started Jan 21 10:16:05 PM PST 24
Finished Jan 21 10:16:19 PM PST 24
Peak memory 241996 kb
Host smart-7c0298bb-a2b5-48c1-b943-8d5e326630c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008503624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2008503624
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.156177450
Short name T1061
Test name
Test status
Simulation time 502970472 ps
CPU time 5.56 seconds
Started Jan 21 10:16:12 PM PST 24
Finished Jan 21 10:16:25 PM PST 24
Peak memory 243968 kb
Host smart-43391eb2-c845-4900-b613-e802b2e4a2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156177450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.156177450
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.1882654520
Short name T657
Test name
Test status
Simulation time 937276027 ps
CPU time 9.46 seconds
Started Jan 21 10:16:16 PM PST 24
Finished Jan 21 10:16:31 PM PST 24
Peak memory 238764 kb
Host smart-7c2ad8d1-0838-4e56-a87f-187cbefcb6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882654520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1882654520
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.1690848982
Short name T1017
Test name
Test status
Simulation time 246711622 ps
CPU time 10.5 seconds
Started Jan 21 10:16:06 PM PST 24
Finished Jan 21 10:16:26 PM PST 24
Peak memory 238672 kb
Host smart-6c8858a3-cf64-42e1-b989-86de418dafad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690848982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.1690848982
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.1116990459
Short name T969
Test name
Test status
Simulation time 490809217 ps
CPU time 6.37 seconds
Started Jan 21 10:16:07 PM PST 24
Finished Jan 21 10:16:24 PM PST 24
Peak memory 234576 kb
Host smart-d55e0543-02dc-4e2b-8392-ce0e6807a8d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116990459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.1116990459
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1666831243
Short name T1049
Test name
Test status
Simulation time 444041209 ps
CPU time 3.41 seconds
Started Jan 21 10:53:39 PM PST 24
Finished Jan 21 10:53:44 PM PST 24
Peak memory 243524 kb
Host smart-1b991d89-cfc7-4b88-9d32-592a09599495
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666831243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1666831243
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.3980593789
Short name T452
Test name
Test status
Simulation time 1952657468 ps
CPU time 4.85 seconds
Started Jan 21 10:16:05 PM PST 24
Finished Jan 21 10:16:20 PM PST 24
Peak memory 241420 kb
Host smart-ac60ccaa-e4a7-470e-9683-a330554fcb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980593789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3980593789
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.255314888
Short name T1295
Test name
Test status
Simulation time 5382903675 ps
CPU time 82.99 seconds
Started Jan 21 10:40:57 PM PST 24
Finished Jan 21 10:42:28 PM PST 24
Peak memory 240660 kb
Host smart-d8f30e4a-6c4e-4443-8174-3aa2faf6ed42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255314888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.
255314888
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.1476770203
Short name T672
Test name
Test status
Simulation time 627544781676 ps
CPU time 5779.01 seconds
Started Jan 21 11:43:46 PM PST 24
Finished Jan 22 01:20:09 AM PST 24
Peak memory 943696 kb
Host smart-bf88faf5-9212-4152-89ac-acc687931cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476770203 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.1476770203
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.4061640883
Short name T2
Test name
Test status
Simulation time 1584164528 ps
CPU time 9.84 seconds
Started Jan 21 10:16:15 PM PST 24
Finished Jan 21 10:16:32 PM PST 24
Peak memory 238720 kb
Host smart-b59f41df-b6a0-4f73-ab26-bdd5b627c0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061640883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.4061640883
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.2962456168
Short name T448
Test name
Test status
Simulation time 106187456 ps
CPU time 2.21 seconds
Started Jan 21 10:16:24 PM PST 24
Finished Jan 21 10:16:29 PM PST 24
Peak memory 239700 kb
Host smart-62d0ddd4-134e-410f-95dd-67828e88b505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962456168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.2962456168
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.50226008
Short name T763
Test name
Test status
Simulation time 231960926 ps
CPU time 6.17 seconds
Started Jan 21 10:16:19 PM PST 24
Finished Jan 21 10:16:29 PM PST 24
Peak memory 243552 kb
Host smart-4dbf910d-245c-470b-a5c3-223c8403e1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50226008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.50226008
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.1978517812
Short name T121
Test name
Test status
Simulation time 247308921 ps
CPU time 4.81 seconds
Started Jan 21 10:16:21 PM PST 24
Finished Jan 21 10:16:29 PM PST 24
Peak memory 238672 kb
Host smart-8c05c7d1-4470-49e5-bd12-48157781aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978517812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1978517812
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.1294991502
Short name T1018
Test name
Test status
Simulation time 1960117389 ps
CPU time 12.06 seconds
Started Jan 21 10:16:14 PM PST 24
Finished Jan 21 10:16:33 PM PST 24
Peak memory 243696 kb
Host smart-8c23d861-c57e-417f-8b65-a55865606eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294991502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.1294991502
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.889326866
Short name T1269
Test name
Test status
Simulation time 1775025218 ps
CPU time 4.9 seconds
Started Jan 21 10:16:14 PM PST 24
Finished Jan 21 10:16:26 PM PST 24
Peak memory 241100 kb
Host smart-9b95dc66-57dc-492f-907d-02d0709c327c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889326866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.889326866
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.4114711384
Short name T604
Test name
Test status
Simulation time 4476345065 ps
CPU time 18.41 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:16:43 PM PST 24
Peak memory 246960 kb
Host smart-33aacb41-5f55-4073-a23e-f99b5bde3dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114711384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.4114711384
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1355425772
Short name T769
Test name
Test status
Simulation time 486563025 ps
CPU time 6.57 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:16:32 PM PST 24
Peak memory 243808 kb
Host smart-641b0ee9-c603-4d1e-98d8-083f5ae478e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355425772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1355425772
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.717518378
Short name T675
Test name
Test status
Simulation time 538748344 ps
CPU time 7.45 seconds
Started Jan 21 10:16:13 PM PST 24
Finished Jan 21 10:16:28 PM PST 24
Peak memory 243388 kb
Host smart-5bfb8b4a-60b2-4b56-bbfb-affc025d381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717518378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.717518378
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1367748846
Short name T907
Test name
Test status
Simulation time 1211686429 ps
CPU time 18.59 seconds
Started Jan 21 10:16:16 PM PST 24
Finished Jan 21 10:16:41 PM PST 24
Peak memory 238776 kb
Host smart-ca7090ed-9082-49a0-92d2-1dede975102e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367748846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1367748846
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3019161998
Short name T861
Test name
Test status
Simulation time 442089803 ps
CPU time 6.84 seconds
Started Jan 21 10:16:22 PM PST 24
Finished Jan 21 10:16:31 PM PST 24
Peak memory 245384 kb
Host smart-56ac148f-de55-4571-96f3-9a3066b589d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019161998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3019161998
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.740241496
Short name T724
Test name
Test status
Simulation time 274844479 ps
CPU time 5.37 seconds
Started Jan 21 10:16:14 PM PST 24
Finished Jan 21 10:16:27 PM PST 24
Peak memory 243576 kb
Host smart-61dd4046-cc9c-461b-bf55-6cbf54919ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740241496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.740241496
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.4114044577
Short name T32
Test name
Test status
Simulation time 213908140878 ps
CPU time 3882.94 seconds
Started Jan 21 10:55:52 PM PST 24
Finished Jan 22 12:00:36 AM PST 24
Peak memory 264148 kb
Host smart-3aa782ad-2902-4d2f-9ec1-e05f10cef95c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114044577 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.4114044577
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1492778073
Short name T933
Test name
Test status
Simulation time 2404558523 ps
CPU time 22.97 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:16:48 PM PST 24
Peak memory 238800 kb
Host smart-f6243a5c-d013-4eae-b523-daa406483872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492778073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1492778073
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2953081520
Short name T670
Test name
Test status
Simulation time 90826180 ps
CPU time 1.6 seconds
Started Jan 21 10:16:22 PM PST 24
Finished Jan 21 10:16:26 PM PST 24
Peak memory 238756 kb
Host smart-c2a3dcd5-514a-4686-9660-6d7b0a6bbd2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953081520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2953081520
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.1046656576
Short name T611
Test name
Test status
Simulation time 219191730 ps
CPU time 6.39 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:16:32 PM PST 24
Peak memory 243268 kb
Host smart-55858004-3665-4478-b592-d1fbd2439f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046656576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1046656576
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.536704248
Short name T369
Test name
Test status
Simulation time 819463482 ps
CPU time 8.54 seconds
Started Jan 21 10:16:22 PM PST 24
Finished Jan 21 10:16:33 PM PST 24
Peak memory 238776 kb
Host smart-91452274-1d22-4c36-abb4-9c1518f6b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536704248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.536704248
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.1424201353
Short name T23
Test name
Test status
Simulation time 131941092 ps
CPU time 3.75 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:16:30 PM PST 24
Peak memory 238780 kb
Host smart-cc836551-6b3e-4401-b74f-302a3429f2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424201353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1424201353
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.2296462034
Short name T850
Test name
Test status
Simulation time 507580488 ps
CPU time 12.34 seconds
Started Jan 21 10:16:21 PM PST 24
Finished Jan 21 10:16:36 PM PST 24
Peak memory 246952 kb
Host smart-33567ff2-549c-4a3b-b5bf-cbf4ff25e11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296462034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.2296462034
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2961935204
Short name T688
Test name
Test status
Simulation time 987825206 ps
CPU time 17.15 seconds
Started Jan 21 10:16:21 PM PST 24
Finished Jan 21 10:16:41 PM PST 24
Peak memory 238748 kb
Host smart-6abb8ebb-c627-4a5d-bb79-fdf70ac28d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961935204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2961935204
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.2635853732
Short name T1014
Test name
Test status
Simulation time 1730969289 ps
CPU time 4.21 seconds
Started Jan 21 10:16:20 PM PST 24
Finished Jan 21 10:16:28 PM PST 24
Peak memory 242240 kb
Host smart-11598e0c-0abf-458b-a515-c186a185cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635853732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2635853732
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.2007119348
Short name T359
Test name
Test status
Simulation time 7467145078 ps
CPU time 22.21 seconds
Started Jan 21 10:16:26 PM PST 24
Finished Jan 21 10:16:50 PM PST 24
Peak memory 238476 kb
Host smart-9a3fcc35-5c4b-4da7-b52b-6d20720efd41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007119348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.2007119348
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.673584436
Short name T221
Test name
Test status
Simulation time 2276977435 ps
CPU time 7.51 seconds
Started Jan 21 10:16:26 PM PST 24
Finished Jan 21 10:16:35 PM PST 24
Peak memory 241416 kb
Host smart-539718bc-3ebb-452e-b07b-d17732d2f489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673584436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.673584436
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.4144213583
Short name T1057
Test name
Test status
Simulation time 941897279 ps
CPU time 6.57 seconds
Started Jan 21 10:16:24 PM PST 24
Finished Jan 21 10:16:33 PM PST 24
Peak memory 238784 kb
Host smart-17d24bf5-bee4-4abb-b6d5-61d0ec5619dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144213583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.4144213583
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.64399615
Short name T1131
Test name
Test status
Simulation time 132718146711 ps
CPU time 153.73 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:18:59 PM PST 24
Peak memory 244316 kb
Host smart-477af849-74d0-419f-8361-e4df7f45ced6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64399615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.64399615
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2667151778
Short name T843
Test name
Test status
Simulation time 119437711298 ps
CPU time 2150.71 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:52:16 PM PST 24
Peak memory 326184 kb
Host smart-e9b44c0d-5fb6-4c18-ab70-38657e2aa6c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667151778 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2667151778
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.415231566
Short name T710
Test name
Test status
Simulation time 4924677440 ps
CPU time 50.28 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:17:16 PM PST 24
Peak memory 244144 kb
Host smart-374b7c7d-e5ed-486a-8909-7032937842ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415231566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.415231566
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.1481430442
Short name T153
Test name
Test status
Simulation time 654459086 ps
CPU time 1.8 seconds
Started Jan 21 10:16:41 PM PST 24
Finished Jan 21 10:16:53 PM PST 24
Peak memory 230500 kb
Host smart-4eca8310-588b-4970-8392-8d677cf20c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481430442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1481430442
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.2172783606
Short name T794
Test name
Test status
Simulation time 8474097397 ps
CPU time 23.01 seconds
Started Jan 21 10:16:30 PM PST 24
Finished Jan 21 10:16:55 PM PST 24
Peak memory 247272 kb
Host smart-672cf1c0-9a35-4099-b54c-5a5a9fe8c895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172783606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.2172783606
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.421604796
Short name T1268
Test name
Test status
Simulation time 122059617 ps
CPU time 5.38 seconds
Started Jan 21 10:16:34 PM PST 24
Finished Jan 21 10:16:42 PM PST 24
Peak memory 238732 kb
Host smart-f15db63e-d058-4f64-89dc-fc8652a7bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421604796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.421604796
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.739311055
Short name T378
Test name
Test status
Simulation time 3925369361 ps
CPU time 12.28 seconds
Started Jan 21 10:16:25 PM PST 24
Finished Jan 21 10:16:39 PM PST 24
Peak memory 238840 kb
Host smart-82352c27-30a8-4a56-ba1d-c5ca4b52657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739311055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.739311055
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.659104851
Short name T143
Test name
Test status
Simulation time 133623505 ps
CPU time 4.23 seconds
Started Jan 21 10:16:30 PM PST 24
Finished Jan 21 10:16:36 PM PST 24
Peak memory 238664 kb
Host smart-78fd42fa-2bea-48f0-af89-b095b658b26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659104851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.659104851
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3770442321
Short name T1193
Test name
Test status
Simulation time 7844640187 ps
CPU time 18.58 seconds
Started Jan 21 10:16:29 PM PST 24
Finished Jan 21 10:16:49 PM PST 24
Peak memory 245880 kb
Host smart-1ba3a24a-1337-4dba-a31b-d02bf7a40559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770442321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3770442321
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.4153295374
Short name T712
Test name
Test status
Simulation time 173907996 ps
CPU time 6.04 seconds
Started Jan 21 10:16:27 PM PST 24
Finished Jan 21 10:16:34 PM PST 24
Peak memory 238724 kb
Host smart-4a12e70f-51fa-4b73-bbdb-68e0b362d9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153295374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.4153295374
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.1652141233
Short name T738
Test name
Test status
Simulation time 194023086 ps
CPU time 4.54 seconds
Started Jan 21 10:16:34 PM PST 24
Finished Jan 21 10:16:41 PM PST 24
Peak memory 243424 kb
Host smart-a0e8c4b9-b4d7-494b-8928-be3c4473c5d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652141233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1652141233
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.2999840638
Short name T713
Test name
Test status
Simulation time 114616571 ps
CPU time 3.11 seconds
Started Jan 21 10:16:27 PM PST 24
Finished Jan 21 10:16:31 PM PST 24
Peak memory 238820 kb
Host smart-a2131dbd-d604-4ada-8bbf-da00a60b86e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999840638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2999840638
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.3257749996
Short name T691
Test name
Test status
Simulation time 174156158 ps
CPU time 5.24 seconds
Started Jan 21 10:16:23 PM PST 24
Finished Jan 21 10:16:30 PM PST 24
Peak memory 243532 kb
Host smart-0a1fe9f6-8689-40d4-acd0-02d1ea69bbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257749996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3257749996
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.1906850846
Short name T1133
Test name
Test status
Simulation time 1874724276726 ps
CPU time 3501.86 seconds
Started Jan 21 10:16:26 PM PST 24
Finished Jan 21 11:14:50 PM PST 24
Peak memory 854972 kb
Host smart-711012ba-a3c0-4ca2-af64-0819d7e5ee0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906850846 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.1906850846
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.1829846830
Short name T701
Test name
Test status
Simulation time 20718486103 ps
CPU time 38.42 seconds
Started Jan 21 10:16:27 PM PST 24
Finished Jan 21 10:17:07 PM PST 24
Peak memory 246972 kb
Host smart-7b22647e-114f-4150-a79d-b0b437091288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829846830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1829846830
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3416563515
Short name T868
Test name
Test status
Simulation time 588383584 ps
CPU time 1.84 seconds
Started Jan 21 10:16:38 PM PST 24
Finished Jan 21 10:16:47 PM PST 24
Peak memory 238484 kb
Host smart-067cf355-b2eb-4791-9c85-7556825499dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416563515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3416563515
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3711837455
Short name T923
Test name
Test status
Simulation time 948033730 ps
CPU time 5.67 seconds
Started Jan 21 10:16:40 PM PST 24
Finished Jan 21 10:16:55 PM PST 24
Peak memory 238804 kb
Host smart-901f627e-9229-460d-8904-36cf28633904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711837455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3711837455
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.2733123756
Short name T606
Test name
Test status
Simulation time 1857917461 ps
CPU time 14.09 seconds
Started Jan 21 10:16:41 PM PST 24
Finished Jan 21 10:17:06 PM PST 24
Peak memory 238832 kb
Host smart-aeb422b2-05f0-4ec5-addf-6bf28a9543e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733123756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2733123756
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.2970649655
Short name T1238
Test name
Test status
Simulation time 252262436 ps
CPU time 3.89 seconds
Started Jan 21 10:16:38 PM PST 24
Finished Jan 21 10:16:50 PM PST 24
Peak memory 238720 kb
Host smart-25ce2cad-8dd2-4ad4-b149-438820c8280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970649655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.2970649655
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3373472886
Short name T1128
Test name
Test status
Simulation time 6935959608 ps
CPU time 14.04 seconds
Started Jan 21 10:16:40 PM PST 24
Finished Jan 21 10:17:06 PM PST 24
Peak memory 238732 kb
Host smart-ef470c64-b52b-49c5-abf7-e116cd5455d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373472886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3373472886
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.1639554444
Short name T1221
Test name
Test status
Simulation time 3215540926 ps
CPU time 17.53 seconds
Started Jan 21 10:16:38 PM PST 24
Finished Jan 21 10:17:04 PM PST 24
Peak memory 244744 kb
Host smart-092cd361-b58f-4b00-a0a9-4f0a8f330cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639554444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1639554444
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3404632343
Short name T341
Test name
Test status
Simulation time 224931176 ps
CPU time 5.99 seconds
Started Jan 21 10:16:38 PM PST 24
Finished Jan 21 10:16:53 PM PST 24
Peak memory 238792 kb
Host smart-32cb7378-6b3b-4b60-83bd-d7ba2a949495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404632343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3404632343
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.2292571146
Short name T1092
Test name
Test status
Simulation time 3749851604 ps
CPU time 12.92 seconds
Started Jan 21 10:16:37 PM PST 24
Finished Jan 21 10:16:53 PM PST 24
Peak memory 238852 kb
Host smart-3c3a99d2-1c96-41a7-9661-b57e58b53570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292571146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.2292571146
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1346919908
Short name T838
Test name
Test status
Simulation time 1882964667 ps
CPU time 9.5 seconds
Started Jan 21 10:16:39 PM PST 24
Finished Jan 21 10:16:57 PM PST 24
Peak memory 238832 kb
Host smart-7df36207-3ea1-40e1-b8db-204ad313206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346919908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1346919908
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3350240170
Short name T1206
Test name
Test status
Simulation time 11347546714 ps
CPU time 129.11 seconds
Started Jan 21 10:16:42 PM PST 24
Finished Jan 21 10:19:01 PM PST 24
Peak memory 247052 kb
Host smart-2a704121-9368-4ac5-a6c1-691e88801b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350240170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3350240170
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.1926714470
Short name T857
Test name
Test status
Simulation time 22841548996 ps
CPU time 603.41 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:26:56 PM PST 24
Peak memory 328752 kb
Host smart-76f18079-a892-43d3-a41b-1a612d7fc080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926714470 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.1926714470
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.1526222307
Short name T1228
Test name
Test status
Simulation time 392488444 ps
CPU time 3.35 seconds
Started Jan 21 10:16:40 PM PST 24
Finished Jan 21 10:16:53 PM PST 24
Peak memory 242572 kb
Host smart-3ebe76d1-9f4d-4ad6-9559-7ce07225ebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526222307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1526222307
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.1625431538
Short name T570
Test name
Test status
Simulation time 672503653 ps
CPU time 1.98 seconds
Started Jan 21 10:16:41 PM PST 24
Finished Jan 21 10:16:54 PM PST 24
Peak memory 239624 kb
Host smart-9ee9c5bd-e4a0-406d-a4d3-aafc123a5e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625431538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.1625431538
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.2612749078
Short name T54
Test name
Test status
Simulation time 1176368873 ps
CPU time 13.42 seconds
Started Jan 21 10:16:40 PM PST 24
Finished Jan 21 10:17:04 PM PST 24
Peak memory 238672 kb
Host smart-1ef59fef-a78f-47fa-b3d1-a982a5b41bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612749078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2612749078
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.2182278576
Short name T1161
Test name
Test status
Simulation time 531414434 ps
CPU time 10.58 seconds
Started Jan 21 10:16:37 PM PST 24
Finished Jan 21 10:16:51 PM PST 24
Peak memory 238812 kb
Host smart-9f7d66d8-68c4-4951-a4b6-66adb309d4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182278576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2182278576
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.4005568639
Short name T516
Test name
Test status
Simulation time 978152510 ps
CPU time 11.28 seconds
Started Jan 21 10:16:40 PM PST 24
Finished Jan 21 10:17:02 PM PST 24
Peak memory 242568 kb
Host smart-1febb3b8-db8d-4f28-97b7-627bf1d7cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005568639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.4005568639
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.808188752
Short name T762
Test name
Test status
Simulation time 372364788 ps
CPU time 4.47 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:16:57 PM PST 24
Peak memory 238708 kb
Host smart-536a0dcb-4e17-4ab7-814a-2c748eb76fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808188752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.808188752
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.2780208013
Short name T1109
Test name
Test status
Simulation time 2377987887 ps
CPU time 26.9 seconds
Started Jan 21 10:16:39 PM PST 24
Finished Jan 21 10:17:16 PM PST 24
Peak memory 238788 kb
Host smart-35fcc1d7-f924-4f60-895d-1916cd7606cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780208013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2780208013
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.870277620
Short name T201
Test name
Test status
Simulation time 1787343090 ps
CPU time 13.5 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:17:06 PM PST 24
Peak memory 246900 kb
Host smart-96d515c3-e1e4-4ad7-8f42-86df7d2e8414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870277620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.870277620
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1058603871
Short name T450
Test name
Test status
Simulation time 825175968 ps
CPU time 7.86 seconds
Started Jan 21 10:16:39 PM PST 24
Finished Jan 21 10:16:56 PM PST 24
Peak memory 243528 kb
Host smart-aef2d610-00f9-493d-996f-43b959944a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058603871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1058603871
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.3619419354
Short name T136
Test name
Test status
Simulation time 670251301 ps
CPU time 5.58 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:16:58 PM PST 24
Peak memory 238720 kb
Host smart-c6007829-4575-4235-96d9-a4ec052a8257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619419354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3619419354
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2348689120
Short name T1039
Test name
Test status
Simulation time 481366865 ps
CPU time 4.35 seconds
Started Jan 21 10:43:17 PM PST 24
Finished Jan 21 10:43:23 PM PST 24
Peak memory 241104 kb
Host smart-bdc5a5a3-bad0-4313-9bae-897d15a5671b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348689120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2348689120
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.3534089424
Short name T708
Test name
Test status
Simulation time 4459675794 ps
CPU time 7.61 seconds
Started Jan 21 10:16:39 PM PST 24
Finished Jan 21 10:16:57 PM PST 24
Peak memory 244048 kb
Host smart-c86bec6a-a01e-41a7-8b31-16a48b5cc731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534089424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3534089424
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.1904912918
Short name T1179
Test name
Test status
Simulation time 15007194507 ps
CPU time 103.53 seconds
Started Jan 21 10:16:43 PM PST 24
Finished Jan 21 10:18:35 PM PST 24
Peak memory 247140 kb
Host smart-f9448f91-be90-42a3-aa08-050c053c23da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904912918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.1904912918
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.3505885518
Short name T509
Test name
Test status
Simulation time 6691835339 ps
CPU time 14.17 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:17:07 PM PST 24
Peak memory 244692 kb
Host smart-fe13bd57-c1c1-4494-90a6-737610ca07d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505885518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3505885518
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.3377258304
Short name T631
Test name
Test status
Simulation time 43805680 ps
CPU time 1.58 seconds
Started Jan 21 10:16:47 PM PST 24
Finished Jan 21 10:16:57 PM PST 24
Peak memory 230544 kb
Host smart-d8837553-4ed9-4c43-a1e3-b8fcdcaa5144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377258304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3377258304
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.478653147
Short name T1213
Test name
Test status
Simulation time 249403996 ps
CPU time 5.2 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:16:58 PM PST 24
Peak memory 238768 kb
Host smart-63c16322-99c8-4e1a-8d64-7c25ca4438bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478653147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.478653147
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.3568332458
Short name T229
Test name
Test status
Simulation time 929242317 ps
CPU time 5.66 seconds
Started Jan 21 10:16:45 PM PST 24
Finished Jan 21 10:16:58 PM PST 24
Peak memory 243768 kb
Host smart-14817de1-49ce-4c69-89e1-d4895eba5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568332458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3568332458
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.1077687448
Short name T1004
Test name
Test status
Simulation time 2054576529 ps
CPU time 4.95 seconds
Started Jan 21 10:16:42 PM PST 24
Finished Jan 21 10:16:57 PM PST 24
Peak memory 241768 kb
Host smart-b8b549d4-960c-4f7f-9bb9-04dcd79e48b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077687448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.1077687448
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.1683795992
Short name T138
Test name
Test status
Simulation time 323711879 ps
CPU time 7.96 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:17:01 PM PST 24
Peak memory 238724 kb
Host smart-7f3b0f86-5216-4e18-895b-557072e39432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683795992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.1683795992
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.4277612571
Short name T1251
Test name
Test status
Simulation time 1967410684 ps
CPU time 12.83 seconds
Started Jan 21 10:16:45 PM PST 24
Finished Jan 21 10:17:05 PM PST 24
Peak memory 243928 kb
Host smart-09823142-24f6-49c3-9017-eda20e63c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277612571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.4277612571
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.3941013784
Short name T666
Test name
Test status
Simulation time 632939930 ps
CPU time 4.8 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:16:57 PM PST 24
Peak memory 238716 kb
Host smart-509f1229-5c4f-4d9a-ab0f-72733ecfe397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941013784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3941013784
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.3015593543
Short name T790
Test name
Test status
Simulation time 1020755578 ps
CPU time 18.59 seconds
Started Jan 21 10:16:47 PM PST 24
Finished Jan 21 10:17:15 PM PST 24
Peak memory 238972 kb
Host smart-64843afb-a757-4cbd-80bc-c656fa81fc1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015593543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.3015593543
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.89889019
Short name T1008
Test name
Test status
Simulation time 3258940220 ps
CPU time 7.19 seconds
Started Jan 21 10:16:45 PM PST 24
Finished Jan 21 10:17:00 PM PST 24
Peak memory 238784 kb
Host smart-ac2eef40-a4f3-4ffb-b29e-b8389c144f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89889019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.89889019
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3218669231
Short name T11
Test name
Test status
Simulation time 159468304 ps
CPU time 5.12 seconds
Started Jan 21 10:16:44 PM PST 24
Finished Jan 21 10:16:58 PM PST 24
Peak memory 238664 kb
Host smart-54c21f4b-29e8-48bd-bf8a-9e18cf46ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218669231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3218669231
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.2842158436
Short name T591
Test name
Test status
Simulation time 627817367 ps
CPU time 15.13 seconds
Started Jan 21 10:16:45 PM PST 24
Finished Jan 21 10:17:08 PM PST 24
Peak memory 238844 kb
Host smart-fde8af60-685f-469b-93bf-a8aff5972b2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842158436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.2842158436
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3589702065
Short name T1009
Test name
Test status
Simulation time 620168878428 ps
CPU time 4821.16 seconds
Started Jan 21 10:16:47 PM PST 24
Finished Jan 21 11:37:18 PM PST 24
Peak memory 279892 kb
Host smart-1432e9d5-976f-4109-b484-2d717ed03b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589702065 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.3589702065
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.1282867687
Short name T677
Test name
Test status
Simulation time 274985104 ps
CPU time 9.1 seconds
Started Jan 21 10:16:45 PM PST 24
Finished Jan 21 10:17:02 PM PST 24
Peak memory 238760 kb
Host smart-1ce28202-81cd-4380-a094-6e0a3df9f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282867687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1282867687
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2352333667
Short name T209
Test name
Test status
Simulation time 134969478 ps
CPU time 2.23 seconds
Started Jan 21 10:16:54 PM PST 24
Finished Jan 21 10:17:03 PM PST 24
Peak memory 230244 kb
Host smart-f01fc367-f98d-4f3b-8e98-c40d4b78e997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352333667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2352333667
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.4135736130
Short name T829
Test name
Test status
Simulation time 9848582316 ps
CPU time 23.53 seconds
Started Jan 21 10:16:55 PM PST 24
Finished Jan 21 10:17:26 PM PST 24
Peak memory 247272 kb
Host smart-5f6294ec-06e7-43b1-b88f-c1ba3ac65a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135736130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.4135736130
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.434607521
Short name T477
Test name
Test status
Simulation time 408264173 ps
CPU time 5.66 seconds
Started Jan 21 10:16:52 PM PST 24
Finished Jan 21 10:17:05 PM PST 24
Peak memory 242616 kb
Host smart-dc646e9b-9751-4efc-9379-f0edfd00cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434607521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.434607521
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.2445976984
Short name T364
Test name
Test status
Simulation time 859655669 ps
CPU time 6.76 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 10:17:10 PM PST 24
Peak memory 238744 kb
Host smart-e69cb584-4bf8-4ae6-9fad-458d28ce1d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445976984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.2445976984
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.2080778585
Short name T160
Test name
Test status
Simulation time 211175153 ps
CPU time 4.56 seconds
Started Jan 21 10:16:45 PM PST 24
Finished Jan 21 10:16:57 PM PST 24
Peak memory 240744 kb
Host smart-52fc2087-905c-4da2-a49c-18e053877c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080778585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.2080778585
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.113821557
Short name T310
Test name
Test status
Simulation time 545596258 ps
CPU time 8.46 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 10:17:12 PM PST 24
Peak memory 238788 kb
Host smart-1814fc1d-6309-477c-87e9-dea3ef1116e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113821557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.113821557
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.1983948430
Short name T99
Test name
Test status
Simulation time 6823091460 ps
CPU time 69.38 seconds
Started Jan 21 10:17:01 PM PST 24
Finished Jan 21 10:18:18 PM PST 24
Peak memory 246148 kb
Host smart-f7ac7454-ce5f-4df7-b685-3b06ea335007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983948430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1983948430
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.188000438
Short name T1043
Test name
Test status
Simulation time 172833280 ps
CPU time 6.53 seconds
Started Jan 21 10:42:49 PM PST 24
Finished Jan 21 10:43:01 PM PST 24
Peak memory 238704 kb
Host smart-60e62b59-4534-42d0-afc8-3457d3507698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188000438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.188000438
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.782471149
Short name T1155
Test name
Test status
Simulation time 1788255664 ps
CPU time 12.39 seconds
Started Jan 21 10:16:48 PM PST 24
Finished Jan 21 10:17:10 PM PST 24
Peak memory 243508 kb
Host smart-34587b58-68c5-4e03-83da-3e0829294bf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782471149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.782471149
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.3211750342
Short name T336
Test name
Test status
Simulation time 950779583 ps
CPU time 9.27 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 10:17:13 PM PST 24
Peak memory 238800 kb
Host smart-6366a6f2-b371-4a7a-8002-1dc81e713009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211750342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3211750342
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3103522685
Short name T224
Test name
Test status
Simulation time 167967670 ps
CPU time 4.02 seconds
Started Jan 21 10:16:47 PM PST 24
Finished Jan 21 10:17:00 PM PST 24
Peak memory 241056 kb
Host smart-37c17de4-e2de-463c-a99d-ae4aa9da8f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103522685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3103522685
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.3116930167
Short name T356
Test name
Test status
Simulation time 8795800063 ps
CPU time 168.6 seconds
Started Jan 21 10:16:54 PM PST 24
Finished Jan 21 10:19:49 PM PST 24
Peak memory 247064 kb
Host smart-ad51be7d-fa80-49b8-9384-ebbb25f7a953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116930167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.3116930167
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.613359623
Short name T12
Test name
Test status
Simulation time 1609109015848 ps
CPU time 6058.78 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 11:58:02 PM PST 24
Peak memory 386692 kb
Host smart-db7ddbec-7d3b-4ad4-8650-442e3b22d49b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613359623 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.613359623
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.335386847
Short name T830
Test name
Test status
Simulation time 1929039956 ps
CPU time 20.98 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 10:17:25 PM PST 24
Peak memory 238780 kb
Host smart-5d35ee3c-6979-44a1-ad54-d8e6bc36f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335386847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.335386847
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.3704207620
Short name T1189
Test name
Test status
Simulation time 94707221 ps
CPU time 1.92 seconds
Started Jan 21 10:17:00 PM PST 24
Finished Jan 21 10:17:10 PM PST 24
Peak memory 239564 kb
Host smart-e7a68bbb-e750-42e5-a384-3db49c5af599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704207620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.3704207620
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.3386126629
Short name T1165
Test name
Test status
Simulation time 621758201 ps
CPU time 9.72 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 10:17:13 PM PST 24
Peak memory 245580 kb
Host smart-8c760569-787e-407d-889c-e85331f4f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386126629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.3386126629
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.103354820
Short name T159
Test name
Test status
Simulation time 1758985450 ps
CPU time 5.38 seconds
Started Jan 21 10:16:55 PM PST 24
Finished Jan 21 10:17:07 PM PST 24
Peak memory 243780 kb
Host smart-ffb0f18c-4433-46ff-999e-e17ba79dd9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103354820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.103354820
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.1391651299
Short name T1081
Test name
Test status
Simulation time 342751406 ps
CPU time 4.46 seconds
Started Jan 21 10:16:58 PM PST 24
Finished Jan 21 10:17:10 PM PST 24
Peak memory 241780 kb
Host smart-838fb458-5a61-4a70-9d32-6123355a360a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391651299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1391651299
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2717464884
Short name T301
Test name
Test status
Simulation time 12357487705 ps
CPU time 24.76 seconds
Started Jan 21 10:16:59 PM PST 24
Finished Jan 21 10:17:31 PM PST 24
Peak memory 247016 kb
Host smart-0eef924c-2f15-48a7-adbb-e053e656b8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717464884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2717464884
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.1426624077
Short name T346
Test name
Test status
Simulation time 852464742 ps
CPU time 13.1 seconds
Started Jan 21 10:17:02 PM PST 24
Finished Jan 21 10:17:22 PM PST 24
Peak memory 238760 kb
Host smart-95ddb309-2f4a-4315-a9bc-b40462b6b872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426624077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1426624077
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.3353989434
Short name T971
Test name
Test status
Simulation time 295294350 ps
CPU time 4 seconds
Started Jan 21 10:16:57 PM PST 24
Finished Jan 21 10:17:08 PM PST 24
Peak memory 238664 kb
Host smart-44f19535-d215-4f25-be44-ab6970e739b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353989434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3353989434
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1200409721
Short name T636
Test name
Test status
Simulation time 1194661237 ps
CPU time 18.47 seconds
Started Jan 21 10:17:01 PM PST 24
Finished Jan 21 10:17:27 PM PST 24
Peak memory 243152 kb
Host smart-37e40c54-5afe-4aed-a55a-ea596f232556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1200409721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1200409721
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.1777035403
Short name T335
Test name
Test status
Simulation time 902739261 ps
CPU time 7.27 seconds
Started Jan 21 10:17:00 PM PST 24
Finished Jan 21 10:17:16 PM PST 24
Peak memory 238856 kb
Host smart-6eebadca-5d24-4b65-b353-a28b018c0c2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1777035403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1777035403
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1700015341
Short name T816
Test name
Test status
Simulation time 549972140 ps
CPU time 6.92 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 10:17:09 PM PST 24
Peak memory 238756 kb
Host smart-e5f84da9-e020-4474-8f28-646d38c60dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700015341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1700015341
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3631523071
Short name T1012
Test name
Test status
Simulation time 6902512819305 ps
CPU time 9227.13 seconds
Started Jan 21 10:17:04 PM PST 24
Finished Jan 22 12:50:58 AM PST 24
Peak memory 647608 kb
Host smart-a23fb40b-5884-47d5-abbd-78f2c8c1e4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631523071 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3631523071
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.2252336750
Short name T831
Test name
Test status
Simulation time 2849173869 ps
CPU time 29.3 seconds
Started Jan 21 10:17:05 PM PST 24
Finished Jan 21 10:17:40 PM PST 24
Peak memory 238840 kb
Host smart-996da239-0220-4525-9e5a-9eabfb0c34ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252336750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2252336750
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.3365129200
Short name T614
Test name
Test status
Simulation time 115141147 ps
CPU time 1.56 seconds
Started Jan 21 10:17:05 PM PST 24
Finished Jan 21 10:17:13 PM PST 24
Peak memory 230476 kb
Host smart-a678360d-5fa9-4793-98fd-f2e78a8be440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365129200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.3365129200
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.3006193796
Short name T382
Test name
Test status
Simulation time 513577002 ps
CPU time 4.34 seconds
Started Jan 21 10:17:01 PM PST 24
Finished Jan 21 10:17:13 PM PST 24
Peak memory 238696 kb
Host smart-541d838c-eddb-4c62-8be6-c57e614a1482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006193796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3006193796
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.1983671501
Short name T610
Test name
Test status
Simulation time 509477583 ps
CPU time 8.51 seconds
Started Jan 21 10:17:00 PM PST 24
Finished Jan 21 10:17:17 PM PST 24
Peak memory 243216 kb
Host smart-ad67d43e-4755-4c16-b059-460710c01aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983671501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.1983671501
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.2912387208
Short name T1287
Test name
Test status
Simulation time 505869643 ps
CPU time 6.34 seconds
Started Jan 21 10:17:06 PM PST 24
Finished Jan 21 10:17:19 PM PST 24
Peak memory 244140 kb
Host smart-74dcf9ca-051c-46e3-a270-f7eed42e0c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912387208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2912387208
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.791918235
Short name T578
Test name
Test status
Simulation time 351315173 ps
CPU time 4.66 seconds
Started Jan 21 10:16:58 PM PST 24
Finished Jan 21 10:17:10 PM PST 24
Peak memory 238760 kb
Host smart-0a8b5762-daed-42c1-a48d-bf975780a6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791918235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.791918235
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2410053039
Short name T1273
Test name
Test status
Simulation time 2070833427 ps
CPU time 11.24 seconds
Started Jan 21 10:17:03 PM PST 24
Finished Jan 21 10:17:21 PM PST 24
Peak memory 245196 kb
Host smart-a98d2998-89b7-4025-8d00-79ab5a4e4c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410053039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2410053039
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2398505804
Short name T1267
Test name
Test status
Simulation time 6687717639 ps
CPU time 18.58 seconds
Started Jan 21 10:17:09 PM PST 24
Finished Jan 21 10:17:35 PM PST 24
Peak memory 238828 kb
Host smart-a99a8ba0-dcd6-41c6-815f-fd41b8f60dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398505804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2398505804
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.327482910
Short name T318
Test name
Test status
Simulation time 165261572 ps
CPU time 5.3 seconds
Started Jan 21 10:16:58 PM PST 24
Finished Jan 21 10:17:11 PM PST 24
Peak memory 238960 kb
Host smart-f01a1ae5-97bb-41c4-992e-ed2d1da8c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327482910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.327482910
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.2965330873
Short name T656
Test name
Test status
Simulation time 2903113828 ps
CPU time 5.79 seconds
Started Jan 21 10:16:56 PM PST 24
Finished Jan 21 10:17:09 PM PST 24
Peak memory 238816 kb
Host smart-300e393d-7438-4215-bfdd-dfc8e5ebdad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965330873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2965330873
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.4281555440
Short name T935
Test name
Test status
Simulation time 993826060 ps
CPU time 7.57 seconds
Started Jan 21 10:17:07 PM PST 24
Finished Jan 21 10:17:21 PM PST 24
Peak memory 238792 kb
Host smart-d4b42c47-8443-4002-9b20-99537e61a2cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4281555440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.4281555440
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.1390505715
Short name T238
Test name
Test status
Simulation time 394477998 ps
CPU time 6.76 seconds
Started Jan 21 10:17:02 PM PST 24
Finished Jan 21 10:17:16 PM PST 24
Peak memory 238764 kb
Host smart-5d6ff70b-cf57-424a-bbd4-4c418e1b0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390505715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1390505715
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.1388690764
Short name T1036
Test name
Test status
Simulation time 256549598 ps
CPU time 4.47 seconds
Started Jan 21 10:17:09 PM PST 24
Finished Jan 21 10:17:20 PM PST 24
Peak memory 238844 kb
Host smart-e18c3d6b-b926-4322-a06c-c5329c9a1c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388690764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.1388690764
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2172937842
Short name T1281
Test name
Test status
Simulation time 3817801780652 ps
CPU time 9655.46 seconds
Started Jan 21 10:17:05 PM PST 24
Finished Jan 22 12:58:08 AM PST 24
Peak memory 993828 kb
Host smart-b6ee39b5-c68c-4db2-b1dd-6fc42c4756ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172937842 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.2172937842
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.572903167
Short name T805
Test name
Test status
Simulation time 1153240675 ps
CPU time 13.37 seconds
Started Jan 21 10:17:11 PM PST 24
Finished Jan 21 10:17:31 PM PST 24
Peak memory 238848 kb
Host smart-7d13eb3c-ee9f-4657-857a-e06a9d3ee886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572903167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.572903167
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.365522934
Short name T1051
Test name
Test status
Simulation time 167435582 ps
CPU time 1.79 seconds
Started Jan 21 10:12:05 PM PST 24
Finished Jan 21 10:12:10 PM PST 24
Peak memory 239720 kb
Host smart-1426ca0a-e036-48e9-bfb7-288bea38d6db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365522934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.365522934
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.2533449331
Short name T555
Test name
Test status
Simulation time 345790208 ps
CPU time 4.87 seconds
Started Jan 21 10:12:06 PM PST 24
Finished Jan 21 10:12:13 PM PST 24
Peak memory 242104 kb
Host smart-fb02357d-2bd1-4436-a2d4-e69e48955122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533449331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2533449331
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2796054645
Short name T45
Test name
Test status
Simulation time 862859297 ps
CPU time 12.6 seconds
Started Jan 21 10:12:05 PM PST 24
Finished Jan 21 10:12:20 PM PST 24
Peak memory 246952 kb
Host smart-688d3b86-a1b2-4415-9f5c-1f903f39e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796054645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2796054645
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.486270331
Short name T499
Test name
Test status
Simulation time 1224142601 ps
CPU time 10.03 seconds
Started Jan 21 10:12:02 PM PST 24
Finished Jan 21 10:12:14 PM PST 24
Peak memory 245228 kb
Host smart-8910071d-0351-4ed3-b7aa-206bcd82866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486270331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.486270331
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.202390369
Short name T1183
Test name
Test status
Simulation time 11561605268 ps
CPU time 33.65 seconds
Started Jan 21 10:12:03 PM PST 24
Finished Jan 21 10:12:40 PM PST 24
Peak memory 244548 kb
Host smart-085ab4fb-e4dd-470d-be1e-77057c289b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202390369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.202390369
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.1386782007
Short name T74
Test name
Test status
Simulation time 139036596 ps
CPU time 4.99 seconds
Started Jan 21 10:12:02 PM PST 24
Finished Jan 21 10:12:09 PM PST 24
Peak memory 238736 kb
Host smart-3ec4e008-8e16-43c9-8700-d11ccf266616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386782007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1386782007
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.826723078
Short name T1216
Test name
Test status
Simulation time 581255004 ps
CPU time 6.63 seconds
Started Jan 21 10:12:07 PM PST 24
Finished Jan 21 10:12:15 PM PST 24
Peak memory 243516 kb
Host smart-c02109f9-6fe8-4e40-ac15-4b35e7efb398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826723078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.826723078
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.3571450760
Short name T894
Test name
Test status
Simulation time 312512691 ps
CPU time 11.24 seconds
Started Jan 21 10:12:06 PM PST 24
Finished Jan 21 10:12:20 PM PST 24
Peak memory 238980 kb
Host smart-943777f6-4d44-40f6-a357-87131e66eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571450760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.3571450760
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.4140224077
Short name T207
Test name
Test status
Simulation time 155459211 ps
CPU time 3.16 seconds
Started Jan 21 10:12:03 PM PST 24
Finished Jan 21 10:12:09 PM PST 24
Peak memory 238732 kb
Host smart-dfe9dfa3-f65a-4e42-9a3c-25c0275b59c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140224077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4140224077
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.599566172
Short name T93
Test name
Test status
Simulation time 453504908 ps
CPU time 14.28 seconds
Started Jan 21 10:12:03 PM PST 24
Finished Jan 21 10:12:20 PM PST 24
Peak memory 238672 kb
Host smart-69d43e25-4e1f-4402-a306-658e18fd4ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599566172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.599566172
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.3595424650
Short name T697
Test name
Test status
Simulation time 891245113 ps
CPU time 8.32 seconds
Started Jan 21 10:12:03 PM PST 24
Finished Jan 21 10:12:15 PM PST 24
Peak memory 243412 kb
Host smart-129f50b0-12cc-4b7a-8eea-ec6948e92139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595424650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3595424650
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.2019357689
Short name T797
Test name
Test status
Simulation time 454343600 ps
CPU time 6.99 seconds
Started Jan 21 10:12:03 PM PST 24
Finished Jan 21 10:12:12 PM PST 24
Peak memory 238676 kb
Host smart-2865a0ee-ea56-4d9a-a654-61817f579218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019357689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2019357689
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.3429835048
Short name T1130
Test name
Test status
Simulation time 493164452396 ps
CPU time 4399.31 seconds
Started Jan 21 10:12:06 PM PST 24
Finished Jan 21 11:25:28 PM PST 24
Peak memory 280888 kb
Host smart-fa3c60ee-6619-43f4-8d0d-c5d82863c2a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429835048 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.3429835048
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.2638731347
Short name T608
Test name
Test status
Simulation time 1186698323 ps
CPU time 11.14 seconds
Started Jan 21 10:12:06 PM PST 24
Finished Jan 21 10:12:19 PM PST 24
Peak memory 247148 kb
Host smart-508cc608-ccd5-4699-b9ef-b76c6c6cbaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638731347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2638731347
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.2270912626
Short name T787
Test name
Test status
Simulation time 1955486560 ps
CPU time 4.73 seconds
Started Jan 21 10:17:10 PM PST 24
Finished Jan 21 10:17:22 PM PST 24
Peak memory 241056 kb
Host smart-b50f6de4-6184-4ec6-8818-4d1c5261acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270912626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.2270912626
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.2555370100
Short name T749
Test name
Test status
Simulation time 471149002 ps
CPU time 6.7 seconds
Started Jan 21 10:17:11 PM PST 24
Finished Jan 21 10:17:25 PM PST 24
Peak memory 238700 kb
Host smart-f713a5f9-f87f-4b37-96fb-93d37c45bf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555370100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2555370100
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.963931653
Short name T580
Test name
Test status
Simulation time 92289049 ps
CPU time 3.49 seconds
Started Jan 21 10:17:09 PM PST 24
Finished Jan 21 10:17:19 PM PST 24
Peak memory 238816 kb
Host smart-fc1b148b-c963-44a6-93e7-68e1a422b9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963931653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.963931653
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.3408119805
Short name T729
Test name
Test status
Simulation time 223559470 ps
CPU time 3.03 seconds
Started Jan 21 10:17:12 PM PST 24
Finished Jan 21 10:17:22 PM PST 24
Peak memory 241136 kb
Host smart-793ecc1d-65d9-459c-8dd5-f9cd18f23efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408119805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3408119805
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3328594790
Short name T835
Test name
Test status
Simulation time 1360345968989 ps
CPU time 6001.07 seconds
Started Jan 21 10:17:14 PM PST 24
Finished Jan 21 11:57:24 PM PST 24
Peak memory 489380 kb
Host smart-834f8a4d-b401-4c7a-bda1-1efff3844bd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328594790 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3328594790
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3441698098
Short name T569
Test name
Test status
Simulation time 269445247 ps
CPU time 4.12 seconds
Started Jan 21 10:17:14 PM PST 24
Finished Jan 21 10:17:25 PM PST 24
Peak memory 241544 kb
Host smart-adf35164-d09d-40d8-b6a0-180c381c4291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441698098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3441698098
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2120670806
Short name T343
Test name
Test status
Simulation time 521680796 ps
CPU time 3.38 seconds
Started Jan 21 10:17:10 PM PST 24
Finished Jan 21 10:17:20 PM PST 24
Peak memory 238656 kb
Host smart-d8ef7b4e-0a07-42a9-8743-b33f3712f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120670806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2120670806
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.482678109
Short name T1116
Test name
Test status
Simulation time 335646843216 ps
CPU time 2641.98 seconds
Started Jan 21 10:17:16 PM PST 24
Finished Jan 21 11:01:27 PM PST 24
Peak memory 273332 kb
Host smart-1e6a018b-c0de-4792-8309-45ba318211e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482678109 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.482678109
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.2540575475
Short name T84
Test name
Test status
Simulation time 494111515 ps
CPU time 4.01 seconds
Started Jan 21 10:17:12 PM PST 24
Finished Jan 21 10:17:23 PM PST 24
Peak memory 238728 kb
Host smart-54539a3b-fc7a-47a4-96e7-020c9b2f5040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540575475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.2540575475
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.1125446392
Short name T1063
Test name
Test status
Simulation time 418529928 ps
CPU time 5.09 seconds
Started Jan 21 10:17:15 PM PST 24
Finished Jan 21 10:17:29 PM PST 24
Peak memory 243008 kb
Host smart-eb154013-ba12-4409-b599-808c4053a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125446392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1125446392
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1191188889
Short name T322
Test name
Test status
Simulation time 1398196311037 ps
CPU time 7262.01 seconds
Started Jan 21 10:17:16 PM PST 24
Finished Jan 22 12:18:28 AM PST 24
Peak memory 291548 kb
Host smart-4b6a776a-47cc-4266-8b9d-13cdf28c111f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191188889 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.1191188889
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3972487388
Short name T1070
Test name
Test status
Simulation time 126814591 ps
CPU time 3.88 seconds
Started Jan 21 10:17:16 PM PST 24
Finished Jan 21 10:17:29 PM PST 24
Peak memory 246864 kb
Host smart-bdc38741-7281-475f-986f-ab22400a4097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972487388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3972487388
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3080260339
Short name T320
Test name
Test status
Simulation time 105162884 ps
CPU time 4.07 seconds
Started Jan 21 10:17:14 PM PST 24
Finished Jan 21 10:17:26 PM PST 24
Peak memory 241976 kb
Host smart-7614e1f0-6a57-4cd2-814e-a5f2b5dad177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080260339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3080260339
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.149490446
Short name T1207
Test name
Test status
Simulation time 6882590505834 ps
CPU time 9688.15 seconds
Started Jan 21 10:17:12 PM PST 24
Finished Jan 22 12:58:48 AM PST 24
Peak memory 301076 kb
Host smart-fb8e553a-6698-48ed-8c7f-c04523a2c862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149490446 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.149490446
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.20931207
Short name T68
Test name
Test status
Simulation time 562236103 ps
CPU time 3.78 seconds
Started Jan 21 10:17:12 PM PST 24
Finished Jan 21 10:17:23 PM PST 24
Peak memory 238624 kb
Host smart-2cbf7866-cc48-4c6b-b205-7a23d9861d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20931207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.20931207
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.2154225675
Short name T744
Test name
Test status
Simulation time 317817351 ps
CPU time 6.87 seconds
Started Jan 21 10:17:21 PM PST 24
Finished Jan 21 10:17:35 PM PST 24
Peak memory 243180 kb
Host smart-b8857ff1-bffc-4b84-987c-093a906d44de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154225675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2154225675
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.2546890065
Short name T195
Test name
Test status
Simulation time 4163136058340 ps
CPU time 10698.9 seconds
Started Jan 21 10:17:19 PM PST 24
Finished Jan 22 01:15:47 AM PST 24
Peak memory 1045888 kb
Host smart-a699f7f6-83b2-4b8a-bb1b-3688045971ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546890065 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.2546890065
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.706676229
Short name T1227
Test name
Test status
Simulation time 489164050 ps
CPU time 4.17 seconds
Started Jan 21 10:17:22 PM PST 24
Finished Jan 21 10:17:33 PM PST 24
Peak memory 238724 kb
Host smart-9d2c8810-a4f4-4368-87f6-e75e198ad891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706676229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.706676229
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.1547635566
Short name T759
Test name
Test status
Simulation time 381743797 ps
CPU time 5.82 seconds
Started Jan 21 10:17:24 PM PST 24
Finished Jan 21 10:17:36 PM PST 24
Peak memory 243056 kb
Host smart-cec198dc-3a85-4a4f-8b0b-020089d91068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547635566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1547635566
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2836078500
Short name T635
Test name
Test status
Simulation time 500867401400 ps
CPU time 1173.39 seconds
Started Jan 21 10:17:23 PM PST 24
Finished Jan 21 10:37:02 PM PST 24
Peak memory 247180 kb
Host smart-ac828cb6-2017-4ed3-90e7-32e20aaadfa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836078500 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2836078500
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.20873428
Short name T28
Test name
Test status
Simulation time 2405962487 ps
CPU time 5.94 seconds
Started Jan 21 10:17:24 PM PST 24
Finished Jan 21 10:17:36 PM PST 24
Peak memory 243664 kb
Host smart-a8a908ca-a08b-4faf-8d38-630bd7aa1491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20873428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.20873428
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.858408298
Short name T1215
Test name
Test status
Simulation time 172278073 ps
CPU time 3.59 seconds
Started Jan 21 10:17:21 PM PST 24
Finished Jan 21 10:17:32 PM PST 24
Peak memory 242612 kb
Host smart-65937df0-4f60-42bf-bea2-d0eeb4d719cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858408298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.858408298
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3543286889
Short name T684
Test name
Test status
Simulation time 3684176473362 ps
CPU time 5366.92 seconds
Started Jan 21 10:17:22 PM PST 24
Finished Jan 21 11:46:56 PM PST 24
Peak memory 936328 kb
Host smart-0c87bda1-1e2e-4d04-8c16-fc75a7f0a9d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543286889 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.3543286889
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.981176085
Short name T146
Test name
Test status
Simulation time 133852422 ps
CPU time 4.31 seconds
Started Jan 21 10:17:17 PM PST 24
Finished Jan 21 10:17:31 PM PST 24
Peak memory 241336 kb
Host smart-4c14389a-e875-41d0-98ef-e688e69d92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981176085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.981176085
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.896326128
Short name T766
Test name
Test status
Simulation time 220320349 ps
CPU time 5.34 seconds
Started Jan 21 10:17:20 PM PST 24
Finished Jan 21 10:17:33 PM PST 24
Peak memory 238788 kb
Host smart-f60ec8c7-6e52-458a-b4b2-2a8a24723593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896326128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.896326128
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.534953108
Short name T1127
Test name
Test status
Simulation time 2082472919309 ps
CPU time 3208.17 seconds
Started Jan 21 10:17:24 PM PST 24
Finished Jan 21 11:10:58 PM PST 24
Peak memory 289116 kb
Host smart-47131187-7fe3-45be-9fbe-622cec21f263
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534953108 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.534953108
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.1255973586
Short name T1115
Test name
Test status
Simulation time 149725747 ps
CPU time 3.86 seconds
Started Jan 21 10:17:22 PM PST 24
Finished Jan 21 10:17:33 PM PST 24
Peak memory 241368 kb
Host smart-14e38568-a077-4767-8811-be09e7ec14cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255973586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1255973586
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.3764966545
Short name T1187
Test name
Test status
Simulation time 2978987674 ps
CPU time 5.39 seconds
Started Jan 21 10:17:23 PM PST 24
Finished Jan 21 10:17:34 PM PST 24
Peak memory 243640 kb
Host smart-7e713731-9881-40af-9ffc-7f994cbc8599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764966545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3764966545
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1605705809
Short name T802
Test name
Test status
Simulation time 325296282062 ps
CPU time 4549.85 seconds
Started Jan 21 10:17:22 PM PST 24
Finished Jan 21 11:33:19 PM PST 24
Peak memory 276800 kb
Host smart-f41134fe-1819-4db3-8bbb-af2b76146b5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605705809 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.1605705809
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.3619229646
Short name T473
Test name
Test status
Simulation time 238759820 ps
CPU time 2.13 seconds
Started Jan 21 10:12:14 PM PST 24
Finished Jan 21 10:12:18 PM PST 24
Peak memory 239748 kb
Host smart-ea114bce-5266-4984-be08-2fc65d955851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619229646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3619229646
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.639637175
Short name T628
Test name
Test status
Simulation time 1212861354 ps
CPU time 7.78 seconds
Started Jan 21 10:12:11 PM PST 24
Finished Jan 21 10:12:21 PM PST 24
Peak memory 238800 kb
Host smart-7352345a-23a9-48a4-87b6-f6226f7946a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639637175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.639637175
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.110612873
Short name T306
Test name
Test status
Simulation time 196860199 ps
CPU time 4.46 seconds
Started Jan 21 10:12:08 PM PST 24
Finished Jan 21 10:12:16 PM PST 24
Peak memory 238760 kb
Host smart-27f11463-22d4-43a9-96bf-3f21cebd5533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110612873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.110612873
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.3813114221
Short name T321
Test name
Test status
Simulation time 126443845 ps
CPU time 5.67 seconds
Started Jan 21 10:48:28 PM PST 24
Finished Jan 21 10:48:35 PM PST 24
Peak memory 242744 kb
Host smart-71983a12-b2fc-4007-a1f3-a0f4221e6d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813114221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3813114221
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3430717888
Short name T959
Test name
Test status
Simulation time 800498997 ps
CPU time 11.16 seconds
Started Jan 21 10:12:08 PM PST 24
Finished Jan 21 10:12:23 PM PST 24
Peak memory 238784 kb
Host smart-95be666b-712c-4b97-92cd-89ef94420dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430717888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3430717888
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.3100893870
Short name T864
Test name
Test status
Simulation time 199273883 ps
CPU time 3.97 seconds
Started Jan 21 10:12:10 PM PST 24
Finished Jan 21 10:12:17 PM PST 24
Peak memory 238732 kb
Host smart-5363b634-237d-4cd8-9b01-f2f6528e30fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100893870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3100893870
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.2907454395
Short name T840
Test name
Test status
Simulation time 457828680 ps
CPU time 10.46 seconds
Started Jan 21 10:12:04 PM PST 24
Finished Jan 21 10:12:17 PM PST 24
Peak memory 238888 kb
Host smart-d34e3c44-2d65-4ada-b48f-f91f4d891452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907454395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2907454395
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.3837811261
Short name T704
Test name
Test status
Simulation time 522069289 ps
CPU time 6.86 seconds
Started Jan 21 10:12:11 PM PST 24
Finished Jan 21 10:12:20 PM PST 24
Peak memory 238888 kb
Host smart-dc920d32-0ef6-4d12-ba83-102ce65ef192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837811261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.3837811261
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.349644081
Short name T87
Test name
Test status
Simulation time 1316832332 ps
CPU time 6.54 seconds
Started Jan 21 10:12:08 PM PST 24
Finished Jan 21 10:12:18 PM PST 24
Peak memory 238804 kb
Host smart-8552d8f7-b733-4e85-94e0-6ec20edd9ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349644081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.349644081
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.1128384644
Short name T643
Test name
Test status
Simulation time 733586376 ps
CPU time 20.56 seconds
Started Jan 21 10:12:07 PM PST 24
Finished Jan 21 10:12:31 PM PST 24
Peak memory 238760 kb
Host smart-7f46c23b-2e7e-4d01-8049-16c9c2d980b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128384644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1128384644
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3398460150
Short name T1264
Test name
Test status
Simulation time 344796386 ps
CPU time 3.85 seconds
Started Jan 21 10:12:06 PM PST 24
Finished Jan 21 10:12:12 PM PST 24
Peak memory 238696 kb
Host smart-ea9003a0-500d-432f-8e04-419366d3a44d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398460150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3398460150
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.809306255
Short name T511
Test name
Test status
Simulation time 2679304755 ps
CPU time 7.34 seconds
Started Jan 21 10:12:00 PM PST 24
Finished Jan 21 10:12:10 PM PST 24
Peak memory 238820 kb
Host smart-aa023ba5-e617-4b38-a64a-8058539ce79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809306255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.809306255
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.3691928092
Short name T958
Test name
Test status
Simulation time 47332642110 ps
CPU time 92.44 seconds
Started Jan 21 10:12:14 PM PST 24
Finished Jan 21 10:13:48 PM PST 24
Peak memory 247112 kb
Host smart-bbf6a6bb-5330-4b41-ae9b-536a046f1977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691928092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
3691928092
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.3129701242
Short name T1190
Test name
Test status
Simulation time 650332216890 ps
CPU time 3662.07 seconds
Started Jan 21 10:12:12 PM PST 24
Finished Jan 21 11:13:16 PM PST 24
Peak memory 271728 kb
Host smart-bdccce44-ecce-4fa7-a82e-593f4e855cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129701242 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.3129701242
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.4232371732
Short name T1
Test name
Test status
Simulation time 1529918486 ps
CPU time 14.52 seconds
Started Jan 21 10:12:13 PM PST 24
Finished Jan 21 10:12:29 PM PST 24
Peak memory 243736 kb
Host smart-2b706268-5aa3-4d28-a491-8d52662aa7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232371732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.4232371732
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1914223368
Short name T1111
Test name
Test status
Simulation time 135531315 ps
CPU time 4.99 seconds
Started Jan 21 10:17:24 PM PST 24
Finished Jan 21 10:17:35 PM PST 24
Peak memory 240748 kb
Host smart-2f86f93f-7ad9-46a8-92b9-0118884242f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914223368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1914223368
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.500047811
Short name T1068
Test name
Test status
Simulation time 607411281 ps
CPU time 7.61 seconds
Started Jan 21 10:17:24 PM PST 24
Finished Jan 21 10:17:38 PM PST 24
Peak memory 238788 kb
Host smart-f57f10b2-9e64-4ed8-a712-0a6894e01968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500047811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.500047811
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3618714576
Short name T746
Test name
Test status
Simulation time 113976342 ps
CPU time 4.02 seconds
Started Jan 21 10:17:18 PM PST 24
Finished Jan 21 10:17:31 PM PST 24
Peak memory 241416 kb
Host smart-4ee5e943-8941-430a-94b7-d05de57b358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618714576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3618714576
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3378561750
Short name T1000
Test name
Test status
Simulation time 255555966 ps
CPU time 5.88 seconds
Started Jan 21 10:17:20 PM PST 24
Finished Jan 21 10:17:33 PM PST 24
Peak memory 238664 kb
Host smart-edd45051-9082-4454-9a11-188c109885d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378561750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3378561750
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1798600153
Short name T1156
Test name
Test status
Simulation time 260455160 ps
CPU time 4.47 seconds
Started Jan 21 10:17:20 PM PST 24
Finished Jan 21 10:17:32 PM PST 24
Peak memory 238664 kb
Host smart-62c2822b-45ea-460f-8b81-2c96385e0ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798600153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1798600153
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.3691305155
Short name T1218
Test name
Test status
Simulation time 3903603248 ps
CPU time 12.01 seconds
Started Jan 21 10:17:32 PM PST 24
Finished Jan 21 10:17:48 PM PST 24
Peak memory 243892 kb
Host smart-097845f9-9e1f-4fbc-8bf2-6379ac4723fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691305155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3691305155
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.3547258956
Short name T293
Test name
Test status
Simulation time 465128131371 ps
CPU time 3665.59 seconds
Started Jan 21 10:17:36 PM PST 24
Finished Jan 21 11:18:45 PM PST 24
Peak memory 854656 kb
Host smart-3c38a290-69f3-4ea1-a36d-e2588b5f96d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547258956 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.3547258956
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.3018007596
Short name T170
Test name
Test status
Simulation time 271746934 ps
CPU time 3.47 seconds
Started Jan 21 10:17:32 PM PST 24
Finished Jan 21 10:17:39 PM PST 24
Peak memory 241092 kb
Host smart-c0fe5eb7-bcfb-4504-a474-9a38af781051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018007596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3018007596
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.919179740
Short name T340
Test name
Test status
Simulation time 725326082 ps
CPU time 4.52 seconds
Started Jan 21 10:17:28 PM PST 24
Finished Jan 21 10:17:37 PM PST 24
Peak memory 238860 kb
Host smart-617eb496-eaaa-4c78-9789-e9ac27d2a96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919179740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.919179740
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.2134453251
Short name T723
Test name
Test status
Simulation time 1196759351045 ps
CPU time 4713.52 seconds
Started Jan 21 10:17:39 PM PST 24
Finished Jan 21 11:36:16 PM PST 24
Peak memory 913420 kb
Host smart-4159bcfc-2986-4948-bbd6-5388145d5778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134453251 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.2134453251
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.143714914
Short name T897
Test name
Test status
Simulation time 299416228 ps
CPU time 4.21 seconds
Started Jan 21 10:17:40 PM PST 24
Finished Jan 21 10:17:48 PM PST 24
Peak memory 240896 kb
Host smart-6f85ed73-a747-4125-9437-6ba4f4f09518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143714914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.143714914
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1391761374
Short name T1048
Test name
Test status
Simulation time 191617013 ps
CPU time 2.65 seconds
Started Jan 21 10:17:43 PM PST 24
Finished Jan 21 10:17:50 PM PST 24
Peak memory 238864 kb
Host smart-539f5229-2cb7-4b00-9f2e-72d614ffbc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391761374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1391761374
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3279330463
Short name T586
Test name
Test status
Simulation time 211070101965 ps
CPU time 2542.38 seconds
Started Jan 21 10:17:41 PM PST 24
Finished Jan 21 11:00:07 PM PST 24
Peak memory 757240 kb
Host smart-01dbf194-d360-4204-83fe-4643af7525e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279330463 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.3279330463
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.970793955
Short name T989
Test name
Test status
Simulation time 172765832 ps
CPU time 4.38 seconds
Started Jan 21 10:17:38 PM PST 24
Finished Jan 21 10:17:45 PM PST 24
Peak memory 238696 kb
Host smart-fe5034c8-4866-41f7-9e30-489fd54a1c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970793955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.970793955
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.1305377237
Short name T638
Test name
Test status
Simulation time 216290480 ps
CPU time 3.54 seconds
Started Jan 21 10:17:40 PM PST 24
Finished Jan 21 10:17:47 PM PST 24
Peak memory 238676 kb
Host smart-21b3e490-b28b-4d10-80eb-461425c2b16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305377237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1305377237
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.105102720
Short name T194
Test name
Test status
Simulation time 5413170112607 ps
CPU time 9241.09 seconds
Started Jan 21 10:17:38 PM PST 24
Finished Jan 22 12:51:42 AM PST 24
Peak memory 951668 kb
Host smart-f5bf7e83-80b6-4e55-976a-fd8cc303c04f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105102720 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.105102720
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.3178720700
Short name T937
Test name
Test status
Simulation time 650478688 ps
CPU time 4.94 seconds
Started Jan 21 10:17:41 PM PST 24
Finished Jan 21 10:17:50 PM PST 24
Peak memory 238776 kb
Host smart-90b3a119-cc0a-4a32-bf7b-efdc4698c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178720700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3178720700
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.938835648
Short name T973
Test name
Test status
Simulation time 94231801 ps
CPU time 3.55 seconds
Started Jan 21 10:17:45 PM PST 24
Finished Jan 21 10:17:54 PM PST 24
Peak memory 242808 kb
Host smart-6c7661b3-5f1f-4636-850f-f0c43fe449ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938835648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.938835648
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1018525673
Short name T361
Test name
Test status
Simulation time 197052402158 ps
CPU time 2059.09 seconds
Started Jan 21 10:17:41 PM PST 24
Finished Jan 21 10:52:04 PM PST 24
Peak memory 285392 kb
Host smart-30588e18-cfb9-468a-a0f2-ed36ba358b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018525673 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.1018525673
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.2909903941
Short name T967
Test name
Test status
Simulation time 123341530 ps
CPU time 4.27 seconds
Started Jan 21 10:17:46 PM PST 24
Finished Jan 21 10:17:56 PM PST 24
Peak memory 238620 kb
Host smart-ab852a8b-7807-46ad-8980-04bbc9f2abe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909903941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2909903941
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.1501156111
Short name T915
Test name
Test status
Simulation time 783555091 ps
CPU time 6.04 seconds
Started Jan 21 10:17:42 PM PST 24
Finished Jan 21 10:17:52 PM PST 24
Peak memory 242632 kb
Host smart-14b0f82d-a1c3-4620-90d8-c8c8deb90313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501156111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1501156111
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.775658502
Short name T198
Test name
Test status
Simulation time 1437865528750 ps
CPU time 6535.1 seconds
Started Jan 21 10:17:44 PM PST 24
Finished Jan 22 12:06:44 AM PST 24
Peak memory 279788 kb
Host smart-78769e1a-1ab8-49e4-98ab-b714f04e13cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775658502 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.775658502
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3658829204
Short name T558
Test name
Test status
Simulation time 566508213 ps
CPU time 5.52 seconds
Started Jan 21 10:17:44 PM PST 24
Finished Jan 21 10:17:55 PM PST 24
Peak memory 238764 kb
Host smart-976e83d8-e118-4441-8142-a157e07e465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658829204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3658829204
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.4017012150
Short name T573
Test name
Test status
Simulation time 2262049856 ps
CPU time 6.5 seconds
Started Jan 21 10:17:40 PM PST 24
Finished Jan 21 10:17:50 PM PST 24
Peak memory 238904 kb
Host smart-4adac318-94a9-4bb0-b5fe-cbb790330544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017012150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.4017012150
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1152347081
Short name T871
Test name
Test status
Simulation time 344246038261 ps
CPU time 5746.39 seconds
Started Jan 21 10:17:38 PM PST 24
Finished Jan 21 11:53:28 PM PST 24
Peak memory 944012 kb
Host smart-eabe5539-3fce-4c60-b72d-cfbd46ff5f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152347081 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.1152347081
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.3130671999
Short name T1291
Test name
Test status
Simulation time 2383923401 ps
CPU time 7.03 seconds
Started Jan 21 10:17:46 PM PST 24
Finished Jan 21 10:17:59 PM PST 24
Peak memory 241668 kb
Host smart-0ca2f3c7-c99a-4a8e-9b27-9946eb5e088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130671999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.3130671999
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.4177285988
Short name T1146
Test name
Test status
Simulation time 1252585215 ps
CPU time 9.78 seconds
Started Jan 21 10:17:43 PM PST 24
Finished Jan 21 10:17:56 PM PST 24
Peak memory 244904 kb
Host smart-ca6062de-2e3f-470d-955c-91465f3346aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177285988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.4177285988
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1771100636
Short name T278
Test name
Test status
Simulation time 3509507360674 ps
CPU time 4286.02 seconds
Started Jan 21 10:17:42 PM PST 24
Finished Jan 21 11:29:12 PM PST 24
Peak memory 927132 kb
Host smart-32a98991-1290-4d4a-b366-373212c2a026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771100636 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.1771100636
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.840784539
Short name T503
Test name
Test status
Simulation time 101454028 ps
CPU time 1.88 seconds
Started Jan 21 10:12:20 PM PST 24
Finished Jan 21 10:12:24 PM PST 24
Peak memory 239600 kb
Host smart-521ff177-3c9e-4a3f-8400-2b280d742223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840784539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.840784539
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.3804235433
Short name T660
Test name
Test status
Simulation time 347041981 ps
CPU time 7.34 seconds
Started Jan 21 10:12:11 PM PST 24
Finished Jan 21 10:12:20 PM PST 24
Peak memory 247028 kb
Host smart-4fcbdead-746a-4be4-bb61-c384468a30c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804235433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3804235433
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.4263518440
Short name T720
Test name
Test status
Simulation time 1393820343 ps
CPU time 11.76 seconds
Started Jan 21 10:12:21 PM PST 24
Finished Jan 21 10:12:34 PM PST 24
Peak memory 238848 kb
Host smart-9fcc9562-5df3-453f-8673-8319638ee488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263518440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.4263518440
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.3645771939
Short name T975
Test name
Test status
Simulation time 871219609 ps
CPU time 14.06 seconds
Started Jan 21 10:12:19 PM PST 24
Finished Jan 21 10:12:35 PM PST 24
Peak memory 245288 kb
Host smart-c4c106ec-e145-4f1d-b604-247668172b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645771939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3645771939
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.401225354
Short name T626
Test name
Test status
Simulation time 682215193 ps
CPU time 11.08 seconds
Started Jan 21 10:12:19 PM PST 24
Finished Jan 21 10:12:32 PM PST 24
Peak memory 247032 kb
Host smart-997f3a9f-ce9e-4fb4-a3fb-115a9adeb9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401225354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.401225354
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.4049207896
Short name T846
Test name
Test status
Simulation time 198460512 ps
CPU time 4.67 seconds
Started Jan 21 10:12:10 PM PST 24
Finished Jan 21 10:12:17 PM PST 24
Peak memory 238788 kb
Host smart-808b2ca0-29bb-427f-b087-1c8c9bd2272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049207896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.4049207896
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.4546794
Short name T1058
Test name
Test status
Simulation time 4822641201 ps
CPU time 10.88 seconds
Started Jan 21 10:24:36 PM PST 24
Finished Jan 21 10:24:52 PM PST 24
Peak memory 247032 kb
Host smart-31795c24-3d47-48e4-99d3-1f65a6031db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4546794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.4546794
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.3542569707
Short name T358
Test name
Test status
Simulation time 13050117066 ps
CPU time 24.13 seconds
Started Jan 21 10:12:20 PM PST 24
Finished Jan 21 10:12:46 PM PST 24
Peak memory 246976 kb
Host smart-3c04d9f9-0dcd-4035-a7c9-b9fa9f296609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542569707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.3542569707
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.3336784421
Short name T479
Test name
Test status
Simulation time 395590012 ps
CPU time 3.62 seconds
Started Jan 21 10:12:11 PM PST 24
Finished Jan 21 10:12:16 PM PST 24
Peak memory 241612 kb
Host smart-4735037a-030a-401e-b79e-3ef3af1ce793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336784421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3336784421
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2240814695
Short name T1234
Test name
Test status
Simulation time 167304552 ps
CPU time 3.04 seconds
Started Jan 21 10:12:14 PM PST 24
Finished Jan 21 10:12:19 PM PST 24
Peak memory 238656 kb
Host smart-1ab7782b-6f5d-4d1c-8936-dea9cd56dd2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240814695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2240814695
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.2166816222
Short name T770
Test name
Test status
Simulation time 215938009 ps
CPU time 5.56 seconds
Started Jan 21 10:12:19 PM PST 24
Finished Jan 21 10:12:26 PM PST 24
Peak memory 238804 kb
Host smart-f49895f6-5ada-405f-b98f-c41d7a4bca6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166816222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.2166816222
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.3487616099
Short name T1083
Test name
Test status
Simulation time 225543989 ps
CPU time 4.91 seconds
Started Jan 21 10:12:13 PM PST 24
Finished Jan 21 10:12:19 PM PST 24
Peak memory 238756 kb
Host smart-ae06acc1-2e59-4695-ac4f-e7d5dc60b581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487616099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3487616099
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3276998276
Short name T352
Test name
Test status
Simulation time 44665303849 ps
CPU time 138.78 seconds
Started Jan 21 10:36:12 PM PST 24
Finished Jan 21 10:38:32 PM PST 24
Peak memory 241728 kb
Host smart-75c0ca5a-f1a5-426b-affb-ffb8ed2ace70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276998276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3276998276
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1365810312
Short name T1099
Test name
Test status
Simulation time 290374226164 ps
CPU time 2344.32 seconds
Started Jan 21 10:12:19 PM PST 24
Finished Jan 21 10:51:25 PM PST 24
Peak memory 262980 kb
Host smart-4dd1e490-67d4-4391-be2d-9c95cdf6c112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365810312 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.1365810312
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.3038864867
Short name T530
Test name
Test status
Simulation time 2563525472 ps
CPU time 22.48 seconds
Started Jan 21 10:12:15 PM PST 24
Finished Jan 21 10:12:39 PM PST 24
Peak memory 244348 kb
Host smart-98d9be66-38b2-4fb3-aaaf-35aac62e1ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038864867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.3038864867
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.2814461009
Short name T1233
Test name
Test status
Simulation time 126807278 ps
CPU time 3.3 seconds
Started Jan 21 10:17:42 PM PST 24
Finished Jan 21 10:17:50 PM PST 24
Peak memory 247164 kb
Host smart-3472bee6-694c-4b51-a8e9-e7cf26970b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814461009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2814461009
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.3792219548
Short name T828
Test name
Test status
Simulation time 369982073 ps
CPU time 4.45 seconds
Started Jan 21 10:17:44 PM PST 24
Finished Jan 21 10:17:53 PM PST 24
Peak memory 238768 kb
Host smart-da2524ea-6bc5-430f-bb27-8b091868aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792219548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3792219548
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1890000313
Short name T1118
Test name
Test status
Simulation time 2216262366106 ps
CPU time 4473.36 seconds
Started Jan 21 10:17:41 PM PST 24
Finished Jan 21 11:32:18 PM PST 24
Peak memory 346788 kb
Host smart-f7cc9387-0ad1-48b3-90a2-3a3705ab5a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890000313 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1890000313
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.3564744515
Short name T532
Test name
Test status
Simulation time 6748541440 ps
CPU time 22.7 seconds
Started Jan 21 10:17:47 PM PST 24
Finished Jan 21 10:18:16 PM PST 24
Peak memory 247028 kb
Host smart-1c5a7d01-352a-4162-b41f-6ce7c6a55118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564744515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3564744515
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.674278107
Short name T1089
Test name
Test status
Simulation time 2461350046 ps
CPU time 5.84 seconds
Started Jan 21 10:17:43 PM PST 24
Finished Jan 21 10:17:53 PM PST 24
Peak memory 238836 kb
Host smart-f9d63769-68ba-4ae5-ba4d-e2c38ad05741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674278107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.674278107
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.171933031
Short name T1112
Test name
Test status
Simulation time 215948269 ps
CPU time 5.17 seconds
Started Jan 21 10:17:44 PM PST 24
Finished Jan 21 10:17:54 PM PST 24
Peak memory 242800 kb
Host smart-3a2bd470-99df-4dba-bb09-87876c363a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171933031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.171933031
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.3112602334
Short name T14
Test name
Test status
Simulation time 2157811681596 ps
CPU time 2989.74 seconds
Started Jan 21 10:17:44 PM PST 24
Finished Jan 21 11:07:39 PM PST 24
Peak memory 263192 kb
Host smart-349dd1e1-791a-469f-b0b2-bb9d1ff4b63e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112602334 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.3112602334
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.3204842132
Short name T55
Test name
Test status
Simulation time 2411634413 ps
CPU time 5.78 seconds
Started Jan 21 10:17:42 PM PST 24
Finished Jan 21 10:17:52 PM PST 24
Peak memory 238856 kb
Host smart-6aa07d1a-ff44-4d76-9727-194a1bd9558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204842132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3204842132
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.2511977763
Short name T927
Test name
Test status
Simulation time 401564509 ps
CPU time 8.97 seconds
Started Jan 21 10:17:49 PM PST 24
Finished Jan 21 10:18:05 PM PST 24
Peak memory 238752 kb
Host smart-dd20067b-15f4-4286-ba08-17773e719314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511977763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2511977763
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2981264345
Short name T197
Test name
Test status
Simulation time 4373419869415 ps
CPU time 10368.1 seconds
Started Jan 21 10:17:48 PM PST 24
Finished Jan 22 01:10:43 AM PST 24
Peak memory 1099832 kb
Host smart-847846fa-b743-4944-afdf-f09130c7012e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981264345 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.2981264345
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.2662504773
Short name T537
Test name
Test status
Simulation time 175777812 ps
CPU time 3.44 seconds
Started Jan 21 10:17:43 PM PST 24
Finished Jan 21 10:17:51 PM PST 24
Peak memory 246964 kb
Host smart-c9d12176-d8e2-4eff-a2a5-6e0e82a41074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662504773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2662504773
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.168943512
Short name T519
Test name
Test status
Simulation time 110150914 ps
CPU time 4.08 seconds
Started Jan 21 10:17:44 PM PST 24
Finished Jan 21 10:17:53 PM PST 24
Peak memory 241788 kb
Host smart-6e4eac25-92a6-4c52-95d5-8cabc17037c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168943512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.168943512
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3824150020
Short name T90
Test name
Test status
Simulation time 232411120 ps
CPU time 3.25 seconds
Started Jan 21 10:17:48 PM PST 24
Finished Jan 21 10:17:58 PM PST 24
Peak memory 238688 kb
Host smart-ddad9d78-fa46-4954-aa49-acb9e61317f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824150020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3824150020
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.3921441416
Short name T807
Test name
Test status
Simulation time 2090632993 ps
CPU time 8.81 seconds
Started Jan 21 10:17:44 PM PST 24
Finished Jan 21 10:17:57 PM PST 24
Peak memory 243180 kb
Host smart-d339265a-3683-4b81-a714-0a77df79a276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921441416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3921441416
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.1899338751
Short name T1211
Test name
Test status
Simulation time 2639929512312 ps
CPU time 3577.88 seconds
Started Jan 21 10:17:49 PM PST 24
Finished Jan 21 11:17:34 PM PST 24
Peak memory 275228 kb
Host smart-7594f1cb-3d46-4fc1-a89c-469abc80b092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899338751 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.1899338751
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.675064539
Short name T163
Test name
Test status
Simulation time 1561534503 ps
CPU time 3.47 seconds
Started Jan 21 10:17:48 PM PST 24
Finished Jan 21 10:17:58 PM PST 24
Peak memory 238688 kb
Host smart-3b49c739-7a23-49a0-83c5-914f57ee596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675064539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.675064539
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.1487569236
Short name T1034
Test name
Test status
Simulation time 352526581 ps
CPU time 4.76 seconds
Started Jan 21 10:17:48 PM PST 24
Finished Jan 21 10:18:00 PM PST 24
Peak memory 238604 kb
Host smart-3f26cadc-061c-4c26-9052-dc00f894d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487569236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1487569236
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1760116403
Short name T212
Test name
Test status
Simulation time 2734249030407 ps
CPU time 4367.01 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 11:31:01 PM PST 24
Peak memory 284804 kb
Host smart-b05b7871-cf1f-4d5c-8f6d-4fe648db9178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760116403 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.1760116403
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.3922514870
Short name T1166
Test name
Test status
Simulation time 99720472 ps
CPU time 2.98 seconds
Started Jan 21 10:17:47 PM PST 24
Finished Jan 21 10:17:57 PM PST 24
Peak memory 241068 kb
Host smart-a0aca046-e9d4-4e0b-92ce-2c92bc3738f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922514870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3922514870
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1470086131
Short name T344
Test name
Test status
Simulation time 605695320 ps
CPU time 7.76 seconds
Started Jan 21 10:17:50 PM PST 24
Finished Jan 21 10:18:05 PM PST 24
Peak memory 242980 kb
Host smart-8244f2f7-0ad4-4801-abbc-4de2c62e3316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470086131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1470086131
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.678596093
Short name T751
Test name
Test status
Simulation time 2013383600 ps
CPU time 4.75 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:18:18 PM PST 24
Peak memory 241404 kb
Host smart-f1817f68-2461-4789-a835-7e9475d4f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678596093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.678596093
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.37023220
Short name T1176
Test name
Test status
Simulation time 194416287108 ps
CPU time 2328.95 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:57:02 PM PST 24
Peak memory 261956 kb
Host smart-729f494e-9c27-434d-be89-e2b1e3e0d585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37023220 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.37023220
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.949479253
Short name T25
Test name
Test status
Simulation time 1997838533 ps
CPU time 4.89 seconds
Started Jan 21 10:17:50 PM PST 24
Finished Jan 21 10:18:02 PM PST 24
Peak memory 246976 kb
Host smart-4f89281e-2c9c-479d-a221-12bc8cdaeaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949479253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.949479253
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.3781246084
Short name T453
Test name
Test status
Simulation time 338321484 ps
CPU time 8.57 seconds
Started Jan 21 10:17:50 PM PST 24
Finished Jan 21 10:18:06 PM PST 24
Peak memory 237952 kb
Host smart-2e33642f-44b6-4676-92c3-2dec81f96258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781246084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3781246084
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.1396506184
Short name T1265
Test name
Test status
Simulation time 208675875 ps
CPU time 2.29 seconds
Started Jan 21 10:12:42 PM PST 24
Finished Jan 21 10:12:47 PM PST 24
Peak memory 239744 kb
Host smart-5079b1c1-d5ef-480f-aa24-b8f7747beead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396506184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1396506184
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.3711407332
Short name T898
Test name
Test status
Simulation time 1142103987 ps
CPU time 12.51 seconds
Started Jan 21 10:12:23 PM PST 24
Finished Jan 21 10:12:37 PM PST 24
Peak memory 244000 kb
Host smart-c8f9362f-e13a-4ea4-bd46-cdd663963723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711407332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3711407332
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2377278275
Short name T774
Test name
Test status
Simulation time 1134650607 ps
CPU time 15.15 seconds
Started Jan 21 10:12:37 PM PST 24
Finished Jan 21 10:12:54 PM PST 24
Peak memory 238760 kb
Host smart-3323c391-f962-41b1-800f-2d08113a34dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377278275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2377278275
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1534387769
Short name T884
Test name
Test status
Simulation time 856623089 ps
CPU time 12.49 seconds
Started Jan 21 10:12:35 PM PST 24
Finished Jan 21 10:12:49 PM PST 24
Peak memory 244432 kb
Host smart-c82859de-fb09-4ef0-bf9e-2a43ecb2d30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534387769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1534387769
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.3686496764
Short name T96
Test name
Test status
Simulation time 731892134 ps
CPU time 13.84 seconds
Started Jan 21 10:58:39 PM PST 24
Finished Jan 21 10:58:54 PM PST 24
Peak memory 246932 kb
Host smart-d225f301-418f-4eda-901f-7f8c3c76a682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686496764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.3686496764
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2761472648
Short name T1167
Test name
Test status
Simulation time 133472107 ps
CPU time 4.61 seconds
Started Jan 21 10:31:17 PM PST 24
Finished Jan 21 10:31:31 PM PST 24
Peak memory 246956 kb
Host smart-a3c01e40-067b-4772-9a55-6b1cab3733a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761472648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2761472648
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.3953177165
Short name T1276
Test name
Test status
Simulation time 907498634 ps
CPU time 20.76 seconds
Started Jan 21 10:12:37 PM PST 24
Finished Jan 21 10:13:00 PM PST 24
Peak memory 247048 kb
Host smart-9ea05f09-e497-4407-a161-e1881f02f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953177165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3953177165
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2945130082
Short name T815
Test name
Test status
Simulation time 11465109655 ps
CPU time 19.9 seconds
Started Jan 21 10:12:38 PM PST 24
Finished Jan 21 10:13:00 PM PST 24
Peak memory 238856 kb
Host smart-3610fe45-293c-4091-b815-cffcc3bb66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945130082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2945130082
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.3836208717
Short name T463
Test name
Test status
Simulation time 678827083 ps
CPU time 4.93 seconds
Started Jan 21 10:28:12 PM PST 24
Finished Jan 21 10:28:19 PM PST 24
Peak memory 238700 kb
Host smart-0a298615-43eb-40fb-812d-830afafe07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836208717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.3836208717
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.4026730733
Short name T571
Test name
Test status
Simulation time 1180395460 ps
CPU time 12.42 seconds
Started Jan 21 10:12:24 PM PST 24
Finished Jan 21 10:12:38 PM PST 24
Peak memory 238720 kb
Host smart-52758c81-acd9-4559-bb59-a813a1229762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026730733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.4026730733
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3062704815
Short name T337
Test name
Test status
Simulation time 3567362194 ps
CPU time 7.6 seconds
Started Jan 21 10:12:36 PM PST 24
Finished Jan 21 10:12:46 PM PST 24
Peak memory 243312 kb
Host smart-4b742eb3-b861-4e72-8449-a83775950c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062704815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3062704815
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.3864630371
Short name T1290
Test name
Test status
Simulation time 296315371 ps
CPU time 5.09 seconds
Started Jan 21 10:37:59 PM PST 24
Finished Jan 21 10:38:07 PM PST 24
Peak memory 239844 kb
Host smart-2c9df1d5-593f-4236-b225-b76db19109d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864630371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3864630371
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.91766127
Short name T996
Test name
Test status
Simulation time 9530401238 ps
CPU time 111.89 seconds
Started Jan 21 10:12:43 PM PST 24
Finished Jan 21 10:14:38 PM PST 24
Peak memory 247140 kb
Host smart-f326d7c6-b78c-4323-af6b-7181873cba1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91766127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.91766127
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.999844944
Short name T651
Test name
Test status
Simulation time 2994042199 ps
CPU time 25.16 seconds
Started Jan 21 10:12:37 PM PST 24
Finished Jan 21 10:13:04 PM PST 24
Peak memory 238888 kb
Host smart-dd416415-e23e-4e72-987a-7bf84dc0f188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999844944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.999844944
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.1670532157
Short name T1035
Test name
Test status
Simulation time 153338535 ps
CPU time 3.97 seconds
Started Jan 21 11:19:28 PM PST 24
Finished Jan 21 11:19:33 PM PST 24
Peak memory 243100 kb
Host smart-fd952122-316f-4cd4-84ee-a6261e19e15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670532157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.1670532157
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1971422177
Short name T295
Test name
Test status
Simulation time 53473167660 ps
CPU time 1225.75 seconds
Started Jan 21 10:17:50 PM PST 24
Finished Jan 21 10:38:23 PM PST 24
Peak memory 267816 kb
Host smart-f41bc329-f9d6-4e04-98d7-6ae78f33c05e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971422177 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1971422177
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.864659118
Short name T1201
Test name
Test status
Simulation time 280711382 ps
CPU time 4.09 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:18:18 PM PST 24
Peak memory 238692 kb
Host smart-54bf45b8-9ea1-4a1f-8aa1-d145bf4a5895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864659118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.864659118
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.2370953691
Short name T1182
Test name
Test status
Simulation time 431449985 ps
CPU time 5.42 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:18:18 PM PST 24
Peak memory 242748 kb
Host smart-0b0af6d8-b6c1-49f4-8f07-8b7236e9a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370953691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2370953691
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3484205128
Short name T637
Test name
Test status
Simulation time 256456557003 ps
CPU time 2511.72 seconds
Started Jan 21 10:18:00 PM PST 24
Finished Jan 21 11:00:02 PM PST 24
Peak memory 299804 kb
Host smart-e0bf643a-dcdf-44ac-a6cd-d92c69c63ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484205128 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.3484205128
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1550369951
Short name T40
Test name
Test status
Simulation time 339528285 ps
CPU time 3.76 seconds
Started Jan 21 10:17:54 PM PST 24
Finished Jan 21 10:18:06 PM PST 24
Peak memory 238812 kb
Host smart-ed1c8685-b4c0-4abf-a88e-66be380234b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550369951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1550369951
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.28730732
Short name T314
Test name
Test status
Simulation time 470654932 ps
CPU time 5.57 seconds
Started Jan 21 10:17:55 PM PST 24
Finished Jan 21 10:18:10 PM PST 24
Peak memory 242948 kb
Host smart-b452a908-92de-41a7-8308-d3e890ebfc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28730732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.28730732
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.1775183960
Short name T705
Test name
Test status
Simulation time 137611313 ps
CPU time 3.58 seconds
Started Jan 21 10:17:57 PM PST 24
Finished Jan 21 10:18:10 PM PST 24
Peak memory 246968 kb
Host smart-de5c1b6c-458c-44d0-a8d7-8ce24890ebbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775183960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1775183960
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.992314767
Short name T1241
Test name
Test status
Simulation time 136711500 ps
CPU time 3.38 seconds
Started Jan 21 10:17:54 PM PST 24
Finished Jan 21 10:18:05 PM PST 24
Peak memory 241004 kb
Host smart-0176cf4b-2c9b-4080-9ff1-51a4c10f2e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992314767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.992314767
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2992813743
Short name T196
Test name
Test status
Simulation time 168096943976 ps
CPU time 3555.23 seconds
Started Jan 21 10:17:58 PM PST 24
Finished Jan 21 11:17:23 PM PST 24
Peak memory 732168 kb
Host smart-7a0e065f-f80b-46d1-8ccb-aef163cdc5ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992813743 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.2992813743
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.4257325319
Short name T644
Test name
Test status
Simulation time 1768827544 ps
CPU time 6.19 seconds
Started Jan 21 10:17:56 PM PST 24
Finished Jan 21 10:18:12 PM PST 24
Peak memory 238788 kb
Host smart-cc1b1546-0cac-443b-a5f8-cec4bb26a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257325319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.4257325319
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1518138281
Short name T466
Test name
Test status
Simulation time 179726171 ps
CPU time 3.91 seconds
Started Jan 21 10:18:00 PM PST 24
Finished Jan 21 10:18:14 PM PST 24
Peak memory 238624 kb
Host smart-260e36c8-22b7-484a-8626-387be14dc532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518138281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1518138281
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2600481513
Short name T679
Test name
Test status
Simulation time 544460791159 ps
CPU time 6021.93 seconds
Started Jan 21 10:17:59 PM PST 24
Finished Jan 21 11:58:31 PM PST 24
Peak memory 951684 kb
Host smart-aecae55c-4ba1-4ca6-bf41-29dec653aea1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600481513 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.2600481513
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.871243134
Short name T1159
Test name
Test status
Simulation time 2243883285 ps
CPU time 6.34 seconds
Started Jan 21 10:17:58 PM PST 24
Finished Jan 21 10:18:14 PM PST 24
Peak memory 238784 kb
Host smart-a34049d0-6845-4181-bd76-1ee95df62d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871243134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.871243134
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.2751528093
Short name T91
Test name
Test status
Simulation time 2945193082 ps
CPU time 9.72 seconds
Started Jan 21 10:17:55 PM PST 24
Finished Jan 21 10:18:14 PM PST 24
Peak memory 243860 kb
Host smart-ac192a71-6ac7-4b17-89aa-9b8e0fc5dd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751528093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2751528093
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.3569469496
Short name T1260
Test name
Test status
Simulation time 519215290893 ps
CPU time 7412.8 seconds
Started Jan 21 10:18:00 PM PST 24
Finished Jan 22 12:21:44 AM PST 24
Peak memory 307160 kb
Host smart-84ddfa28-a803-40f7-b73a-02ed2e33a2a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569469496 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.3569469496
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.2481876797
Short name T484
Test name
Test status
Simulation time 447723298 ps
CPU time 4.76 seconds
Started Jan 21 10:17:58 PM PST 24
Finished Jan 21 10:18:12 PM PST 24
Peak memory 241240 kb
Host smart-bd4965ac-266a-426e-9942-606c995d4e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481876797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2481876797
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.1206011887
Short name T459
Test name
Test status
Simulation time 334099214 ps
CPU time 7.91 seconds
Started Jan 21 10:17:55 PM PST 24
Finished Jan 21 10:18:12 PM PST 24
Peak memory 246980 kb
Host smart-2535b214-1eca-4403-b26e-271dd5867f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206011887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1206011887
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.2004161167
Short name T1194
Test name
Test status
Simulation time 57732212370 ps
CPU time 1337.42 seconds
Started Jan 21 10:17:58 PM PST 24
Finished Jan 21 10:40:25 PM PST 24
Peak memory 482864 kb
Host smart-47e078d2-e2c8-4865-af97-f59b5b82eb87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004161167 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.2004161167
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3812210723
Short name T888
Test name
Test status
Simulation time 450314814 ps
CPU time 5 seconds
Started Jan 21 10:17:59 PM PST 24
Finished Jan 21 10:18:13 PM PST 24
Peak memory 243484 kb
Host smart-e1a4fc03-8d04-45cf-bd46-6138263f74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812210723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3812210723
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1636599607
Short name T383
Test name
Test status
Simulation time 395485262 ps
CPU time 4.55 seconds
Started Jan 21 10:17:58 PM PST 24
Finished Jan 21 10:18:12 PM PST 24
Peak memory 242792 kb
Host smart-2bfe6921-c54f-4dad-bce9-c83229a4e02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636599607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1636599607
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.3510015641
Short name T716
Test name
Test status
Simulation time 435644270734 ps
CPU time 6085.15 seconds
Started Jan 21 10:17:57 PM PST 24
Finished Jan 21 11:59:32 PM PST 24
Peak memory 345384 kb
Host smart-8c90dcfe-67cf-4e92-89d5-7f35794f13fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510015641 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.3510015641
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.2208740456
Short name T79
Test name
Test status
Simulation time 633915484 ps
CPU time 4.66 seconds
Started Jan 21 10:53:35 PM PST 24
Finished Jan 21 10:53:40 PM PST 24
Peak memory 241456 kb
Host smart-ce1b8e4f-10e7-4314-98fd-e886b85a69c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208740456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2208740456
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2222442470
Short name T622
Test name
Test status
Simulation time 122160537 ps
CPU time 5.01 seconds
Started Jan 21 10:17:56 PM PST 24
Finished Jan 21 10:18:10 PM PST 24
Peak memory 238792 kb
Host smart-7ef27646-d2fa-402f-8c08-96f9810ae607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222442470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2222442470
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3664658778
Short name T13
Test name
Test status
Simulation time 207108408563 ps
CPU time 2621.11 seconds
Started Jan 21 11:11:43 PM PST 24
Finished Jan 21 11:55:25 PM PST 24
Peak memory 257576 kb
Host smart-638691ce-8cbc-4345-9aee-2d4490b86b92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664658778 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.3664658778
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.111308418
Short name T78
Test name
Test status
Simulation time 763039405 ps
CPU time 4.73 seconds
Started Jan 21 10:18:06 PM PST 24
Finished Jan 21 10:18:21 PM PST 24
Peak memory 242872 kb
Host smart-9a7dee8d-cb58-4b74-8ae6-b15f19e60992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111308418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.111308418
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.2055289757
Short name T465
Test name
Test status
Simulation time 226567602 ps
CPU time 4.54 seconds
Started Jan 21 10:47:35 PM PST 24
Finished Jan 21 10:47:42 PM PST 24
Peak memory 243900 kb
Host smart-11cabbf2-1960-49cf-9680-9035334c3d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055289757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.2055289757
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3298681865
Short name T1208
Test name
Test status
Simulation time 2104107634747 ps
CPU time 7414.95 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 22 12:21:50 AM PST 24
Peak memory 963944 kb
Host smart-41a5dd0f-321a-4389-9499-1f7bb3b308fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298681865 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3298681865
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.9154445
Short name T172
Test name
Test status
Simulation time 109884100 ps
CPU time 1.67 seconds
Started Jan 21 10:12:39 PM PST 24
Finished Jan 21 10:12:44 PM PST 24
Peak memory 230536 kb
Host smart-ca2ef0c4-8c8c-470a-aab1-c5f6d0450f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9154445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.9154445
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.2203788623
Short name T1175
Test name
Test status
Simulation time 1359001907 ps
CPU time 8.5 seconds
Started Jan 21 10:12:40 PM PST 24
Finished Jan 21 10:12:51 PM PST 24
Peak memory 238856 kb
Host smart-156eff00-9ee3-4e0b-9a76-fdc919c017ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203788623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2203788623
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2609531693
Short name T52
Test name
Test status
Simulation time 1167236935 ps
CPU time 14.64 seconds
Started Jan 21 10:12:36 PM PST 24
Finished Jan 21 10:12:53 PM PST 24
Peak memory 244376 kb
Host smart-11c424e6-5d94-427d-a87d-982702929a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609531693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2609531693
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.879918198
Short name T640
Test name
Test status
Simulation time 343076018 ps
CPU time 9.95 seconds
Started Jan 21 10:12:35 PM PST 24
Finished Jan 21 10:12:46 PM PST 24
Peak memory 246096 kb
Host smart-b5ccf559-0479-4628-ab27-c990d1a00ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879918198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.879918198
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.1824749107
Short name T1141
Test name
Test status
Simulation time 10852436868 ps
CPU time 35.42 seconds
Started Jan 21 10:12:37 PM PST 24
Finished Jan 21 10:13:14 PM PST 24
Peak memory 238880 kb
Host smart-e5eee91e-737e-4350-a96f-35a24b1d81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824749107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.1824749107
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.3945743916
Short name T1237
Test name
Test status
Simulation time 301204644 ps
CPU time 3.84 seconds
Started Jan 21 10:12:38 PM PST 24
Finished Jan 21 10:12:44 PM PST 24
Peak memory 238776 kb
Host smart-a9fd2337-7394-42fc-8f88-f553fa0ae9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945743916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.3945743916
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.2151340013
Short name T728
Test name
Test status
Simulation time 4398915727 ps
CPU time 24.61 seconds
Started Jan 21 10:12:45 PM PST 24
Finished Jan 21 10:13:12 PM PST 24
Peak memory 241988 kb
Host smart-518ff696-0d2b-4444-b01f-27fa7b90d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151340013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.2151340013
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2427668900
Short name T374
Test name
Test status
Simulation time 842113149 ps
CPU time 13.52 seconds
Started Jan 21 10:12:45 PM PST 24
Finished Jan 21 10:13:01 PM PST 24
Peak memory 238768 kb
Host smart-6a9dadc5-2c5a-4984-809c-da4fb58f3b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427668900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2427668900
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1021334996
Short name T1204
Test name
Test status
Simulation time 826477150 ps
CPU time 6.32 seconds
Started Jan 21 10:12:37 PM PST 24
Finished Jan 21 10:12:45 PM PST 24
Peak memory 242600 kb
Host smart-e5ac23ae-2d7c-4837-b030-51907afbefc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021334996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1021334996
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.4274782448
Short name T642
Test name
Test status
Simulation time 4165741251 ps
CPU time 8.35 seconds
Started Jan 21 10:12:39 PM PST 24
Finished Jan 21 10:12:50 PM PST 24
Peak memory 243608 kb
Host smart-74dc9be1-c921-4aea-ae9b-146e41733730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274782448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.4274782448
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.1838390869
Short name T334
Test name
Test status
Simulation time 1512657757 ps
CPU time 5.34 seconds
Started Jan 21 10:12:54 PM PST 24
Finished Jan 21 10:13:01 PM PST 24
Peak memory 243252 kb
Host smart-21d723c5-8c02-4bb9-a7c5-2983c551f5ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838390869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1838390869
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.2616378020
Short name T485
Test name
Test status
Simulation time 561278438 ps
CPU time 4.27 seconds
Started Jan 21 10:12:36 PM PST 24
Finished Jan 21 10:12:43 PM PST 24
Peak memory 238748 kb
Host smart-9bdfd7f6-6b18-43c7-b9e8-595f5414e152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616378020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2616378020
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.2337716282
Short name T899
Test name
Test status
Simulation time 14177451077 ps
CPU time 19.28 seconds
Started Jan 21 10:12:41 PM PST 24
Finished Jan 21 10:13:03 PM PST 24
Peak memory 238888 kb
Host smart-a981c876-20fb-46ca-901b-5605e35d859d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337716282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
2337716282
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.210285476
Short name T826
Test name
Test status
Simulation time 502298262819 ps
CPU time 2290.04 seconds
Started Jan 21 10:12:42 PM PST 24
Finished Jan 21 10:50:55 PM PST 24
Peak memory 263536 kb
Host smart-be7e80d7-13e0-4afe-b20f-88a65271538f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210285476 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.210285476
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.3385919348
Short name T351
Test name
Test status
Simulation time 806220578 ps
CPU time 16.81 seconds
Started Jan 21 10:12:39 PM PST 24
Finished Jan 21 10:12:59 PM PST 24
Peak memory 238712 kb
Host smart-a2d73ea6-b9fe-442e-aa93-752c6d964ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385919348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3385919348
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.3207788731
Short name T1170
Test name
Test status
Simulation time 152071206 ps
CPU time 5.01 seconds
Started Jan 21 10:18:05 PM PST 24
Finished Jan 21 10:18:20 PM PST 24
Peak memory 238796 kb
Host smart-3c7c6d9c-4c6d-4276-891b-d07c6ffbaf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207788731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3207788731
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.2015711272
Short name T495
Test name
Test status
Simulation time 505833501 ps
CPU time 5.08 seconds
Started Jan 21 10:18:07 PM PST 24
Finished Jan 21 10:18:21 PM PST 24
Peak memory 232484 kb
Host smart-19d90d1d-685a-4859-a7bd-066519ef506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015711272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2015711272
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2707520435
Short name T1101
Test name
Test status
Simulation time 220572664145 ps
CPU time 2370.51 seconds
Started Jan 21 10:18:07 PM PST 24
Finished Jan 21 10:57:47 PM PST 24
Peak memory 264580 kb
Host smart-29043d84-44fd-47ca-b645-b481e6b71313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707520435 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.2707520435
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.813945680
Short name T824
Test name
Test status
Simulation time 126241394 ps
CPU time 4.03 seconds
Started Jan 21 10:18:08 PM PST 24
Finished Jan 21 10:18:21 PM PST 24
Peak memory 241204 kb
Host smart-65e50b1d-130d-47b5-a620-dc17863f0309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813945680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.813945680
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.4137289319
Short name T808
Test name
Test status
Simulation time 201035583 ps
CPU time 5.04 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:18:18 PM PST 24
Peak memory 242672 kb
Host smart-34ba2084-23ab-4b93-b66d-942257fbc8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137289319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.4137289319
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1318009358
Short name T1060
Test name
Test status
Simulation time 5148961077962 ps
CPU time 5745.9 seconds
Started Jan 21 10:18:10 PM PST 24
Finished Jan 21 11:54:06 PM PST 24
Peak memory 254484 kb
Host smart-6b6c45be-2df8-40be-9cb3-93d0cadcd20f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318009358 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.1318009358
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.3666702443
Short name T916
Test name
Test status
Simulation time 579411420 ps
CPU time 4.5 seconds
Started Jan 21 10:18:10 PM PST 24
Finished Jan 21 10:18:24 PM PST 24
Peak memory 241320 kb
Host smart-5097a66f-be32-4346-ba14-6e3348d65365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666702443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3666702443
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.2781468173
Short name T718
Test name
Test status
Simulation time 375775894 ps
CPU time 3.22 seconds
Started Jan 21 10:18:04 PM PST 24
Finished Jan 21 10:18:17 PM PST 24
Peak memory 238776 kb
Host smart-00ab1d8a-f07f-4352-9419-e1e1f1f5861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781468173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2781468173
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.4221553908
Short name T1224
Test name
Test status
Simulation time 555728216546 ps
CPU time 7053.07 seconds
Started Jan 21 10:18:10 PM PST 24
Finished Jan 22 12:15:53 AM PST 24
Peak memory 285940 kb
Host smart-8f1063a8-6e23-46a5-90e2-e12a58549514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221553908 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.4221553908
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.1842690381
Short name T1097
Test name
Test status
Simulation time 148660342 ps
CPU time 3.85 seconds
Started Jan 21 10:18:23 PM PST 24
Finished Jan 21 10:18:34 PM PST 24
Peak memory 238728 kb
Host smart-3fc4c789-324a-423a-8882-17aa7892d1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842690381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.1842690381
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1534789433
Short name T203
Test name
Test status
Simulation time 2442402562411 ps
CPU time 9013.81 seconds
Started Jan 21 10:18:14 PM PST 24
Finished Jan 22 12:48:38 AM PST 24
Peak memory 817376 kb
Host smart-9bb8243a-9ab7-49e2-a4b8-0c10e5d982db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534789433 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1534789433
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.3055156624
Short name T164
Test name
Test status
Simulation time 226880859 ps
CPU time 4.39 seconds
Started Jan 21 10:18:23 PM PST 24
Finished Jan 21 10:18:34 PM PST 24
Peak memory 238664 kb
Host smart-cf642e16-efdc-4916-8e7f-f870d7eb451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055156624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3055156624
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.54432460
Short name T560
Test name
Test status
Simulation time 313446462 ps
CPU time 7.64 seconds
Started Jan 21 10:18:19 PM PST 24
Finished Jan 21 10:18:35 PM PST 24
Peak memory 238892 kb
Host smart-53284016-30c9-4a3d-89f8-37d1c60aef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54432460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.54432460
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.3596940999
Short name T913
Test name
Test status
Simulation time 3473981073982 ps
CPU time 4717.7 seconds
Started Jan 21 10:18:13 PM PST 24
Finished Jan 21 11:37:01 PM PST 24
Peak memory 279308 kb
Host smart-e1a83efc-3a78-4d6b-82c5-9a42e6e255ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596940999 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.3596940999
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3220444305
Short name T707
Test name
Test status
Simulation time 234118830 ps
CPU time 4.62 seconds
Started Jan 21 10:18:23 PM PST 24
Finished Jan 21 10:18:34 PM PST 24
Peak memory 238676 kb
Host smart-485b5fd4-6c6f-4629-9f07-56096316b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220444305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3220444305
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.959882315
Short name T317
Test name
Test status
Simulation time 165863190 ps
CPU time 4.35 seconds
Started Jan 21 10:18:16 PM PST 24
Finished Jan 21 10:18:29 PM PST 24
Peak memory 238956 kb
Host smart-c991e63c-705c-4a12-8aeb-75fa4af052f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959882315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.959882315
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.793493892
Short name T667
Test name
Test status
Simulation time 1454644836675 ps
CPU time 6070.75 seconds
Started Jan 21 10:18:13 PM PST 24
Finished Jan 21 11:59:34 PM PST 24
Peak memory 488924 kb
Host smart-c8b9f638-4f77-469d-a85e-ba2509a7a7aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793493892 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.793493892
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.1606601685
Short name T1144
Test name
Test status
Simulation time 159037159 ps
CPU time 3.81 seconds
Started Jan 21 10:18:18 PM PST 24
Finished Jan 21 10:18:30 PM PST 24
Peak memory 238740 kb
Host smart-36d34a7e-7ec2-4c80-a732-790fb3efb102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606601685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1606601685
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.1690017418
Short name T1019
Test name
Test status
Simulation time 387461406 ps
CPU time 4.13 seconds
Started Jan 21 10:18:12 PM PST 24
Finished Jan 21 10:18:26 PM PST 24
Peak memory 238804 kb
Host smart-da7fbd9b-a4f2-4a58-8304-851bfe47b245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690017418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1690017418
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.1969859820
Short name T778
Test name
Test status
Simulation time 1838744375019 ps
CPU time 5695.61 seconds
Started Jan 21 10:18:19 PM PST 24
Finished Jan 21 11:53:23 PM PST 24
Peak memory 921448 kb
Host smart-32c500c9-5b66-4471-912d-bfdfc7b133c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969859820 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.1969859820
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2511427106
Short name T986
Test name
Test status
Simulation time 437718154 ps
CPU time 4.54 seconds
Started Jan 21 10:18:12 PM PST 24
Finished Jan 21 10:18:26 PM PST 24
Peak memory 238804 kb
Host smart-c1d6c37c-e6fd-44a3-a468-dad34d1d7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511427106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2511427106
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.4043471689
Short name T900
Test name
Test status
Simulation time 395118018 ps
CPU time 7.66 seconds
Started Jan 21 10:18:15 PM PST 24
Finished Jan 21 10:18:32 PM PST 24
Peak memory 238808 kb
Host smart-11e259fd-b0f9-4f51-9d0e-4d4a02d046ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043471689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.4043471689
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.3929674057
Short name T1096
Test name
Test status
Simulation time 567474595734 ps
CPU time 4681.59 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 11:36:30 PM PST 24
Peak memory 1120616 kb
Host smart-2cae5ce3-4d49-4b33-93fa-ebc31e4ac7af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929674057 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.3929674057
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.1011805262
Short name T891
Test name
Test status
Simulation time 450929124 ps
CPU time 4.86 seconds
Started Jan 21 10:18:23 PM PST 24
Finished Jan 21 10:18:35 PM PST 24
Peak memory 241148 kb
Host smart-e9497eba-57ee-4387-9be7-7758cd727559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011805262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1011805262
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.262980120
Short name T488
Test name
Test status
Simulation time 1298610024 ps
CPU time 6.07 seconds
Started Jan 21 10:18:23 PM PST 24
Finished Jan 21 10:18:36 PM PST 24
Peak memory 242080 kb
Host smart-73866534-78c2-4807-b884-92bf7c1bcd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262980120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.262980120
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.1933403623
Short name T1108
Test name
Test status
Simulation time 550240099 ps
CPU time 3.74 seconds
Started Jan 21 10:18:20 PM PST 24
Finished Jan 21 10:18:32 PM PST 24
Peak memory 240620 kb
Host smart-467ecaf6-a654-4d58-bfd8-c6bcd524ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933403623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1933403623
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.97589992
Short name T741
Test name
Test status
Simulation time 363858309 ps
CPU time 5.54 seconds
Started Jan 21 10:18:17 PM PST 24
Finished Jan 21 10:18:31 PM PST 24
Peak memory 238848 kb
Host smart-52caacfa-99aa-46d4-80b8-b4020e0c0c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97589992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.97589992
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.4139105023
Short name T15
Test name
Test status
Simulation time 3541889909367 ps
CPU time 6344.69 seconds
Started Jan 21 10:18:15 PM PST 24
Finished Jan 22 12:04:09 AM PST 24
Peak memory 288136 kb
Host smart-92c328d1-13d7-445c-9346-4c7bc0aedb39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139105023 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.4139105023
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%