Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	574938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

386926

1

T1

550

T2

207

T3

147

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	624828	1			T1	990		T2	438		T3	299
values[0x0]	146509	1			T1	89		T2	125		T3	74
values[0x1]	190527	1			T1	77		T2	118		T3	95

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	418684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

543180

1

T1

671

T2

307

T3

215

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2664	1			T1	3		T3	3		T17	2
valid_sources[0x01]	4948	1			T1	7		T3	3		T18	4
valid_sources[0x02]	4033	1			T1	3		T17	6		T19	6
valid_sources[0x03]	3265	1			T1	9		T3	6		T18	3
valid_sources[0x04]	3421	1			T1	2		T3	4		T17	3
valid_sources[0x05]	3340	1			T1	1		T3	1		T17	5
valid_sources[0x06]	3374	1			T1	8		T2	37		T3	1
valid_sources[0x07]	3563	1			T1	2		T2	31		T3	3
valid_sources[0x08]	3247	1			T1	3		T17	1		T18	1
valid_sources[0x09]	6418	1			T3	6		T17	4		T18	2
valid_sources[0x0a]	4274	1			T1	4		T3	2		T17	3
valid_sources[0x0b]	4548	1			T1	10		T3	4		T17	2
valid_sources[0x0c]	3227	1			T1	9		T3	1		T17	4
valid_sources[0x0d]	3143	1			T1	2		T3	2		T17	10
valid_sources[0x0e]	3013	1			T1	9		T3	2		T17	4
valid_sources[0x0f]	3104	1			T1	10		T3	4		T17	2
valid_sources[0x10]	4657	1			T1	1		T3	1		T17	4
valid_sources[0x11]	2841	1			T3	1		T17	3		T18	1
valid_sources[0x12]	8208	1			T1	10		T3	2		T17	4
valid_sources[0x13]	3915	1			T3	2		T17	4		T18	1
valid_sources[0x14]	4055	1			T1	8		T3	3		T17	4
valid_sources[0x15]	2902	1			T3	3		T17	3		T18	2
valid_sources[0x16]	3274	1			T1	1		T3	2		T17	1
valid_sources[0x17]	4924	1			T1	4		T2	17		T3	4
valid_sources[0x18]	3494	1			T1	3		T3	3		T17	1
valid_sources[0x19]	3051	1			T1	13		T3	3		T17	3
valid_sources[0x1a]	3388	1			T1	1		T3	2		T17	1
valid_sources[0x1b]	2721	1			T1	12		T3	2		T17	2
valid_sources[0x1c]	2557	1			T1	3		T3	2		T18	1
valid_sources[0x1d]	3369	1			T1	18		T3	1		T17	4
valid_sources[0x1e]	2834	1			T1	3		T3	4		T17	1
valid_sources[0x1f]	3307	1			T3	3		T17	5		T18	4
valid_sources[0x20]	2788	1			T1	6		T17	7		T18	3
valid_sources[0x21]	2923	1			T1	6		T3	2		T17	1
valid_sources[0x22]	3529	1			T1	1		T2	24		T3	3
valid_sources[0x23]	2833	1			T1	7		T3	3		T17	2
valid_sources[0x24]	2521	1			T1	6		T2	40		T3	2
valid_sources[0x25]	2989	1			T1	5		T3	2		T17	4
valid_sources[0x26]	2924	1			T1	2		T18	1		T5	8
valid_sources[0x27]	4974	1			T1	2		T3	1		T9	2372
valid_sources[0x28]	3557	1			T1	9		T3	3		T17	4
valid_sources[0x29]	8528	1			T1	1		T3	2		T18	2
valid_sources[0x2a]	3390	1			T1	11		T3	1		T17	2
valid_sources[0x2b]	5359	1			T1	2		T3	3		T17	5
valid_sources[0x2c]	3086	1			T1	7		T3	3		T17	2
valid_sources[0x2d]	2981	1			T1	4		T3	1		T17	1
valid_sources[0x2e]	4250	1			T1	3		T3	4		T17	4
valid_sources[0x2f]	2866	1			T1	1		T3	1		T17	2
valid_sources[0x30]	3710	1			T1	2		T3	3		T17	3
valid_sources[0x31]	3097	1			T3	2		T17	7		T18	2
valid_sources[0x32]	4153	1			T1	3		T3	2		T17	6
valid_sources[0x33]	3426	1			T1	10		T3	2		T17	1
valid_sources[0x34]	13664	1			T1	6		T3	3		T17	5
valid_sources[0x35]	4715	1			T1	2		T3	3		T17	2
valid_sources[0x36]	3210	1			T1	4		T3	1		T17	2
valid_sources[0x37]	5203	1			T1	4		T17	2		T18	3
valid_sources[0x38]	3162	1			T1	7		T3	1		T17	6
valid_sources[0x39]	2788	1			T3	3		T17	5		T18	2
valid_sources[0x3a]	2692	1			T1	8		T3	2		T17	4
valid_sources[0x3b]	2857	1			T1	1		T3	1		T17	8
valid_sources[0x3c]	3288	1			T1	2		T3	4		T18	1
valid_sources[0x3d]	3509	1			T1	2		T17	2		T19	2
valid_sources[0x3e]	5797	1			T2	2		T3	1		T17	2
valid_sources[0x3f]	3019	1			T3	1		T17	10		T18	2
valid_sources[0x40]	3662	1			T1	7		T3	3		T17	6
valid_sources[0x41]	3099	1			T1	1		T3	2		T17	2
valid_sources[0x42]	4323	1			T3	2		T17	3		T18	2
valid_sources[0x43]	4941	1			T1	1		T3	2		T17	5
valid_sources[0x44]	3493	1			T1	9		T2	29		T3	1
valid_sources[0x45]	5543	1			T1	6		T3	1		T17	2
valid_sources[0x46]	3150	1			T1	6		T2	1		T17	9
valid_sources[0x47]	3778	1			T1	2		T3	2		T17	6
valid_sources[0x48]	3669	1			T1	12		T3	1		T17	2
valid_sources[0x49]	2783	1			T1	4		T3	3		T17	3
valid_sources[0x4a]	3124	1			T3	1		T17	3		T18	5
valid_sources[0x4b]	2984	1			T1	8		T3	1		T18	2
valid_sources[0x4c]	3496	1			T3	6		T17	7		T18	2
valid_sources[0x4d]	4726	1			T1	7		T3	2		T17	5
valid_sources[0x4e]	3311	1			T1	9		T3	1		T17	5
valid_sources[0x4f]	3531	1			T1	5		T3	2		T17	4
valid_sources[0x50]	3474	1			T1	11		T3	4		T17	5
valid_sources[0x51]	3747	1			T1	8		T3	2		T17	4
valid_sources[0x52]	2953	1			T1	9		T3	2		T17	1
valid_sources[0x53]	3220	1			T1	1		T3	1		T17	2
valid_sources[0x54]	2913	1			T1	2		T3	3		T17	3
valid_sources[0x55]	4791	1			T2	57		T17	2		T18	3
valid_sources[0x56]	4207	1			T1	4		T17	2		T18	3
valid_sources[0x57]	4041	1			T3	1		T17	2		T18	3
valid_sources[0x58]	3345	1			T1	9		T3	3		T17	3
valid_sources[0x59]	2836	1			T1	2		T3	2		T17	4
valid_sources[0x5a]	2662	1			T1	7		T3	2		T18	2
valid_sources[0x5b]	3137	1			T1	10		T3	1		T17	1
valid_sources[0x5c]	3540	1			T1	1		T2	8		T3	3
valid_sources[0x5d]	2982	1			T1	1		T3	2		T17	11
valid_sources[0x5e]	4108	1			T1	7		T3	2		T17	4
valid_sources[0x5f]	2641	1			T3	3		T17	1		T18	3
valid_sources[0x60]	2880	1			T1	5		T17	2		T18	2
valid_sources[0x61]	3363	1			T1	2		T3	3		T17	2
valid_sources[0x62]	5230	1			T1	9		T3	3		T17	1
valid_sources[0x63]	5524	1			T1	1		T3	6		T17	3
valid_sources[0x64]	10462	1			T1	8		T3	3		T17	2
valid_sources[0x65]	3009	1			T1	6		T3	1		T17	5
valid_sources[0x66]	2996	1			T3	3		T17	2		T18	1
valid_sources[0x67]	2587	1			T1	1		T2	40		T3	3
valid_sources[0x68]	5135	1			T1	2		T17	4		T18	3
valid_sources[0x69]	2630	1			T1	2		T17	6		T18	6
valid_sources[0x6a]	2784	1			T1	5		T3	4		T17	2
valid_sources[0x6b]	4553	1			T1	4		T3	1		T17	1
valid_sources[0x6c]	7044	1			T1	2		T2	27		T3	2
valid_sources[0x6d]	3114	1			T1	3		T18	2		T19	3
valid_sources[0x6e]	5120	1			T1	13		T3	2		T17	2
valid_sources[0x6f]	3892	1			T1	11		T3	1		T17	1
valid_sources[0x70]	4492	1			T1	4		T3	1		T18	2
valid_sources[0x71]	3173	1			T1	7		T3	2		T18	3
valid_sources[0x72]	6576	1			T1	1		T3	1		T17	6
valid_sources[0x73]	5825	1			T1	6		T3	3		T17	2
valid_sources[0x74]	4074	1			T1	2		T3	2		T17	1
valid_sources[0x75]	2891	1			T1	12		T2	11		T3	2
valid_sources[0x76]	3763	1			T1	9		T2	65		T3	4
valid_sources[0x77]	6785	1			T1	8		T3	3		T17	4
valid_sources[0x78]	2722	1			T1	8		T3	1		T17	11
valid_sources[0x79]	4442	1			T1	6		T17	8		T18	3
valid_sources[0x7a]	2821	1			T1	14		T3	3		T17	3
valid_sources[0x7b]	4412	1			T1	16		T3	2		T17	3
valid_sources[0x7c]	3160	1			T1	1		T3	1		T17	1
valid_sources[0x7d]	2671	1			T1	2		T3	1		T17	3
valid_sources[0x7e]	3261	1			T1	2		T3	3		T17	4
valid_sources[0x7f]	2866	1			T1	8		T2	11		T17	1
valid_sources[0x80]	2869	1			T1	4		T3	5		T17	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

195802

1

T1

481

T2

88

T3

72

values[0x0]

all_enables

biggest_size

101151

1

T1

43

T2

69

T3

41

values[0x1]

all_enables

biggest_size

89973

1

T1

26

T2

50

T3

34

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18754	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

304306

1

T1

80

T9

200

T4

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	91613	1			T1	40		T9	100		T4	20
values[0x0]	112641	1			T1	18		T9	41		T4	11
values[0x1]	118806	1			T1	22		T9	59		T4	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

312681

1

T1

80

T9

200

T4

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1211	1			T193	2		T10	1066		T259	1
valid_sources[0x01]	1235	1			T1	2		T193	1		T311	1
valid_sources[0x02]	1477	1			T1	4		T5	1		T146	1
valid_sources[0x03]	1216	1			T69	1		T10	1061		T258	1
valid_sources[0x04]	1337	1			T146	1		T65	3		T71	1
valid_sources[0x05]	1220	1			T8	1		T13	2		T10	1040
valid_sources[0x06]	1172	1			T5	1		T64	1		T10	1026
valid_sources[0x07]	1268	1			T204	5		T10	1078		T72	7
valid_sources[0x08]	1307	1			T8	4		T10	1076		T330	4
valid_sources[0x09]	1336	1			T193	1		T70	1		T10	1094
valid_sources[0x0a]	1290	1			T5	1		T146	2		T193	5
valid_sources[0x0b]	1170	1			T64	1		T10	1053		T258	2
valid_sources[0x0c]	1316	1			T193	1		T311	1		T10	1164
valid_sources[0x0d]	1203	1			T204	1		T64	2		T311	1
valid_sources[0x0e]	1262	1			T204	3		T64	1		T193	1
valid_sources[0x0f]	1190	1			T1	1		T7	20		T64	1
valid_sources[0x10]	1230	1			T5	1		T10	1089		T195	1
valid_sources[0x11]	1143	1			T146	2		T71	1		T10	1003
valid_sources[0x12]	1256	1			T8	3		T146	1		T64	1
valid_sources[0x13]	1201	1			T49	1		T10	1077		T258	2
valid_sources[0x14]	1222	1			T8	1		T204	1		T146	1
valid_sources[0x15]	1218	1			T8	1		T21	51		T64	1
valid_sources[0x16]	1243	1			T146	1		T64	1		T193	3
valid_sources[0x17]	1212	1			T13	2		T193	3		T67	1
valid_sources[0x18]	1318	1			T21	72		T146	2		T64	1
valid_sources[0x19]	1216	1			T146	3		T71	3		T10	1022
valid_sources[0x1a]	1177	1			T146	1		T48	1		T10	1035
valid_sources[0x1b]	1233	1			T64	3		T193	5		T10	1062
valid_sources[0x1c]	1249	1			T1	1		T146	1		T64	1
valid_sources[0x1d]	1202	1			T146	1		T311	1		T49	1
valid_sources[0x1e]	1299	1			T146	1		T64	1		T10	1135
valid_sources[0x1f]	1146	1			T1	1		T204	1		T146	1
valid_sources[0x20]	1243	1			T64	1		T193	1		T10	1062
valid_sources[0x21]	1306	1			T204	15		T146	1		T10	1095
valid_sources[0x22]	1262	1			T5	3		T8	4		T64	1
valid_sources[0x23]	1242	1			T204	6		T193	8		T69	1
valid_sources[0x24]	1304	1			T146	1		T64	2		T193	1
valid_sources[0x25]	1261	1			T5	2		T204	4		T146	1
valid_sources[0x26]	1243	1			T204	2		T146	2		T193	2
valid_sources[0x27]	1187	1			T146	1		T64	2		T193	1
valid_sources[0x28]	1143	1			T204	1		T10	1038		T258	1
valid_sources[0x29]	1222	1			T71	1		T10	1023		T101	4
valid_sources[0x2a]	1219	1			T1	5		T146	2		T64	1
valid_sources[0x2b]	1235	1			T146	1		T64	1		T10	1070
valid_sources[0x2c]	1182	1			T204	4		T193	4		T151	13
valid_sources[0x2d]	1508	1			T8	2		T146	1		T22	40
valid_sources[0x2e]	1216	1			T193	1		T151	2		T10	1072
valid_sources[0x2f]	1382	1			T64	2		T151	3		T311	1
valid_sources[0x30]	1215	1			T64	1		T193	1		T311	1
valid_sources[0x31]	1420	1			T204	1		T64	1		T10	1120
valid_sources[0x32]	1274	1			T65	6		T193	2		T311	2
valid_sources[0x33]	1272	1			T193	1		T311	1		T10	1074
valid_sources[0x34]	1304	1			T5	2		T204	1		T146	1
valid_sources[0x35]	1285	1			T146	1		T10	1178		T259	1
valid_sources[0x36]	1285	1			T146	1		T64	1		T65	4
valid_sources[0x37]	1209	1			T204	4		T10	1031		T258	4
valid_sources[0x38]	1383	1			T146	2		T48	9		T49	2
valid_sources[0x39]	1497	1			T193	2		T70	1		T10	1069
valid_sources[0x3a]	1164	1			T146	2		T194	7		T10	985
valid_sources[0x3b]	1168	1			T311	1		T10	1023		T258	2
valid_sources[0x3c]	1255	1			T146	1		T64	2		T193	2
valid_sources[0x3d]	1192	1			T64	2		T311	1		T10	1066
valid_sources[0x3e]	1344	1			T29	40		T204	1		T146	2
valid_sources[0x3f]	1266	1			T193	1		T49	1		T10	1107
valid_sources[0x40]	1368	1			T8	3		T146	6		T48	3
valid_sources[0x41]	1283	1			T204	1		T64	2		T10	1079
valid_sources[0x42]	1224	1			T193	5		T151	5		T71	1
valid_sources[0x43]	1278	1			T1	1		T193	1		T194	5
valid_sources[0x44]	1344	1			T146	1		T193	5		T155	100
valid_sources[0x45]	1233	1			T193	3		T311	2		T10	1054
valid_sources[0x46]	1208	1			T5	1		T204	3		T146	1
valid_sources[0x47]	1214	1			T146	1		T64	1		T193	1
valid_sources[0x48]	1301	1			T4	40		T146	1		T71	1
valid_sources[0x49]	1219	1			T146	2		T151	1		T311	2
valid_sources[0x4a]	1232	1			T1	8		T5	1		T146	1
valid_sources[0x4b]	1121	1			T64	1		T10	987		T258	1
valid_sources[0x4c]	1228	1			T64	1		T151	1		T10	1073
valid_sources[0x4d]	1389	1			T1	2		T8	1		T64	2
valid_sources[0x4e]	1254	1			T13	2		T193	2		T10	1062
valid_sources[0x4f]	1267	1			T5	1		T146	1		T64	1
valid_sources[0x50]	1198	1			T146	1		T311	3		T10	1052
valid_sources[0x51]	1227	1			T146	3		T63	5		T311	1
valid_sources[0x52]	1240	1			T146	2		T10	1072		T258	1
valid_sources[0x53]	1313	1			T146	1		T10	1101		T258	1
valid_sources[0x54]	1543	1			T64	2		T67	1		T231	20
valid_sources[0x55]	1208	1			T146	2		T10	1063		T259	6
valid_sources[0x56]	1280	1			T64	1		T193	2		T311	1
valid_sources[0x57]	1288	1			T146	2		T10	1079		T258	2
valid_sources[0x58]	1356	1			T64	1		T193	1		T10	1087
valid_sources[0x59]	1297	1			T193	6		T311	1		T10	1070
valid_sources[0x5a]	1278	1			T48	5		T193	1		T151	31
valid_sources[0x5b]	1272	1			T204	14		T146	2		T311	1
valid_sources[0x5c]	1261	1			T204	4		T151	1		T10	1097
valid_sources[0x5d]	1342	1			T5	2		T146	1		T10	1092
valid_sources[0x5e]	1210	1			T64	1		T10	1055		T195	1
valid_sources[0x5f]	1179	1			T1	5		T71	1		T10	1048
valid_sources[0x60]	1195	1			T146	1		T151	5		T10	1064
valid_sources[0x61]	1294	1			T146	1		T64	1		T193	2
valid_sources[0x62]	1387	1			T146	1		T64	1		T203	1
valid_sources[0x63]	1246	1			T5	2		T146	1		T64	2
valid_sources[0x64]	1309	1			T146	1		T67	1		T10	1113
valid_sources[0x65]	1242	1			T64	1		T71	1		T10	1106
valid_sources[0x66]	1274	1			T8	6		T64	1		T67	2
valid_sources[0x67]	1246	1			T146	1		T10	1091		T207	1
valid_sources[0x68]	1215	1			T146	2		T311	1		T10	1067
valid_sources[0x69]	1207	1			T8	1		T146	3		T10	1043
valid_sources[0x6a]	1251	1			T146	1		T64	1		T311	1
valid_sources[0x6b]	1265	1			T146	2		T10	1127		T195	2
valid_sources[0x6c]	1325	1			T8	10		T204	2		T193	2
valid_sources[0x6d]	1312	1			T65	1		T311	1		T10	1084
valid_sources[0x6e]	1480	1			T146	1		T10	1127		T89	3
valid_sources[0x6f]	1231	1			T65	1		T10	1056		T72	3
valid_sources[0x70]	1156	1			T146	1		T10	1036		T330	1
valid_sources[0x71]	1302	1			T146	3		T64	1		T203	3
valid_sources[0x72]	1346	1			T5	1		T204	7		T146	2
valid_sources[0x73]	1242	1			T146	1		T13	2		T151	2
valid_sources[0x74]	1297	1			T64	1		T67	3		T10	1096
valid_sources[0x75]	1338	1			T1	4		T146	2		T311	1
valid_sources[0x76]	1258	1			T204	2		T64	1		T193	1
valid_sources[0x77]	1265	1			T204	3		T193	1		T10	1152
valid_sources[0x78]	1191	1			T21	17		T64	1		T13	2
valid_sources[0x79]	1186	1			T65	2		T151	17		T10	1011
valid_sources[0x7a]	1349	1			T10	1144		T258	4		T195	1
valid_sources[0x7b]	1204	1			T5	1		T311	2		T10	1058
valid_sources[0x7c]	1251	1			T193	4		T10	1138		T195	3
valid_sources[0x7d]	1255	1			T146	1		T193	2		T311	1
valid_sources[0x7e]	1255	1			T5	1		T204	2		T146	1
valid_sources[0x7f]	1303	1			T5	1		T204	2		T146	2
valid_sources[0x80]	1459	1			T204	5		T64	2		T192	180

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81840

1

T1

40

T9

100

T4

20

values[0x0]

all_enables

biggest_size

111494

1

T1

18

T9

41

T4

11

values[0x1]

all_enables

biggest_size

110972

1

T1

22

T9

59

T4

9