Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1142742

1

T1

606

T2

474

T3

321

full_word

422726

1

T1

550

T2

207

T3

147

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1565208	1			T1	1156		T2	681		T3	468
auto[TlIntgErrCmd]	89	1			T91	5		T93	4		T95	6
auto[TlIntgErrData]	86	1			T91	5		T93	10		T95	3
auto[TlIntgErrBoth]	85	1			T91	10		T93	6		T95	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668296

1

T1

990

T2

438

T3

299

auto[1]

897172

1

T1

166

T2

243

T3

169

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	467925	1			T1	509		T2	350		T3	227
auto[TlIntgErrNone]	partial	auto[1]	674582	1			T1	97		T2	124		T3	94
auto[TlIntgErrNone]	full_word	auto[0]	200253	1			T1	481		T2	88		T3	72
auto[TlIntgErrNone]	full_word	auto[1]	222448	1			T1	69		T2	119		T3	75
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T91	2		T93	4		T95	3
auto[TlIntgErrCmd]	partial	auto[1]	36	1			T91	3		T95	2		T96	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T109	1		T315	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T95	1		T96	1		T141	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T91	1		T93	6		T95	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T91	4		T93	3		T95	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T93	1		T109	1		T141	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T96	1		T109	1		T316	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1			T91	5		T93	1		T96	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T91	5		T93	4		T95	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T93	1		T96	1		T127	1