Unified Coverage Report :: Module :: otp_ctrl_kdi

Module : otp_ctrl_kdi

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.28	98.65	94.44		79.17	89.13	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_kdi	93.72	98.65	94.44		86.36	89.13	100.00

---

Module Instance : tb.dut.u_otp_ctrl_kdi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.72	98.65	94.44		86.36	89.13	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.35	99.26	94.43	100.00	86.36	94.68	97.37

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.86	95.10	88.12	78.08		96.00	97.01	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_flash_addr_key_anchor	100.00	100.00
u_flash_data_key_anchor	100.00	100.00
u_key_out_anchor	100.00	100.00				100.00
u_prim_count_entropy	100.00			100.00
u_prim_count_seed	100.00			100.00
u_req_arb	97.04	100.00	94.42			100.00	93.75
u_sram_data_key_anchor	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_kdi

	Line No.	Total	Covered	Percent
TOTAL		148	146	98.65
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
ALWAYS	257	9	9	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
ALWAYS	355	88	86	97.73
ALWAYS	571	3	3	100.00
ALWAYS	574	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
114	1	1
115	1	1
117	1	1
118	1	1
119	1	1
148	1	1
156	1	1
164	1	1
175	4	4
176	4	4
177	4	4
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
263	1	1
264	1	1
			MISSING_ELSE
266	1	1
267	1	1
			MISSING_ELSE
282	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	4	4
292	4	4
293	4	4
303	1	1
352	1	1
355	1	1
358	1	1
361	1	1
362	1	1
363	1	1
364	1	1
371	1	1
374	1	1
375	1	1
376	1	1
377	1	1
380	1	1
381	1	1
382	1	1
383	1	1
385	1	1
388	1	1
390	1	1
394	1	1
395	1	1
			MISSING_ELSE
401	1	1
402	1	1
403	1	1
404	1	1
			MISSING_ELSE
410	1	1
411	1	1
413	1	1
414	1	1
415	1	1
			MISSING_ELSE
421	1	1
422	1	1
424	1	1
425	1	1
426	1	1
428	1	1
429	1	1
432	1	1
			==> MISSING_ELSE
436	1	1
437	1	1
			==> MISSING_ELSE
443	1	1
444	1	1
445	1	1
446	1	1
448	1	1
449	1	1
450	1	1
453	1	1
			MISSING_ELSE
460	1	1
461	1	1
462	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
			==> MISSING_ELSE
472	1	1
473	1	1
			MISSING_ELSE
479	1	1
480	1	1
481	1	1
482	1	1
483	1	1
			MISSING_ELSE
491	1	1
492	1	1
493	1	1
495	1	1
496	1	1
499	1	1
500	0	1
503	1	1
507	1	1
509	1	1
511	1	1
512	1	1
515	0	1
			MISSING_ELSE
524	1	1
525	1	1
526	1	1
528	1	1
529	1	1
530	1	1
533	1	1
			MISSING_ELSE
540	1	1
541	1	1
546	1	1
560	1	1
562	1	1
563	1	1
			MISSING_ELSE
571	3	3
574	1	1
575	1	1
576	1	1
577	1	1
579	1	1
580	1	1
581	1	1

---

Cond Coverage for Module : otp_ctrl_kdi

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       303
 EXPRESSION ((data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0))
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       303
 SUB-EXPRESSION (data_sel == EntropyData)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       303
 SUB-EXPRESSION (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0)
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T29,T63

 LINE       371
 EXPRESSION (edn_req_q & ((~edn_ack_i)))
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       414
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T9,T4

 LINE       448
 EXPRESSION (entropy_cnt == 2'b1)
            ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       495
 EXPRESSION (seed_cnt == 2'b1)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       528
 EXPRESSION (entropy_cnt == req_bundle.nonce_size)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Module : otp_ctrl_kdi

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	24	19	79.17
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DigClrSt	402	Covered	T1,T9,T4
DigEntropySt	449	Covered	T4,T5,T6
DigFinSt	432	Covered	T4,T5,T6
DigLoadSt	415	Covered	T1,T9,T4
DigWaitSt	483	Covered	T4,T5,T6
ErrorSt	562	Covered	T1,T9,T8
FetchEntropySt	429	Covered	T4,T5,T6
FetchNonceSt	512	Covered	T4,T5,T6
FinishSt	515	Covered	T4,T5,T6
IdleSt	395	Covered	T1,T2,T3
ResetSt	393	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DigClrSt->DigLoadSt	415	Covered	T1,T9,T4
DigClrSt->ErrorSt	562	Covered	T250,T148
DigEntropySt->DigFinSt	468	Covered	T4,T5,T6
DigEntropySt->ErrorSt	562	Not Covered
DigFinSt->DigWaitSt	483	Covered	T4,T5,T6
DigFinSt->ErrorSt	562	Covered	T251,T252
DigLoadSt->DigFinSt	432	Covered	T4,T5,T6
DigLoadSt->ErrorSt	562	Covered	T1,T9,T204
DigLoadSt->FetchEntropySt	429	Covered	T4,T5,T6
DigWaitSt->DigClrSt	503	Covered	T4,T5,T6
DigWaitSt->DigLoadSt	500	Not Covered
DigWaitSt->ErrorSt	562	Covered	T147,T253
DigWaitSt->FetchNonceSt	512	Covered	T4,T5,T6
DigWaitSt->FinishSt	515	Not Covered
FetchEntropySt->DigEntropySt	449	Covered	T4,T5,T6
FetchEntropySt->ErrorSt	562	Covered	T21,T64,T192
FetchNonceSt->ErrorSt	562	Not Covered
FetchNonceSt->FinishSt	529	Covered	T4,T5,T6
FinishSt->ErrorSt	562	Not Covered
FinishSt->IdleSt	540	Covered	T4,T5,T6
IdleSt->DigClrSt	402	Covered	T1,T9,T4
IdleSt->ErrorSt	562	Covered	T8,T146,T203
ResetSt->ErrorSt	562	Covered	T48
ResetSt->IdleSt	395	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_kdi

	Line No.	Total	Covered	Percent
Branches		46	41	89.13
TERNARY	303	3	3	100.00
IF	260	2	2	100.00
IF	263	2	2	100.00
IF	266	2	2	100.00
CASE	390	31	26	83.87
IF	560	2	2	100.00
IF	571	2	2	100.00
IF	574	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	303	((data_sel == EntropyData)) ? 
-2-:	303	(req_bundle.seed_valid) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T5,T29,T63
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	if (key_reg_en)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	if (nonce_reg_en)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if (seed_valid_reg_en)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	390	case (state_q)
-2-:	394	if (kdi_en_i)
-3-:	401	if (req_valid)
-4-:	414	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-5-:	424	if (seed_cnt[0])
-6-:	426	if (scrmbl_ready_i)
-7-:	428	if (req_bundle.ingest_entropy)
-8-:	436	if (scrmbl_ready_i)
-9-:	445	if (edn_ack_i)
-10-:	448	if ((entropy_cnt == 2'b1))
-11-:	465	if (entropy_cnt[0])
-12-:	467	if (scrmbl_ready_i)
-13-:	472	if (scrmbl_ready_i)
-14-:	482	if (scrmbl_ready_i)
-15-:	492	if (scrmbl_valid_i)
-16-:	495	if ((seed_cnt == 2'b1))
-17-:	499	if (req_bundle.chained_digest)
-18-:	511	if (req_bundle.fetch_nonce)
-19-:	525	if (edn_ack_i)
-20-:	528	if ((entropy_cnt == req_bundle.nonce_size))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T4
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigClrSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T4
DigClrSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T148
DigLoadSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigLoadSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigLoadSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigLoadSt	-	-	-	0	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T4
DigLoadSt	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
FetchEntropySt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
FetchEntropySt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
FetchEntropySt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigEntropySt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigEntropySt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Not Covered
DigEntropySt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigEntropySt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T5,T65,T13
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T5,T6
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T5,T6
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T4,T5,T6
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	Covered	T4,T5,T6
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T5,T6
FetchNonceSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	Covered	T4,T5,T6
FetchNonceSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	Covered	T4,T5,T6
FetchNonceSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T6
FinishSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	560	if (((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || seed_cnt_err) || entropy_cnt_err))

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	571	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	574	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_kdi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	21	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	21	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EdnReqKnown_A	26050016	25806694	0	0
EntropyWidthDividesDigestBlockWidth_A	552	552	0	0
FlashOtpKeyRspKnown_A	26050016	25806694	0	0
FsmErrKnown_A	26050016	25806694	0	0
KeyNonceSize0_A	552	552	0	0
KeyNonceSize1_A	552	552	0	0
KeyNonceSize2_A	552	552	0	0
KeyNonceSize3_A	552	552	0	0
KeyNonceSize4_A	552	552	0	0
KeyNonceSize5_A	552	552	0	0
KeyNonceSize6_A	552	552	0	0
NonceWidth_A	552	552	0	0
OtbnOtpKeyRspKnown_A	26050016	25806694	0	0
ScrmblCmdKnown_A	26050016	25806694	0	0
ScrmblDataKnown_A	26050016	25806694	0	0
ScrmblModeKnown_A	26050016	25806694	0	0
ScrmblMtxReqKnown_A	26050016	25806694	0	0
ScrmblSelKnown_A	26050016	25806694	0	0
ScrmblValidKnown_A	26050016	25806694	0	0
SramOtpKeyRspKnown_A	26050016	25806694	0	0
u_state_regs_A	26050016	25806694	0	0

EdnReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

EntropyWidthDividesDigestBlockWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

FsmErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

KeyNonceSize0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize5_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize6_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

NonceWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtbnOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

SramOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_kdi

	Line No.	Total	Covered	Percent
TOTAL		148	146	98.65
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
ALWAYS	257	9	9	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
ALWAYS	355	88	86	97.73
ALWAYS	571	3	3	100.00
ALWAYS	574	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
114	1	1
115	1	1
117	1	1
118	1	1
119	1	1
148	1	1
156	1	1
164	1	1
175	4	4
176	4	4
177	4	4
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
263	1	1
264	1	1
			MISSING_ELSE
266	1	1
267	1	1
			MISSING_ELSE
282	1	1
283	1	1
284	1	1
286	1	1
287	1	1
288	1	1
291	4	4
292	4	4
293	4	4
303	1	1
352	1	1
355	1	1
358	1	1
361	1	1
362	1	1
363	1	1
364	1	1
371	1	1
374	1	1
375	1	1
376	1	1
377	1	1
380	1	1
381	1	1
382	1	1
383	1	1
385	1	1
388	1	1
390	1	1
394	1	1
395	1	1
			MISSING_ELSE
401	1	1
402	1	1
403	1	1
404	1	1
			MISSING_ELSE
410	1	1
411	1	1
413	1	1
414	1	1
415	1	1
			MISSING_ELSE
421	1	1
422	1	1
424	1	1
425	1	1
426	1	1
428	1	1
429	1	1
432	1	1
			==> MISSING_ELSE
436	1	1
437	1	1
			==> MISSING_ELSE
443	1	1
444	1	1
445	1	1
446	1	1
448	1	1
449	1	1
450	1	1
453	1	1
			MISSING_ELSE
460	1	1
461	1	1
462	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
			==> MISSING_ELSE
472	1	1
473	1	1
			MISSING_ELSE
479	1	1
480	1	1
481	1	1
482	1	1
483	1	1
			MISSING_ELSE
491	1	1
492	1	1
493	1	1
495	1	1
496	1	1
499	1	1
500	0	1
503	1	1
507	1	1
509	1	1
511	1	1
512	1	1
515	0	1
			MISSING_ELSE
524	1	1
525	1	1
526	1	1
528	1	1
529	1	1
530	1	1
533	1	1
			MISSING_ELSE
540	1	1
541	1	1
546	1	1
560	1	1
562	1	1
563	1	1
			MISSING_ELSE
571	3	3
574	1	1
575	1	1
576	1	1
577	1	1
579	1	1
580	1	1
581	1	1

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_kdi

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       303
 EXPRESSION ((data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0))
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       303
 SUB-EXPRESSION (data_sel == EntropyData)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       303
 SUB-EXPRESSION (req_bundle.seed_valid ? req_bundle.seed[seed_cnt] : '0)
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T29,T63

 LINE       371
 EXPRESSION (edn_req_q & ((~edn_ack_i)))
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       414
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T9,T4

 LINE       448
 EXPRESSION (entropy_cnt == 2'b1)
            ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       495
 EXPRESSION (seed_cnt == 2'b1)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       528
 EXPRESSION (entropy_cnt == req_bundle.nonce_size)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_kdi

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	22	19	86.36
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DigClrSt	402	Covered	T1,T9,T4
DigEntropySt	449	Covered	T4,T5,T6
DigFinSt	432	Covered	T4,T5,T6
DigLoadSt	415	Covered	T1,T9,T4
DigWaitSt	483	Covered	T4,T5,T6
ErrorSt	562	Covered	T1,T9,T8
FetchEntropySt	429	Covered	T4,T5,T6
FetchNonceSt	512	Covered	T4,T5,T6
FinishSt	515	Covered	T4,T5,T6
IdleSt	395	Covered	T1,T2,T3
ResetSt	393	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DigClrSt->DigLoadSt	415	Covered	T1,T9,T4
DigClrSt->ErrorSt	562	Covered	T250,T148
DigEntropySt->DigFinSt	468	Covered	T4,T5,T6
DigEntropySt->ErrorSt	562	Not Covered
DigFinSt->DigWaitSt	483	Covered	T4,T5,T6
DigFinSt->ErrorSt	562	Covered	T251,T252
DigLoadSt->DigFinSt	432	Covered	T4,T5,T6
DigLoadSt->ErrorSt	562	Covered	T1,T9,T204
DigLoadSt->FetchEntropySt	429	Covered	T4,T5,T6
DigWaitSt->DigClrSt	503	Covered	T4,T5,T6
DigWaitSt->DigLoadSt	500	Excluded
DigWaitSt->ErrorSt	562	Covered	T147,T253
DigWaitSt->FetchNonceSt	512	Covered	T4,T5,T6
DigWaitSt->FinishSt	515	Excluded
FetchEntropySt->DigEntropySt	449	Covered	T4,T5,T6
FetchEntropySt->ErrorSt	562	Covered	T21,T64,T192
FetchNonceSt->ErrorSt	562	Not Covered
FetchNonceSt->FinishSt	529	Covered	T4,T5,T6
FinishSt->ErrorSt	562	Not Covered
FinishSt->IdleSt	540	Covered	T4,T5,T6
IdleSt->DigClrSt	402	Covered	T1,T9,T4
IdleSt->ErrorSt	562	Covered	T8,T146,T203
ResetSt->ErrorSt	562	Covered	T48
ResetSt->IdleSt	395	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_kdi

	Line No.	Total	Covered	Percent
Branches		46	41	89.13
TERNARY	303	3	3	100.00
IF	260	2	2	100.00
IF	263	2	2	100.00
IF	266	2	2	100.00
CASE	390	31	26	83.87
IF	560	2	2	100.00
IF	571	2	2	100.00
IF	574	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_kdi.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	303	((data_sel == EntropyData)) ? 
-2-:	303	(req_bundle.seed_valid) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T5,T29,T63
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	260	if (key_reg_en)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	if (nonce_reg_en)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if (seed_valid_reg_en)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	390	case (state_q)
-2-:	394	if (kdi_en_i)
-3-:	401	if (req_valid)
-4-:	414	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-5-:	424	if (seed_cnt[0])
-6-:	426	if (scrmbl_ready_i)
-7-:	428	if (req_bundle.ingest_entropy)
-8-:	436	if (scrmbl_ready_i)
-9-:	445	if (edn_ack_i)
-10-:	448	if ((entropy_cnt == 2'b1))
-11-:	465	if (entropy_cnt[0])
-12-:	467	if (scrmbl_ready_i)
-13-:	472	if (scrmbl_ready_i)
-14-:	482	if (scrmbl_ready_i)
-15-:	492	if (scrmbl_valid_i)
-16-:	495	if ((seed_cnt == 2'b1))
-17-:	499	if (req_bundle.chained_digest)
-18-:	511	if (req_bundle.fetch_nonce)
-19-:	525	if (edn_ack_i)
-20-:	528	if ((entropy_cnt == req_bundle.nonce_size))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T4
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigClrSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T4
DigClrSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T148
DigLoadSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigLoadSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigLoadSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigLoadSt	-	-	-	0	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T4
DigLoadSt	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
FetchEntropySt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
FetchEntropySt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
FetchEntropySt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigEntropySt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigEntropySt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Not Covered
DigEntropySt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
DigEntropySt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T5,T65,T13
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T5,T6
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T5,T6
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T4,T5,T6
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	Covered	T4,T5,T6
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	Not Covered
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T5,T6
FetchNonceSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	Covered	T4,T5,T6
FetchNonceSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	Covered	T4,T5,T6
FetchNonceSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T6
FinishSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	560	if (((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || seed_cnt_err) || entropy_cnt_err))

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	571	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	574	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_kdi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	21	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	21	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EdnReqKnown_A	26050016	25806694	0	0
EntropyWidthDividesDigestBlockWidth_A	552	552	0	0
FlashOtpKeyRspKnown_A	26050016	25806694	0	0
FsmErrKnown_A	26050016	25806694	0	0
KeyNonceSize0_A	552	552	0	0
KeyNonceSize1_A	552	552	0	0
KeyNonceSize2_A	552	552	0	0
KeyNonceSize3_A	552	552	0	0
KeyNonceSize4_A	552	552	0	0
KeyNonceSize5_A	552	552	0	0
KeyNonceSize6_A	552	552	0	0
NonceWidth_A	552	552	0	0
OtbnOtpKeyRspKnown_A	26050016	25806694	0	0
ScrmblCmdKnown_A	26050016	25806694	0	0
ScrmblDataKnown_A	26050016	25806694	0	0
ScrmblModeKnown_A	26050016	25806694	0	0
ScrmblMtxReqKnown_A	26050016	25806694	0	0
ScrmblSelKnown_A	26050016	25806694	0	0
ScrmblValidKnown_A	26050016	25806694	0	0
SramOtpKeyRspKnown_A	26050016	25806694	0	0
u_state_regs_A	26050016	25806694	0	0

EdnReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

EntropyWidthDividesDigestBlockWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

FsmErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

KeyNonceSize0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize5_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

KeyNonceSize6_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

NonceWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	552	552	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OtbnOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

SramOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	25806694	0	0
T1	14672	14484	0	0
T2	14654	14378	0	0
T3	11603	11345	0	0
T4	24955	24423	0	0
T5	20141	19565	0	0
T9	24294	24025	0	0
T17	18877	18607	0	0
T18	15607	15337	0	0
T19	14051	13781	0	0
T20	12287	12094	0	0