Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	50.68			50.68
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	61.64			61.64
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	64.38			64.38
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	64.73			64.73
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	65.75			65.75
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	68.15			68.15
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	68.49			68.49
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	71.23			71.23
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	72.60			72.60
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	73.97			73.97
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	73.97			73.97
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	76.71			76.71
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	91.78			91.78
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.84			93.84

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.68			50.68

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.68			50.68

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.64			61.64

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.64			61.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.73			64.73

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.73			64.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.75			65.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.75			65.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.15			68.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.15			68.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.49			68.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.49			68.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.23			71.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.23			71.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.97			73.97

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.97			73.97

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.97			73.97

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.97			73.97

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.71			76.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.71			76.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78			91.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.78			91.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.84			93.84

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.84			93.84

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00				80.00	100.00	gen_ecc_reg.u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T48,T13,T52	Yes	T48,T13,T52	INPUT
data_o[63:0]	Yes	Yes	T47,T48,T66	Yes	T48,T13,T32	OUTPUT
syndrome_o[2:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T52,*T53,*T54	Yes	T52,T53,T54	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	148	50.68
Total Bits 0->1	146	104	71.23
Total Bits 1->0	146	44	30.14

Ports	4	0	0.00
Port Bits	292	148	50.68
Port Bits 0->1	146	104	71.23
Port Bits 1->0	146	44	30.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[15:0]	Yes	Yes	*T52,*T32,*T261	Yes	T52,T32,T261	INPUT
data_i[18:16]	No	No		Yes	T262	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[24:21]	No	No		Yes	T262	INPUT
data_i[26:25]	No	No		No		INPUT
data_i[28:27]	No	No		Yes	T262	INPUT
data_i[29]	No	No		No		INPUT
data_i[31:30]	No	No		Yes	T262	INPUT
data_i[32]	No	No		No		INPUT
data_i[33]	No	No		Yes	T262	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[39:36]	No	No		Yes	T262	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	No	No		Yes	T262	INPUT
data_i[42]	No	No		No		INPUT
data_i[46:43]	No	No		Yes	T262	INPUT
data_i[47]	No	No		No		INPUT
data_i[49:48]	No	No		Yes	T262	INPUT
data_i[50]	No	No		No		INPUT
data_i[53:51]	No	No		Yes	T262	INPUT
data_i[54]	No	No		No		INPUT
data_i[58:55]	No	No		Yes	T262	INPUT
data_i[63:59]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T20,T73,T74	Yes	T20,T73,T74	INPUT
data_o[15:0]	Yes	Yes	*T32,*T261,*T263	Yes	T32,T261,T263	OUTPUT
data_o[18:16]	No	No		Yes	T262	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[24:21]	No	No		Yes	T262	OUTPUT
data_o[26:25]	No	No		No		OUTPUT
data_o[28:27]	No	No		Yes	T262	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[31:30]	No	No		Yes	T262	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[33]	No	No		Yes	T262	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[39:36]	No	No		Yes	T262	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	No	No		Yes	T262	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[46:43]	No	No		Yes	T262	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[49:48]	No	No		Yes	T262	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[53:51]	No	No		Yes	T262	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[58:55]	No	No		Yes	T262	OUTPUT
data_o[63:59]	No	No		No		OUTPUT
syndrome_o[2:0]	Yes	Yes	T52,T161,T162	Yes	T52,T161,T162	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T52,*T161,*T162	Yes	T52,T161,T162	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	180	61.64
Total Bits 0->1	146	90	61.64
Total Bits 1->0	146	90	61.64

Ports	4	0	0.00
Port Bits	292	180	61.64
Port Bits 0->1	146	90	61.64
Port Bits 1->0	146	90	61.64

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[9]	No	No		No		INPUT
data_i[13:10]	Yes	Yes	T69,T71,T207	Yes	T7,T69,T71	INPUT
data_i[14]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	INPUT
data_i[26:24]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T69,T71,T207	Yes	T7,T69,T71	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[36:31]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	INPUT
data_i[40]	No	No		No		INPUT
data_i[49:41]	Yes	Yes	*T69,T71,T207	Yes	T7,T69,T71	INPUT
data_i[50]	No	No		No		INPUT
data_i[52:51]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[56:53]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T71,T207,T216	Yes	T7,T71,T207	INPUT
data_o[3:0]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	T69,T71,T207	Yes	T7,T69,T71	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	OUTPUT
data_o[26:24]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T69,T71,T207	Yes	T7,T69,T71	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[36:31]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T69,*T71,*T207	Yes	T7,T69,T71	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[49:41]	Yes	Yes	*T69,T71,T207	Yes	T7,T69,T71	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[52:51]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[56:53]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T71,T207,T216	Yes	T7,T71,T207	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	188	64.38
Total Bits 0->1	146	94	64.38
Total Bits 1->0	146	94	64.38

Ports	4	0	0.00
Port Bits	292	188	64.38
Port Bits 0->1	146	94	64.38
Port Bits 1->0	146	94	64.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[5]	No	No		No		INPUT
data_i[9:6]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[10]	No	No		No		INPUT
data_i[11]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	INPUT
data_i[16]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[23:22]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[24]	No	No		No		INPUT
data_i[31:25]	Yes	Yes	T69,T71,T104	Yes	T7,T69,T231	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[35]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T69,T71,T104	Yes	T7,T69,T231	INPUT
data_i[47]	No	No		No		INPUT
data_i[49:48]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[51:50]	No	No		No		INPUT
data_i[57:52]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T69,T71,T104	Yes	T7,T69,T71	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_o[1:0]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[9:6]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[11]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[23:22]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[31:25]	Yes	Yes	T69,T71,T104	Yes	T7,T69,T231	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T69,*T71,*T104	Yes	T7,T69,T231	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T69,T71,T104	Yes	T7,T69,T231	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[49:48]	Yes	Yes	*T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[51:50]	No	No		No		OUTPUT
data_o[57:52]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T69,T71,T104	Yes	T7,T69,T71	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	189	64.73
Total Bits 0->1	146	95	65.07
Total Bits 1->0	146	94	64.38

Ports	4	0	0.00
Port Bits	292	189	64.73
Port Bits 0->1	146	95	65.07
Port Bits 1->0	146	94	64.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[6:1]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[14:9]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[15]	No	No		No		INPUT
data_i[18:16]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	INPUT
data_i[19]	No	No		No		INPUT
data_i[22:20]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T71,*T216,*T214	Yes	T7,T71,T150	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[34:30]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[35]	No	No		No		INPUT
data_i[38:36]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	INPUT
data_i[39]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	INPUT
data_i[45:43]	No	No		No		INPUT
data_i[47:46]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T71,T216,T214	Yes	T71,T150,T216	INPUT
data_i[55]	No	No		No		INPUT
data_i[58:56]	Yes	Yes	T71,T216,T214	Yes	T71,T150,T216	INPUT
data_i[59]	No	No		No		INPUT
data_i[64:60]	Yes	Yes	*T71,*T216,*T214	Yes	T71,T150,T216	INPUT
data_i[65]	No	No		No		INPUT
data_i[69:66]	Yes	Yes	T71,*T216,*T214	Yes	T7,T71,T150	INPUT
data_i[70]	No	No		Yes	T7	INPUT
data_i[71]	Yes	Yes	T5,T6,T29	Yes	T6,T69,T72	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[6:1]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[14:9]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[18:16]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[22:20]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T71,*T216,*T214	Yes	T7,T71,T150	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[34:30]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[38:36]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	T71,T216,T214	Yes	T7,T71,T150	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[47:46]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T71,T216,T214	Yes	T71,T150,T216	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[58:56]	Yes	Yes	T71,T216,T214	Yes	T71,T150,T216	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T71,T216,T214	Yes	T71,T150,T216	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	192	65.75
Total Bits 0->1	146	96	65.75
Total Bits 1->0	146	96	65.75

Ports	4	0	0.00
Port Bits	292	192	65.75
Port Bits 0->1	146	96	65.75
Port Bits 1->0	146	96	65.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[6:0]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[7]	No	No		No		INPUT
data_i[9:8]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_i[15]	No	No		No		INPUT
data_i[19:16]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_i[25:23]	No	No		No		INPUT
data_i[27:26]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_i[28]	No	No		No		INPUT
data_i[30:29]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[32:31]	No	No		No		INPUT
data_i[36:33]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[43:39]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[44]	No	No		No		INPUT
data_i[47:45]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	INPUT
data_i[49:48]	No	No		No		INPUT
data_i[52:50]	Yes	Yes	*T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[53]	No	No		No		INPUT
data_i[57:54]	Yes	Yes	*T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[59:58]	No	No		No		INPUT
data_i[60]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T6,T71,T72	Yes	T5,T6,T70	INPUT
data_o[6:0]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[9:8]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[19:16]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
data_o[25:23]	No	No		No		OUTPUT
data_o[27:26]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
data_o[28]	No	No		No		OUTPUT
data_o[30:29]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[32:31]	No	No		No		OUTPUT
data_o[36:33]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[43:39]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[47:45]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[49:48]	No	No		No		OUTPUT
data_o[52:50]	Yes	Yes	*T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[57:54]	Yes	Yes	*T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[59:58]	No	No		No		OUTPUT
data_o[60]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T71,T72	Yes	T5,T6,T70	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	199	68.15
Total Bits 0->1	146	104	71.23
Total Bits 1->0	146	95	65.07

Ports	4	0	0.00
Port Bits	292	199	68.15
Port Bits 0->1	146	104	71.23
Port Bits 1->0	146	95	65.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[8]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[13]	No	No		No		INPUT
data_i[17:14]	Yes	Yes	T71,*T221,*T224	Yes	T71,T150,T225	INPUT
data_i[18]	No	No		No		INPUT
data_i[21:19]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[24:22]	No	No		No		INPUT
data_i[28:25]	Yes	Yes	T71,*T221,*T224	Yes	T71,T150,T225	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[38:31]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[39]	No	No		No		INPUT
data_i[45:40]	Yes	Yes	*T6,*T47,*T69	Yes	T5,T7,T6	INPUT
data_i[46]	No	No		No		INPUT
data_i[50:47]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[55:53]	No	No		Yes	T150,T232	INPUT
data_i[56]	No	No		No		INPUT
data_i[57]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[58]	No	No		Yes	T150,T232	INPUT
data_i[60:59]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[61]	No	No		No		INPUT
data_i[65:62]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[66]	No	No		Yes	T150,T232	INPUT
data_i[71:67]	Yes	Yes	T5,T7,T6	Yes	T6,T69,T71	INPUT
data_o[0]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[17:14]	Yes	Yes	T71,*T221,*T224	Yes	T71,T150,T225	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[21:19]	Yes	Yes	*T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[24:22]	No	No		No		OUTPUT
data_o[28:25]	Yes	Yes	T71,*T221,*T224	Yes	T71,T150,T225	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[38:31]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[45:40]	Yes	Yes	*T6,*T47,*T69	Yes	T5,T7,T6	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[50:47]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[55:53]	No	No		Yes	T150,T232	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[57]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[58]	No	No		Yes	T150,T232	OUTPUT
data_o[60:59]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	200	68.49
Total Bits 0->1	146	100	68.49
Total Bits 1->0	146	100	68.49

Ports	4	0	0.00
Port Bits	292	200	68.49
Port Bits 0->1	146	100	68.49
Port Bits 1->0	146	100	68.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	INPUT
data_i[5]	No	No		No		INPUT
data_i[10:6]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[23:17]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[27:26]	No	No		No		INPUT
data_i[33:28]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[41]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[49]	No	No		No		INPUT
data_i[59:50]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T69,T104,T207	Yes	T7,T6,T29	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T6,*T71,*T72	Yes	T5,T6,T70	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[10:6]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[23:17]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[27:26]	No	No		No		OUTPUT
data_o[33:28]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	T6,*T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[59:50]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	208	71.23
Total Bits 0->1	146	104	71.23
Total Bits 1->0	146	104	71.23

Ports	4	0	0.00
Port Bits	292	208	71.23
Port Bits 0->1	146	104	71.23
Port Bits 1->0	146	104	71.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_i[4]	No	No		No		INPUT
data_i[10:5]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[27:17]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[32:28]	No	No		No		INPUT
data_i[41:33]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[42]	No	No		No		INPUT
data_i[46:43]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[47]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[55]	No	No		No		INPUT
data_i[61:56]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[10:5]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[27:17]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[32:28]	No	No		No		OUTPUT
data_o[41:33]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[46:43]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[61:56]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	212	72.60
Total Bits 0->1	146	106	72.60
Total Bits 1->0	146	106	72.60

Ports	4	0	0.00
Port Bits	292	212	72.60
Port Bits 0->1	146	106	72.60
Port Bits 1->0	146	106	72.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T6,T72,T229	Yes	T6,T72,T230	INPUT
data_i[2]	No	No		No		INPUT
data_i[7:3]	Yes	Yes	T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T6,*T72,*T229	Yes	T6,T72,T230	INPUT
data_i[19]	No	No		No		INPUT
data_i[28:20]	Yes	Yes	T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[36:31]	Yes	Yes	T6,T72,*T229	Yes	T6,T72,T230	INPUT
data_i[37]	No	No		No		INPUT
data_i[45:38]	Yes	Yes	T6,T72,*T229	Yes	T6,T72,T230	INPUT
data_i[48:46]	No	No		No		INPUT
data_i[53:49]	Yes	Yes	T6,T72,*T229	Yes	T6,T72,T230	INPUT
data_i[54]	No	No		No		INPUT
data_i[56:55]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[57]	No	No		No		INPUT
data_i[60:58]	Yes	Yes	T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_o[1:0]	Yes	Yes	T6,T72,T229	Yes	T6,T72,T230	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[7:3]	Yes	Yes	T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T6,*T72,*T229	Yes	T6,T72,T230	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[28:20]	Yes	Yes	T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[36:31]	Yes	Yes	T6,T72,*T229	Yes	T6,T72,T230	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[45:38]	Yes	Yes	T6,T72,*T229	Yes	T6,T72,T230	OUTPUT
data_o[48:46]	No	No		No		OUTPUT
data_o[53:49]	Yes	Yes	T6,T72,*T229	Yes	T6,T72,T230	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[56:55]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[60:58]	Yes	Yes	T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	216	73.97
Total Bits 0->1	146	108	73.97
Total Bits 1->0	146	108	73.97

Ports	4	0	0.00
Port Bits	292	216	73.97
Port Bits 0->1	146	108	73.97
Port Bits 1->0	146	108	73.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	No	No		No		INPUT
data_i[12:2]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	INPUT
data_i[15]	No	No		No		INPUT
data_i[20:16]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[22:21]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[25]	No	No		No		INPUT
data_i[37:26]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	INPUT
data_i[38]	No	No		No		INPUT
data_i[40:39]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_i[42:41]	No	No		No		INPUT
data_i[51:43]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[55]	No	No		No		INPUT
data_i[57:56]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_i[58]	No	No		No		INPUT
data_i[60:59]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[12:2]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[20:16]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[22:21]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[37:26]	Yes	Yes	*T7,*T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[40:39]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
data_o[42:41]	No	No		No		OUTPUT
data_o[51:43]	Yes	Yes	T7,T6,*T69	Yes	T5,T7,T6	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[57:56]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[60:59]	Yes	Yes	T7,T6,T71	Yes	T5,T7,T6	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T7,T6,T69	Yes	T5,T7,T6	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	216	73.97
Total Bits 0->1	146	108	73.97
Total Bits 1->0	146	108	73.97

Ports	4	0	0.00
Port Bits	292	216	73.97
Port Bits 0->1	146	108	73.97
Port Bits 1->0	146	108	73.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[5:0]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[20:18]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[22]	No	No		No		INPUT
data_i[34:23]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[35]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T264	Yes	T264	INPUT
data_i[37]	No	No		No		INPUT
data_i[42:38]	Yes	Yes	T69,T71,T104	Yes	T5,T7,T6	INPUT
data_i[43]	No	No		No		INPUT
data_i[47:44]	Yes	Yes	*T69,*T71,*T104	Yes	T5,T7,T6	INPUT
data_i[48]	No	No		No		INPUT
data_i[59:49]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[60]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_o[5:0]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[20:18]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[34:23]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T264	Yes	T264	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[42:38]	Yes	Yes	T69,T71,T104	Yes	T5,T7,T6	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[47:44]	Yes	Yes	*T69,*T71,*T104	Yes	T5,T7,T6	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[59:49]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	224	76.71
Total Bits 0->1	146	112	76.71
Total Bits 1->0	146	112	76.71

Ports	4	0	0.00
Port Bits	292	224	76.71
Port Bits 0->1	146	112	76.71
Port Bits 1->0	146	112	76.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[4:0]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[19]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[26]	No	No		No		INPUT
data_i[44:27]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	INPUT
data_i[47:45]	No	No		No		INPUT
data_i[71:48]	Yes	Yes	T19,T6,T69	Yes	T19,T5,T7	INPUT
data_o[4:0]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	T6,T69,T71	Yes	T5,T7,T6	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[44:27]	Yes	Yes	*T6,*T69,*T71	Yes	T5,T7,T6	OUTPUT
data_o[47:45]	No	No		No		OUTPUT
data_o[63:48]	Yes	Yes	T19,T6,T69	Yes	T19,T5,T7	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	268	91.78
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	128	87.67

Ports	4	0	0.00
Port Bits	292	268	91.78
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	128	87.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[26:0]	Yes	Yes	*T48,*T13,*T52	Yes	T48,T13,T52	INPUT
data_i[27]	No	No		Yes	T148	INPUT
data_i[28]	Yes	Yes	*T48,*T265	Yes	T48,T265,T266	INPUT
data_i[29]	No	No		Yes	T266,T148,T267	INPUT
data_i[34:30]	Yes	Yes	*T13,*T265,*T48	Yes	T13,T265,T267	INPUT
data_i[36:35]	No	No		Yes	T266,T148,T267	INPUT
data_i[38:37]	Yes	Yes	T48,*T265	Yes	T48,T267,T265	INPUT
data_i[39]	No	No		Yes	T266,T267	INPUT
data_i[43:40]	Yes	Yes	*T48,*T13,*T265	Yes	T48,T13,T265	INPUT
data_i[44]	No	No		Yes	T148	INPUT
data_i[71:45]	Yes	Yes	T48,T265,T13	Yes	T48,T148,T265	INPUT
data_o[26:0]	Yes	Yes	*T48,*T13,*T98	Yes	T48,T13,T98	OUTPUT
data_o[27]	No	No		Yes	T148	OUTPUT
data_o[28]	Yes	Yes	*T48,*T265	Yes	T48,T265,T266	OUTPUT
data_o[29]	No	No		Yes	T266,T148,T267	OUTPUT
data_o[34:30]	Yes	Yes	*T13,*T265,*T48	Yes	T13,T265,T267	OUTPUT
data_o[36:35]	No	No		Yes	T266,T148,T267	OUTPUT
data_o[38:37]	Yes	Yes	T48,*T265	Yes	T48,T267,T265	OUTPUT
data_o[39]	No	No		Yes	T266,T267	OUTPUT
data_o[43:40]	Yes	Yes	*T48,*T13,*T265	Yes	T48,T13,T265	OUTPUT
data_o[44]	No	No		Yes	T148	OUTPUT
data_o[63:45]	Yes	Yes	T48,T265,T13	Yes	T48,T148,T265	OUTPUT
syndrome_o[2:0]	Yes	Yes	T52,T54,T165	Yes	T52,T54,T165	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T52,*T54,*T165	Yes	T52,T54,T165	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T47,T66,T268	Yes	T47,T63,T66	INPUT
data_o[63:0]	Yes	Yes	T47,T66,T268	Yes	T47,T63,T66	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T205,T100,T269	Yes	T205,T100,T269	INPUT
data_o[63:0]	Yes	Yes	T205,T100,T269	Yes	T205,T100,T269	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T57,T34,T103	Yes	T57,T34,T103	INPUT
data_o[63:0]	Yes	Yes	T57,T34,T103	Yes	T57,T34,T103	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T17,T145,T268	Yes	T17,T145,T268	INPUT
data_o[63:0]	Yes	Yes	T17,T145,T268	Yes	T17,T145,T268	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T66,T104,T213	Yes	T66,T104,T213	INPUT
data_o[63:0]	Yes	Yes	T66,T104,T213	Yes	T66,T104,T213	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T2,T18,T30	Yes	T2,T18,T30	INPUT
data_o[63:0]	Yes	Yes	T2,T18,T30	Yes	T2,T18,T30	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T35,T180	Yes	T5,T64,T35	INPUT
data_o[63:0]	Yes	Yes	T5,T35,T180	Yes	T5,T64,T35	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T17,T29,T270	Yes	T17,T29,T270	INPUT
data_o[63:0]	Yes	Yes	T17,T29,T270	Yes	T17,T29,T270	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T18,T4,T271	Yes	T18,T4,T7	INPUT
data_o[63:0]	Yes	Yes	T18,T4,T271	Yes	T18,T4,T7	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T17,T18,T5	Yes	T17,T18,T5	INPUT
data_o[63:0]	Yes	Yes	T17,T18,T5	Yes	T17,T18,T5	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T268,T69	Yes	T6,T29,T268	INPUT
data_o[63:0]	Yes	Yes	T6,T268,T69	Yes	T6,T29,T268	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	INPUT
data_o[63:0]	Yes	Yes	T17,T19,T47	Yes	T17,T19,T47	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T18,T33,T36	Yes	T18,T33,T36	INPUT
data_o[63:0]	Yes	Yes	T18,T33,T36	Yes	T18,T33,T36	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	INPUT
data_o[63:0]	Yes	Yes	T4,T5,T33	Yes	T4,T5,T33	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T4	INPUT
data_o[63:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T4	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T29,T30,T268	Yes	T4,T29,T30	INPUT
data_o[63:0]	Yes	Yes	T29,T30,T268	Yes	T4,T29,T30	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T30,T216	Yes	T5,T7,T30	INPUT
data_o[63:0]	Yes	Yes	T5,T30,T216	Yes	T5,T7,T30	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T72,T103,T45	Yes	T4,T71,T72	INPUT
data_o[63:0]	Yes	Yes	T72,T103,T45	Yes	T4,T71,T72	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T29,T69,T103	Yes	T5,T29,T69	INPUT
data_o[63:0]	Yes	Yes	T29,T69,T103	Yes	T5,T29,T69	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T69,T44	Yes	T6,T69,T70	INPUT
data_o[63:0]	Yes	Yes	T6,T69,T44	Yes	T6,T69,T70	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T4,T29,T32	Yes	T4,T29,T32	INPUT
data_o[63:0]	Yes	Yes	T4,T29,T32	Yes	T4,T29,T32	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T68,T100,T230	Yes	T7,T63,T64	INPUT
data_o[63:0]	Yes	Yes	T68,T100,T230	Yes	T7,T63,T64	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T4,T65,T71	Yes	T4,T7,T65	INPUT
data_o[63:0]	Yes	Yes	T4,T65,T71	Yes	T4,T7,T65	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	274	93.84
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	134	91.78

Ports	4	0	0.00
Port Bits	292	274	93.84
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	134	91.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[30:0]	Yes	Yes	*T48,*T52,*T183	Yes	T48,T52,T183	INPUT
data_i[31]	No	No		Yes	T255,T147,T198	INPUT
data_i[41:32]	Yes	Yes	*T13,*T48,*T272	Yes	T13,T146,T48	INPUT
data_i[42]	No	No		Yes	T146	INPUT
data_i[56:43]	Yes	Yes	*T13,*T48,*T272	Yes	T146,T13,T148	INPUT
data_i[57]	No	No		Yes	T147,T198	INPUT
data_i[71:58]	Yes	Yes	T272,T273,T48	Yes	T146,T272,T147	INPUT
data_o[30:0]	Yes	Yes	*T48,*T183,*T274	Yes	T48,T183,T274	OUTPUT
data_o[31]	No	No		Yes	T255,T147,T198	OUTPUT
data_o[41:32]	Yes	Yes	*T13,*T48,*T272	Yes	T13,T146,T48	OUTPUT
data_o[42]	No	No		Yes	T146	OUTPUT
data_o[56:43]	Yes	Yes	*T13,*T48,*T272	Yes	T146,T13,T148	OUTPUT
data_o[57]	No	No		Yes	T147,T198	OUTPUT
data_o[63:58]	Yes	Yes	T272,T273,T48	Yes	T146,T272,T147	OUTPUT
syndrome_o[2:0]	Yes	Yes	T52,T53,T165	Yes	T52,T53,T165	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T52,*T53,*T165	Yes	T52,T53,T165	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range