Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8461907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10966311

1

T1

1020

T2

621

T3

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8844573	1			T1	5934		T2	3455		T3	1740
values[0x0]	3879806	1			T1	287		T2	170		T3	24
values[0x1]	6703839	1			T1	257		T2	165		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4966282	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14461936

1

T1

2708

T2

1626

T3

617

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	68154	1			T1	57		T3	5		T4	6
valid_sources[0x01]	68262	1			T1	51		T3	4		T4	5
valid_sources[0x02]	71761	1			T1	20		T3	8		T4	6
valid_sources[0x03]	68230	1			T1	49		T3	10		T4	7
valid_sources[0x04]	67066	1			T1	45		T3	3		T4	7
valid_sources[0x05]	75347	1			T1	21		T3	6		T4	9
valid_sources[0x06]	71715	1			T1	19		T3	9		T4	8
valid_sources[0x07]	70002	1			T1	24		T3	5		T4	7
valid_sources[0x08]	65202	1			T1	11		T3	6		T4	11
valid_sources[0x09]	70983	1			T1	15		T3	9		T4	13
valid_sources[0x0a]	69433	1			T1	29		T3	6		T4	10
valid_sources[0x0b]	65599	1			T1	17		T3	7		T4	9
valid_sources[0x0c]	67348	1			T1	27		T3	9		T4	3
valid_sources[0x0d]	70137	1			T1	37		T3	10		T4	6
valid_sources[0x0e]	76003	1			T1	49		T3	6		T4	10
valid_sources[0x0f]	65766	1			T1	31		T3	11		T4	6
valid_sources[0x10]	172497	1			T1	21		T3	1		T4	12
valid_sources[0x11]	69493	1			T1	31		T3	3		T4	9
valid_sources[0x12]	68390	1			T1	19		T3	8		T4	10
valid_sources[0x13]	69158	1			T1	27		T3	4		T4	4
valid_sources[0x14]	69235	1			T1	37		T3	6		T4	10
valid_sources[0x15]	69206	1			T1	47		T3	5		T4	6
valid_sources[0x16]	72930	1			T1	10		T3	7		T4	8
valid_sources[0x17]	67134	1			T1	31		T3	9		T4	6
valid_sources[0x18]	71702	1			T1	36		T3	8		T4	7
valid_sources[0x19]	73214	1			T1	17		T3	8		T4	9
valid_sources[0x1a]	66770	1			T1	8		T3	9		T4	3
valid_sources[0x1b]	75730	1			T1	15		T3	11		T4	5
valid_sources[0x1c]	65565	1			T1	21		T3	3		T4	13
valid_sources[0x1d]	73824	1			T1	34		T3	3		T4	6
valid_sources[0x1e]	71040	1			T1	13		T3	6		T4	7
valid_sources[0x1f]	74983	1			T1	33		T3	7		T4	8
valid_sources[0x20]	68657	1			T1	31		T3	4		T4	6
valid_sources[0x21]	80348	1			T1	34		T3	5		T4	6
valid_sources[0x22]	69484	1			T1	23		T3	2		T4	3
valid_sources[0x23]	82506	1			T1	18		T3	5		T4	6
valid_sources[0x24]	85252	1			T1	18		T3	10		T4	5
valid_sources[0x25]	67548	1			T1	24		T3	9		T4	4
valid_sources[0x26]	74481	1			T1	25		T3	6		T4	7
valid_sources[0x27]	76583	1			T1	21		T3	5		T4	6
valid_sources[0x28]	68234	1			T1	24		T3	4		T4	6
valid_sources[0x29]	70404	1			T1	33		T3	13		T4	9
valid_sources[0x2a]	66775	1			T1	36		T3	3		T4	8
valid_sources[0x2b]	70741	1			T1	20		T3	1		T4	11
valid_sources[0x2c]	69583	1			T1	21		T3	5		T4	7
valid_sources[0x2d]	71170	1			T1	11		T3	3		T4	5
valid_sources[0x2e]	69452	1			T1	24		T3	3		T4	9
valid_sources[0x2f]	83735	1			T1	36		T3	7		T4	12
valid_sources[0x30]	75398	1			T1	26		T3	9		T4	14
valid_sources[0x31]	69694	1			T1	27		T3	3		T4	4
valid_sources[0x32]	71563	1			T1	12		T3	7		T4	8
valid_sources[0x33]	70999	1			T1	6		T3	2		T4	4
valid_sources[0x34]	77837	1			T1	23		T3	8		T4	9
valid_sources[0x35]	67271	1			T1	19		T3	4		T4	6
valid_sources[0x36]	69318	1			T1	38		T3	2		T4	8
valid_sources[0x37]	77588	1			T1	24		T3	6		T4	8
valid_sources[0x38]	70875	1			T1	22		T3	6		T4	13
valid_sources[0x39]	69472	1			T1	26		T3	4		T4	4
valid_sources[0x3a]	72814	1			T1	20		T3	5		T4	6
valid_sources[0x3b]	80194	1			T1	32		T3	11		T4	9
valid_sources[0x3c]	80598	1			T1	32		T3	2		T4	9
valid_sources[0x3d]	79818	1			T1	29		T3	13		T4	9
valid_sources[0x3e]	71779	1			T1	15		T3	7		T4	4
valid_sources[0x3f]	71127	1			T1	21		T3	4		T4	8
valid_sources[0x40]	71224	1			T1	20		T3	6		T4	9
valid_sources[0x41]	76919	1			T1	35		T3	5		T4	10
valid_sources[0x42]	68845	1			T1	38		T3	1		T4	5
valid_sources[0x43]	70834	1			T1	20		T3	13		T4	10
valid_sources[0x44]	72640	1			T1	27		T3	10		T4	8
valid_sources[0x45]	75561	1			T1	32		T3	6		T4	7
valid_sources[0x46]	66130	1			T1	16		T3	11		T4	7
valid_sources[0x47]	86266	1			T1	27		T3	2		T4	8
valid_sources[0x48]	68890	1			T1	22		T3	7		T4	5
valid_sources[0x49]	68039	1			T1	32		T3	15		T4	9
valid_sources[0x4a]	73018	1			T1	33		T3	2		T4	4
valid_sources[0x4b]	86314	1			T1	26		T3	11		T4	9
valid_sources[0x4c]	66449	1			T1	13		T3	5		T4	6
valid_sources[0x4d]	70344	1			T1	19		T3	4		T4	10
valid_sources[0x4e]	69588	1			T1	21		T3	1		T4	5
valid_sources[0x4f]	133270	1			T1	23		T3	14		T4	6
valid_sources[0x50]	68607	1			T1	19		T3	13		T4	5
valid_sources[0x51]	84043	1			T1	34		T3	3		T4	9
valid_sources[0x52]	76984	1			T1	27		T3	12		T4	8
valid_sources[0x53]	74921	1			T1	22		T3	11		T4	7
valid_sources[0x54]	70729	1			T1	32		T3	1		T4	7
valid_sources[0x55]	72373	1			T1	25		T3	7		T4	8
valid_sources[0x56]	71928	1			T1	35		T3	7		T4	7
valid_sources[0x57]	70485	1			T1	28		T3	6		T4	9
valid_sources[0x58]	75507	1			T1	36		T3	1		T4	11
valid_sources[0x59]	84759	1			T1	21		T3	12		T4	5
valid_sources[0x5a]	70431	1			T1	17		T3	8		T4	11
valid_sources[0x5b]	83020	1			T1	30		T3	18		T4	6
valid_sources[0x5c]	74046	1			T1	13		T3	4		T4	7
valid_sources[0x5d]	64944	1			T1	11		T3	4		T4	10
valid_sources[0x5e]	181816	1			T1	39		T3	2		T4	8
valid_sources[0x5f]	70967	1			T1	20		T3	3		T4	4
valid_sources[0x60]	65027	1			T1	9		T3	6		T4	7
valid_sources[0x61]	69101	1			T1	15		T3	9		T4	4
valid_sources[0x62]	70842	1			T1	45		T3	12		T4	9
valid_sources[0x63]	80305	1			T1	27		T3	4		T4	8
valid_sources[0x64]	70089	1			T1	19		T3	11		T4	5
valid_sources[0x65]	80125	1			T1	15		T3	7		T4	10
valid_sources[0x66]	77842	1			T1	23		T3	8		T4	9
valid_sources[0x67]	68178	1			T1	25		T3	7		T4	7
valid_sources[0x68]	73146	1			T1	37		T3	2		T4	5
valid_sources[0x69]	75185	1			T1	33		T3	11		T4	5
valid_sources[0x6a]	71536	1			T1	31		T3	9		T4	7
valid_sources[0x6b]	72440	1			T1	16		T3	17		T4	5
valid_sources[0x6c]	79957	1			T1	21		T3	4		T4	8
valid_sources[0x6d]	72134	1			T1	21		T3	8		T4	8
valid_sources[0x6e]	70665	1			T1	16		T3	8		T4	4
valid_sources[0x6f]	70529	1			T1	15		T3	6		T4	6
valid_sources[0x70]	71721	1			T1	19		T3	3		T4	7
valid_sources[0x71]	66821	1			T1	33		T3	2		T4	7
valid_sources[0x72]	143721	1			T1	25		T3	5		T4	7
valid_sources[0x73]	80692	1			T1	24		T3	6		T4	8
valid_sources[0x74]	70594	1			T1	29		T3	3		T4	10
valid_sources[0x75]	69536	1			T1	26		T3	9		T4	7
valid_sources[0x76]	69622	1			T1	32		T3	9		T4	3
valid_sources[0x77]	72064	1			T1	35		T3	6		T4	6
valid_sources[0x78]	65685	1			T1	19		T3	7		T4	7
valid_sources[0x79]	69280	1			T1	31		T4	9		T10	7
valid_sources[0x7a]	70998	1			T1	33		T3	14		T4	8
valid_sources[0x7b]	80661	1			T1	23		T3	5		T4	7
valid_sources[0x7c]	72613	1			T1	32		T3	14		T4	6
valid_sources[0x7d]	69663	1			T1	19		T3	5		T4	4
valid_sources[0x7e]	78986	1			T1	43		T3	9		T4	8
valid_sources[0x7f]	70278	1			T1	44		T3	3		T4	5
valid_sources[0x80]	67037	1			T1	26		T3	7		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4273351

1

T1

785

T2

462

T3

62

values[0x0]

all_enables

biggest_size

3382365

1

T1

148

T2

89

T3

7

values[0x1]

all_enables

biggest_size

3310595

1

T1

87

T2

70

T3

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	466868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16963947

1

T1

120

T2

100

T3

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4290781	1			T1	60		T2	50		T3	20
values[0x0]	6376207	1			T1	29		T2	20		T3	10
values[0x1]	6763827	1			T1	31		T2	30		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163146	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17267669

1

T1

120

T2

100

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	72164	1			T2	2		T17	1		T31	1
valid_sources[0x01]	66309	1			T110	1		T99	1		T100	1
valid_sources[0x02]	66170	1			T2	1		T9	2		T110	1
valid_sources[0x03]	68598	1			T8	1		T96	2		T31	5
valid_sources[0x04]	70335	1			T1	1		T4	1		T8	1
valid_sources[0x05]	67283	1			T4	1		T31	1		T100	1
valid_sources[0x06]	64927	1			T8	3		T17	1		T96	2
valid_sources[0x07]	66220	1			T8	3		T9	2		T96	1
valid_sources[0x08]	69186	1			T8	1		T9	1		T96	1
valid_sources[0x09]	66357	1			T9	1		T17	1		T40	4
valid_sources[0x0a]	69066	1			T9	3		T12	3		T96	1
valid_sources[0x0b]	67708	1			T9	1		T12	2		T96	2
valid_sources[0x0c]	67729	1			T1	1		T2	2		T228	2
valid_sources[0x0d]	67982	1			T12	1		T110	1		T31	1
valid_sources[0x0e]	67290	1			T9	5		T10	17		T12	3
valid_sources[0x0f]	66930	1			T9	2		T12	1		T40	4
valid_sources[0x10]	64863	1			T1	1		T2	2		T100	2
valid_sources[0x11]	66478	1			T100	1		T20	2		T145	1
valid_sources[0x12]	67763	1			T12	1		T17	1		T96	1
valid_sources[0x13]	68133	1			T2	1		T4	1		T12	1
valid_sources[0x14]	65764	1			T110	1		T96	2		T100	2
valid_sources[0x15]	70869	1			T1	3		T2	1		T17	1
valid_sources[0x16]	68078	1			T9	1		T12	3		T20	1
valid_sources[0x17]	68254	1			T97	5		T99	1		T145	2
valid_sources[0x18]	65758	1			T96	2		T97	1		T145	10
valid_sources[0x19]	69662	1			T105	2		T14	376		T15	230
valid_sources[0x1a]	68625	1			T9	2		T12	1		T99	1
valid_sources[0x1b]	67030	1			T96	2		T99	1		T145	1
valid_sources[0x1c]	63066	1			T2	2		T9	1		T40	4
valid_sources[0x1d]	65712	1			T110	1		T100	1		T252	2
valid_sources[0x1e]	68837	1			T9	1		T96	2		T97	2
valid_sources[0x1f]	68055	1			T8	1		T9	1		T12	1
valid_sources[0x20]	70217	1			T1	1		T9	2		T97	1
valid_sources[0x21]	64917	1			T2	1		T9	2		T12	1
valid_sources[0x22]	70141	1			T12	1		T17	3		T109	3
valid_sources[0x23]	68236	1			T8	2		T12	1		T99	1
valid_sources[0x24]	69249	1			T8	1		T9	1		T10	2
valid_sources[0x25]	67573	1			T8	1		T9	1		T12	2
valid_sources[0x26]	68084	1			T9	1		T12	1		T99	2
valid_sources[0x27]	67360	1			T9	1		T12	2		T40	3
valid_sources[0x28]	68783	1			T9	1		T12	4		T96	1
valid_sources[0x29]	70598	1			T9	1		T12	1		T109	2
valid_sources[0x2a]	68412	1			T9	2		T12	1		T97	1
valid_sources[0x2b]	70488	1			T9	2		T252	1		T105	1
valid_sources[0x2c]	69700	1			T8	1		T9	1		T12	3
valid_sources[0x2d]	66809	1			T9	1		T11	3		T17	1
valid_sources[0x2e]	63173	1			T12	1		T96	1		T97	5
valid_sources[0x2f]	65480	1			T1	2		T97	2		T103	1
valid_sources[0x30]	67032	1			T96	1		T101	4		T239	4
valid_sources[0x31]	72655	1			T9	1		T110	1		T96	1
valid_sources[0x32]	66663	1			T9	1		T103	1		T105	3
valid_sources[0x33]	72721	1			T2	1		T9	1		T12	2
valid_sources[0x34]	64960	1			T2	1		T12	1		T110	1
valid_sources[0x35]	69715	1			T1	1		T10	1		T110	4
valid_sources[0x36]	65512	1			T97	1		T228	1		T105	2
valid_sources[0x37]	67801	1			T8	1		T10	1		T17	1
valid_sources[0x38]	70980	1			T9	1		T12	1		T96	1
valid_sources[0x39]	70410	1			T8	1		T12	1		T17	1
valid_sources[0x3a]	67114	1			T2	1		T97	5		T103	1
valid_sources[0x3b]	65154	1			T9	2		T17	1		T99	1
valid_sources[0x3c]	73336	1			T2	3		T9	2		T96	1
valid_sources[0x3d]	67266	1			T9	3		T96	1		T99	1
valid_sources[0x3e]	65973	1			T9	1		T40	14		T97	1
valid_sources[0x3f]	66297	1			T1	1		T40	13		T97	1
valid_sources[0x40]	68384	1			T2	2		T9	1		T110	1
valid_sources[0x41]	69125	1			T2	2		T9	2		T96	2
valid_sources[0x42]	66775	1			T1	1		T2	1		T97	10
valid_sources[0x43]	67555	1			T100	3		T160	1		T239	3
valid_sources[0x44]	68962	1			T1	5		T12	1		T96	4
valid_sources[0x45]	70414	1			T9	1		T105	1		T239	1
valid_sources[0x46]	68351	1			T1	2		T9	2		T96	1
valid_sources[0x47]	73008	1			T9	2		T109	2		T31	2
valid_sources[0x48]	70757	1			T12	4		T96	1		T31	12
valid_sources[0x49]	64084	1			T9	1		T110	3		T31	1
valid_sources[0x4a]	68045	1			T1	1		T2	2		T12	2
valid_sources[0x4b]	66714	1			T2	1		T96	1		T100	1
valid_sources[0x4c]	66352	1			T9	1		T12	2		T17	1
valid_sources[0x4d]	68877	1			T9	2		T110	1		T99	1
valid_sources[0x4e]	66277	1			T9	1		T10	1		T12	3
valid_sources[0x4f]	73239	1			T2	1		T9	2		T12	1
valid_sources[0x50]	64751	1			T8	1		T9	1		T97	1
valid_sources[0x51]	66670	1			T10	4		T12	3		T31	2
valid_sources[0x52]	69019	1			T12	1		T110	1		T96	1
valid_sources[0x53]	66263	1			T110	2		T96	1		T99	2
valid_sources[0x54]	66530	1			T4	1		T8	2		T9	1
valid_sources[0x55]	68044	1			T9	1		T252	1		T103	1
valid_sources[0x56]	67039	1			T2	3		T9	1		T96	2
valid_sources[0x57]	67707	1			T9	1		T96	1		T99	1
valid_sources[0x58]	69299	1			T12	3		T17	2		T96	3
valid_sources[0x59]	67796	1			T8	1		T9	3		T12	2
valid_sources[0x5a]	67077	1			T2	9		T8	3		T12	1
valid_sources[0x5b]	70625	1			T1	4		T2	1		T12	1
valid_sources[0x5c]	67863	1			T11	8		T17	1		T100	2
valid_sources[0x5d]	66461	1			T96	2		T20	3		T252	1
valid_sources[0x5e]	67757	1			T9	5		T17	1		T109	2
valid_sources[0x5f]	65112	1			T9	1		T97	2		T100	1
valid_sources[0x60]	67564	1			T97	1		T99	2		T100	1
valid_sources[0x61]	65915	1			T108	5		T105	3		T157	160
valid_sources[0x62]	65952	1			T96	2		T99	1		T100	2
valid_sources[0x63]	69644	1			T4	3		T12	1		T96	1
valid_sources[0x64]	67199	1			T8	1		T9	1		T96	1
valid_sources[0x65]	66733	1			T9	2		T12	1		T17	2
valid_sources[0x66]	66102	1			T109	1		T96	1		T97	1
valid_sources[0x67]	67493	1			T9	1		T17	1		T31	3
valid_sources[0x68]	69288	1			T9	2		T96	2		T31	2
valid_sources[0x69]	67903	1			T8	1		T12	1		T17	2
valid_sources[0x6a]	68775	1			T9	2		T12	2		T103	1
valid_sources[0x6b]	68273	1			T2	2		T97	1		T99	1
valid_sources[0x6c]	67303	1			T1	4		T4	1		T8	5
valid_sources[0x6d]	68258	1			T12	2		T17	1		T5	1140
valid_sources[0x6e]	68684	1			T2	2		T12	1		T228	1
valid_sources[0x6f]	67253	1			T9	3		T12	1		T109	2
valid_sources[0x70]	71768	1			T9	1		T97	1		T252	3
valid_sources[0x71]	69854	1			T9	1		T12	1		T96	2
valid_sources[0x72]	69143	1			T8	1		T40	3		T100	1
valid_sources[0x73]	66024	1			T110	2		T99	1		T100	1
valid_sources[0x74]	69728	1			T2	1		T96	2		T31	3
valid_sources[0x75]	66057	1			T9	1		T12	2		T20	1
valid_sources[0x76]	69196	1			T2	1		T9	2		T12	1
valid_sources[0x77]	72486	1			T9	1		T12	2		T109	1
valid_sources[0x78]	65202	1			T3	40		T9	3		T96	1
valid_sources[0x79]	68569	1			T9	1		T96	1		T31	1
valid_sources[0x7a]	65386	1			T1	1		T12	1		T96	3
valid_sources[0x7b]	66842	1			T8	2		T31	3		T100	1
valid_sources[0x7c]	68690	1			T12	2		T110	1		T96	1
valid_sources[0x7d]	70694	1			T1	2		T2	1		T96	1
valid_sources[0x7e]	69011	1			T1	1		T9	4		T12	1
valid_sources[0x7f]	66464	1			T4	2		T8	1		T9	4
valid_sources[0x80]	69148	1			T1	6		T2	1		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4277835

1

T1

60

T2

50

T3

20

values[0x0]

all_enables

biggest_size

6344017

1

T1

29

T2

20

T3

10

values[0x1]

all_enables

biggest_size

6342095

1

T1

31

T2

30

T3

10