Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

43677369

1

T1

5458

T2

3169

T3

1711

full_word

13108414

1

T1

1020

T2

621

T3

75

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	56785463	1			T1	6478		T2	3790		T3	1786
auto[TlIntgErrCmd]	116	1			T259	7		T260	4		T261	10
auto[TlIntgErrData]	103	1			T259	1		T260	3		T261	5
auto[TlIntgErrBoth]	101	1			T259	2		T260	3		T261	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11412370

1

T1

5934

T2

3455

T3

1740

auto[1]

45373413

1

T1

544

T2

335

T3

46

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6878953	1			T1	5149		T2	2993		T3	1678
auto[TlIntgErrNone]	partial	auto[1]	36798115	1			T1	309		T2	176		T3	33
auto[TlIntgErrNone]	full_word	auto[0]	4533252	1			T1	785		T2	462		T3	62
auto[TlIntgErrNone]	full_word	auto[1]	8575143	1			T1	235		T2	159		T3	13
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T259	2		T260	1		T261	6
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T259	5		T260	1		T261	4
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T260	2		T348	1		T349	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T350	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	52	1			T259	1		T260	1		T261	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T260	2		T261	2		T351	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T348	1		T352	2		T266	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T349	1		T353	1		T354	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T261	3		T351	2		T348	4
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T259	2		T260	3		T261	2
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T355	1		T356	1		-	-