Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9910740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13232594

1

T1

1682

T2

424

T3

1479

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10111627	1			T1	3093		T2	2032		T3	2830
values[0x0]	4777205	1			T1	288		T2	53		T3	204
values[0x1]	8254502	1			T1	299		T2	54		T3	143

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5712320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17431014

1

T1

2114

T2

934

T3

1834

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	83709	1			T1	18		T2	12		T4	7
valid_sources[0x01]	89768	1			T1	14		T2	11		T4	4
valid_sources[0x02]	93718	1			T1	18		T4	3		T7	26
valid_sources[0x03]	84609	1			T1	14		T2	5		T4	4
valid_sources[0x04]	84293	1			T1	16		T2	14		T4	2
valid_sources[0x05]	87136	1			T1	19		T2	11		T4	3
valid_sources[0x06]	88065	1			T1	11		T2	17		T4	4
valid_sources[0x07]	90957	1			T1	13		T2	6		T4	6
valid_sources[0x08]	83972	1			T1	17		T2	12		T4	6
valid_sources[0x09]	88666	1			T1	17		T2	7		T4	5
valid_sources[0x0a]	95204	1			T1	11		T2	11		T4	3
valid_sources[0x0b]	83205	1			T1	10		T2	18		T4	4
valid_sources[0x0c]	86763	1			T1	12		T2	6		T4	1
valid_sources[0x0d]	86292	1			T1	15		T2	18		T4	7
valid_sources[0x0e]	93310	1			T1	16		T2	2		T4	4
valid_sources[0x0f]	84825	1			T1	19		T2	3		T4	3
valid_sources[0x10]	89540	1			T1	12		T2	4		T4	3
valid_sources[0x11]	130150	1			T1	11		T2	8		T4	2
valid_sources[0x12]	85668	1			T1	13		T2	6		T4	2
valid_sources[0x13]	84373	1			T1	10		T4	4		T7	30
valid_sources[0x14]	95406	1			T1	8		T2	1		T4	8
valid_sources[0x15]	83854	1			T1	18		T2	11		T4	5
valid_sources[0x16]	86474	1			T1	12		T2	5		T4	7
valid_sources[0x17]	85585	1			T1	22		T2	4		T4	5
valid_sources[0x18]	84674	1			T1	10		T2	2		T4	4
valid_sources[0x19]	89857	1			T1	17		T2	14		T4	9
valid_sources[0x1a]	84847	1			T1	22		T2	8		T4	3
valid_sources[0x1b]	102540	1			T1	17		T2	10		T4	7
valid_sources[0x1c]	88955	1			T1	23		T2	8		T4	2
valid_sources[0x1d]	87336	1			T1	18		T2	11		T4	8
valid_sources[0x1e]	97527	1			T1	17		T2	17		T4	4
valid_sources[0x1f]	89947	1			T1	18		T2	4		T4	4
valid_sources[0x20]	94126	1			T1	13		T2	5		T4	9
valid_sources[0x21]	85337	1			T1	18		T2	9		T4	3
valid_sources[0x22]	82742	1			T1	13		T2	2		T4	2
valid_sources[0x23]	92545	1			T1	12		T4	4		T7	22
valid_sources[0x24]	93603	1			T1	12		T2	7		T4	3
valid_sources[0x25]	85930	1			T1	14		T2	10		T4	4
valid_sources[0x26]	89047	1			T1	16		T2	4		T4	7
valid_sources[0x27]	84813	1			T1	20		T2	3		T4	4
valid_sources[0x28]	88572	1			T1	13		T2	5		T4	2
valid_sources[0x29]	90929	1			T1	18		T2	6		T4	2
valid_sources[0x2a]	87967	1			T1	13		T2	2		T4	5
valid_sources[0x2b]	87344	1			T1	13		T2	7		T4	3
valid_sources[0x2c]	102586	1			T1	17		T2	8		T4	5
valid_sources[0x2d]	84894	1			T1	14		T2	2		T4	5
valid_sources[0x2e]	84473	1			T1	12		T2	13		T4	3
valid_sources[0x2f]	85503	1			T1	11		T2	9		T4	3
valid_sources[0x30]	91135	1			T1	22		T2	5		T4	3
valid_sources[0x31]	94527	1			T1	14		T2	6		T4	3
valid_sources[0x32]	86859	1			T1	9		T2	14		T4	4
valid_sources[0x33]	86847	1			T1	18		T2	12		T4	5
valid_sources[0x34]	86951	1			T1	11		T2	5		T4	4
valid_sources[0x35]	96429	1			T1	15		T2	8		T4	6
valid_sources[0x36]	107136	1			T1	14		T2	24		T4	1
valid_sources[0x37]	83919	1			T1	15		T2	2		T7	18
valid_sources[0x38]	85811	1			T1	17		T2	7		T4	5
valid_sources[0x39]	83770	1			T1	15		T2	16		T4	9
valid_sources[0x3a]	99337	1			T1	12		T2	5		T4	4
valid_sources[0x3b]	87061	1			T1	14		T2	7		T4	5
valid_sources[0x3c]	88696	1			T1	9		T2	2		T4	3
valid_sources[0x3d]	85708	1			T1	12		T2	9		T4	3
valid_sources[0x3e]	86999	1			T1	12		T2	13		T4	5
valid_sources[0x3f]	85984	1			T1	15		T2	7		T4	10
valid_sources[0x40]	85531	1			T1	15		T2	8		T4	2
valid_sources[0x41]	98373	1			T1	8		T2	9		T4	5
valid_sources[0x42]	86100	1			T1	17		T2	3		T4	4
valid_sources[0x43]	85387	1			T1	17		T2	16		T4	4
valid_sources[0x44]	83928	1			T1	17		T2	14		T4	4
valid_sources[0x45]	88566	1			T1	8		T2	4		T4	8
valid_sources[0x46]	88760	1			T1	8		T2	10		T4	5
valid_sources[0x47]	90300	1			T1	17		T2	13		T4	5
valid_sources[0x48]	95995	1			T1	13		T2	17		T4	5
valid_sources[0x49]	85556	1			T1	14		T2	11		T4	8
valid_sources[0x4a]	95491	1			T1	18		T2	6		T4	4
valid_sources[0x4b]	149928	1			T1	11		T2	13		T4	5
valid_sources[0x4c]	87998	1			T1	16		T2	1		T4	1
valid_sources[0x4d]	83474	1			T1	13		T2	3		T4	2
valid_sources[0x4e]	83235	1			T1	9		T2	2		T4	2
valid_sources[0x4f]	83747	1			T1	12		T4	6		T7	21
valid_sources[0x50]	89148	1			T1	19		T2	12		T4	4
valid_sources[0x51]	108607	1			T1	13		T2	4		T4	1
valid_sources[0x52]	90078	1			T1	13		T2	11		T4	2
valid_sources[0x53]	91085	1			T1	17		T2	6		T4	4
valid_sources[0x54]	87137	1			T1	14		T2	23		T4	3
valid_sources[0x55]	100861	1			T1	16		T2	6		T4	5
valid_sources[0x56]	84575	1			T1	18		T2	15		T4	7
valid_sources[0x57]	100738	1			T1	20		T2	17		T4	5
valid_sources[0x58]	88804	1			T1	11		T2	6		T4	4
valid_sources[0x59]	82818	1			T1	15		T2	13		T4	10
valid_sources[0x5a]	106833	1			T1	18		T2	7		T4	7
valid_sources[0x5b]	85967	1			T1	17		T2	13		T4	5
valid_sources[0x5c]	89915	1			T1	19		T2	9		T4	4
valid_sources[0x5d]	81526	1			T1	16		T2	12		T4	4
valid_sources[0x5e]	86062	1			T1	9		T2	4		T4	9
valid_sources[0x5f]	86525	1			T1	13		T2	14		T4	5
valid_sources[0x60]	94968	1			T1	21		T2	10		T4	7
valid_sources[0x61]	92068	1			T1	17		T2	16		T4	2
valid_sources[0x62]	90151	1			T1	15		T2	8		T4	7
valid_sources[0x63]	87405	1			T1	10		T2	3		T4	13
valid_sources[0x64]	82552	1			T1	15		T2	8		T4	5
valid_sources[0x65]	86270	1			T1	15		T2	14		T4	9
valid_sources[0x66]	86974	1			T1	14		T2	2		T4	2
valid_sources[0x67]	85888	1			T1	13		T2	7		T4	5
valid_sources[0x68]	89405	1			T1	14		T2	7		T4	10
valid_sources[0x69]	177063	1			T1	16		T2	7		T4	6
valid_sources[0x6a]	84341	1			T1	17		T2	7		T4	10
valid_sources[0x6b]	88060	1			T1	16		T4	3		T7	21
valid_sources[0x6c]	87232	1			T1	12		T2	16		T4	6
valid_sources[0x6d]	84990	1			T1	14		T2	16		T4	4
valid_sources[0x6e]	81573	1			T1	15		T2	10		T4	8
valid_sources[0x6f]	82962	1			T1	18		T2	7		T4	3
valid_sources[0x70]	89450	1			T1	9		T2	5		T4	7
valid_sources[0x71]	85574	1			T1	13		T2	20		T4	5
valid_sources[0x72]	85521	1			T1	7		T2	19		T4	6
valid_sources[0x73]	85873	1			T1	12		T2	18		T4	6
valid_sources[0x74]	85388	1			T1	16		T2	11		T4	3
valid_sources[0x75]	83463	1			T1	15		T2	11		T4	5
valid_sources[0x76]	89479	1			T1	14		T2	10		T4	10
valid_sources[0x77]	86925	1			T1	14		T2	7		T4	2
valid_sources[0x78]	88680	1			T1	9		T2	2		T4	5
valid_sources[0x79]	82679	1			T1	16		T2	14		T4	4
valid_sources[0x7a]	89271	1			T1	11		T2	6		T4	2
valid_sources[0x7b]	88859	1			T1	25		T2	3		T4	7
valid_sources[0x7c]	86411	1			T1	16		T2	8		T4	6
valid_sources[0x7d]	89659	1			T1	22		T2	5		T4	2
valid_sources[0x7e]	99152	1			T1	14		T2	4		T4	8
valid_sources[0x7f]	95181	1			T1	7		T2	8		T4	10
valid_sources[0x80]	103235	1			T1	9		T4	5		T7	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4926799

1

T1

1423

T2

388

T3

1321

values[0x0]

all_enables

biggest_size

4195427

1

T1

147

T2

21

T3

107

values[0x1]

all_enables

biggest_size

4110368

1

T1

112

T2

15

T3

51

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	579982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21034198

1

T1

20

T2

20

T3

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5311176	1			T1	10		T2	10		T3	90
values[0x0]	7912513	1			T1	5		T2	4		T3	56
values[0x1]	8390491	1			T1	5		T2	6		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21412293

1

T1

20

T2

20

T3

180

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	84045	1			T5	2135		T25	2		T11	1850
valid_sources[0x01]	83610	1			T5	2301		T117	1		T11	522
valid_sources[0x02]	86276	1			T5	2156		T9	1		T11	407
valid_sources[0x03]	85898	1			T5	2249		T11	1564		T12	1358
valid_sources[0x04]	86694	1			T5	2209		T118	1		T11	2192
valid_sources[0x05]	89752	1			T5	2197		T11	1339		T12	1366
valid_sources[0x06]	86022	1			T5	2230		T25	3		T119	40
valid_sources[0x07]	83998	1			T5	2182		T25	2		T11	210
valid_sources[0x08]	85256	1			T5	2205		T11	558		T12	1324
valid_sources[0x09]	84134	1			T5	2224		T115	9		T11	845
valid_sources[0x0a]	89484	1			T4	3		T5	2155		T11	3477
valid_sources[0x0b]	85974	1			T5	2285		T11	848		T12	1360
valid_sources[0x0c]	86577	1			T5	2237		T6	2		T11	182
valid_sources[0x0d]	85469	1			T5	2104		T12	1368		T15	1547
valid_sources[0x0e]	83016	1			T4	1		T5	2230		T11	330
valid_sources[0x0f]	83401	1			T5	2279		T11	795		T12	1394
valid_sources[0x10]	86578	1			T5	2258		T117	1		T118	1
valid_sources[0x11]	83348	1			T5	2145		T10	1		T25	1
valid_sources[0x12]	83113	1			T5	2306		T10	1		T11	782
valid_sources[0x13]	88984	1			T5	2160		T11	1450		T12	1404
valid_sources[0x14]	85804	1			T5	2274		T10	2		T25	2
valid_sources[0x15]	87444	1			T5	2136		T11	697		T12	1297
valid_sources[0x16]	83559	1			T5	2162		T11	833		T12	1260
valid_sources[0x17]	79982	1			T5	2170		T25	1		T11	347
valid_sources[0x18]	84889	1			T5	2269		T11	198		T12	1336
valid_sources[0x19]	84520	1			T4	1		T5	2063		T118	1
valid_sources[0x1a]	88095	1			T5	2132		T10	3		T25	3
valid_sources[0x1b]	80477	1			T5	2190		T10	2		T25	2
valid_sources[0x1c]	83784	1			T5	2292		T11	721		T12	1281
valid_sources[0x1d]	86145	1			T5	2185		T25	1		T117	1
valid_sources[0x1e]	84891	1			T5	2159		T118	1		T11	407
valid_sources[0x1f]	89722	1			T5	2221		T10	2		T117	1
valid_sources[0x20]	81855	1			T5	2249		T10	1		T117	1
valid_sources[0x21]	82161	1			T5	2284		T10	2		T11	723
valid_sources[0x22]	83607	1			T5	2187		T10	1		T11	1349
valid_sources[0x23]	82390	1			T5	2176		T12	1369		T15	1523
valid_sources[0x24]	87584	1			T5	2187		T11	1723		T12	1265
valid_sources[0x25]	80644	1			T5	2225		T10	3		T11	493
valid_sources[0x26]	84260	1			T5	2243		T117	1		T118	1
valid_sources[0x27]	86245	1			T5	2199		T11	820		T12	1360
valid_sources[0x28]	82078	1			T5	2267		T10	1		T11	692
valid_sources[0x29]	81329	1			T5	2271		T11	70		T12	1378
valid_sources[0x2a]	86143	1			T5	2141		T11	993		T12	1463
valid_sources[0x2b]	83982	1			T5	2200		T11	390		T12	1248
valid_sources[0x2c]	87660	1			T5	2232		T6	9		T11	71
valid_sources[0x2d]	84490	1			T5	2131		T118	1		T11	372
valid_sources[0x2e]	88305	1			T5	2170		T11	1291		T12	1296
valid_sources[0x2f]	80075	1			T5	2181		T11	1470		T12	1407
valid_sources[0x30]	85834	1			T5	2327		T118	2		T11	369
valid_sources[0x31]	82001	1			T5	2153		T11	1213		T12	1431
valid_sources[0x32]	84475	1			T5	2140		T12	1399		T15	1308
valid_sources[0x33]	87067	1			T5	2215		T25	1		T11	1076
valid_sources[0x34]	83486	1			T5	2312		T116	1		T11	715
valid_sources[0x35]	88122	1			T5	2181		T10	1		T25	2
valid_sources[0x36]	83690	1			T5	2188		T11	479		T12	1327
valid_sources[0x37]	83598	1			T5	2219		T11	1140		T12	1346
valid_sources[0x38]	83100	1			T5	2303		T25	6		T11	403
valid_sources[0x39]	88148	1			T5	2190		T11	1936		T12	1332
valid_sources[0x3a]	84616	1			T5	2283		T11	154		T12	1265
valid_sources[0x3b]	84696	1			T5	2179		T11	732		T12	1305
valid_sources[0x3c]	85161	1			T5	2328		T11	606		T12	1358
valid_sources[0x3d]	86026	1			T5	2256		T25	3		T11	780
valid_sources[0x3e]	88066	1			T5	2183		T11	752		T12	1358
valid_sources[0x3f]	82721	1			T5	2266		T11	433		T12	1361
valid_sources[0x40]	81092	1			T5	2164		T6	3		T11	477
valid_sources[0x41]	83399	1			T5	2173		T12	1464		T136	1
valid_sources[0x42]	90021	1			T5	2172		T11	1161		T12	1374
valid_sources[0x43]	82554	1			T5	2189		T10	2		T11	1278
valid_sources[0x44]	80706	1			T5	2173		T11	293		T12	1288
valid_sources[0x45]	84720	1			T1	3		T5	2254		T10	1
valid_sources[0x46]	84853	1			T5	2170		T25	2		T11	966
valid_sources[0x47]	82347	1			T5	2136		T25	8		T11	520
valid_sources[0x48]	80318	1			T5	2228		T11	304		T12	1275
valid_sources[0x49]	85918	1			T5	2282		T11	87		T12	1381
valid_sources[0x4a]	89322	1			T5	2134		T10	2		T25	3
valid_sources[0x4b]	87962	1			T5	2251		T11	582		T12	1387
valid_sources[0x4c]	88890	1			T5	2165		T11	66		T12	1372
valid_sources[0x4d]	84090	1			T5	2239		T11	484		T12	1273
valid_sources[0x4e]	83449	1			T5	2148		T11	1351		T12	1337
valid_sources[0x4f]	84128	1			T5	2226		T115	1		T118	1
valid_sources[0x50]	83658	1			T5	2230		T10	2		T11	522
valid_sources[0x51]	79704	1			T4	1		T5	2255		T11	449
valid_sources[0x52]	87124	1			T5	2146		T11	459		T12	1397
valid_sources[0x53]	84820	1			T5	2250		T10	1		T25	1
valid_sources[0x54]	77760	1			T5	2180		T11	308		T12	1341
valid_sources[0x55]	83753	1			T5	2185		T25	1		T11	271
valid_sources[0x56]	84517	1			T5	2145		T11	611		T12	1290
valid_sources[0x57]	84523	1			T5	2243		T11	604		T12	1313
valid_sources[0x58]	81174	1			T5	2136		T11	220		T12	1297
valid_sources[0x59]	85531	1			T5	2169		T11	1142		T12	1330
valid_sources[0x5a]	83045	1			T5	2139		T11	1430		T12	1376
valid_sources[0x5b]	85910	1			T5	2190		T10	1		T11	2250
valid_sources[0x5c]	83938	1			T5	2255		T11	47		T12	1363
valid_sources[0x5d]	84850	1			T5	2209		T10	1		T116	3
valid_sources[0x5e]	84865	1			T2	8		T5	2202		T10	1
valid_sources[0x5f]	81718	1			T5	2221		T12	1334		T15	1305
valid_sources[0x60]	85100	1			T5	2200		T25	1		T11	1421
valid_sources[0x61]	85632	1			T5	2272		T11	2234		T12	1375
valid_sources[0x62]	85273	1			T5	2296		T11	518		T12	1419
valid_sources[0x63]	83701	1			T5	2224		T115	2		T116	3
valid_sources[0x64]	86229	1			T5	2218		T11	2386		T12	1370
valid_sources[0x65]	88506	1			T5	2194		T25	3		T11	675
valid_sources[0x66]	83413	1			T5	2184		T10	5		T11	352
valid_sources[0x67]	81652	1			T5	2261		T10	1		T12	1300
valid_sources[0x68]	82304	1			T5	2244		T25	2		T11	79
valid_sources[0x69]	85115	1			T5	2323		T117	1		T11	235
valid_sources[0x6a]	81632	1			T5	2117		T25	1		T11	144
valid_sources[0x6b]	82234	1			T5	2161		T116	2		T11	329
valid_sources[0x6c]	84290	1			T1	3		T5	2212		T13	80
valid_sources[0x6d]	84854	1			T5	2150		T25	1		T11	284
valid_sources[0x6e]	83265	1			T5	2284		T25	3		T11	371
valid_sources[0x6f]	85959	1			T1	3		T5	2225		T11	318
valid_sources[0x70]	84397	1			T5	2202		T11	134		T12	1342
valid_sources[0x71]	84292	1			T5	2215		T118	1		T11	1321
valid_sources[0x72]	85171	1			T5	2228		T11	121		T12	1382
valid_sources[0x73]	80456	1			T5	2240		T25	4		T11	634
valid_sources[0x74]	81252	1			T5	2141		T11	219		T12	1389
valid_sources[0x75]	86728	1			T5	2296		T11	671		T12	1371
valid_sources[0x76]	85518	1			T5	2254		T25	1		T11	82
valid_sources[0x77]	85805	1			T5	2203		T12	1376		T136	1
valid_sources[0x78]	84572	1			T3	180		T5	2195		T25	2
valid_sources[0x79]	84159	1			T5	2135		T115	3		T11	946
valid_sources[0x7a]	83479	1			T5	2222		T11	944		T12	1356
valid_sources[0x7b]	88403	1			T5	2158		T10	1		T11	510
valid_sources[0x7c]	90823	1			T5	2176		T6	1		T10	1
valid_sources[0x7d]	86281	1			T5	2345		T11	1192		T12	1385
valid_sources[0x7e]	85646	1			T5	2264		T6	13		T11	110
valid_sources[0x7f]	83266	1			T5	2182		T11	506		T12	1370
valid_sources[0x80]	88229	1			T5	2209		T25	1		T11	1552

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5297503

1

T1

10

T2

10

T3

90

values[0x0]

all_enables

biggest_size

7872069

1

T1

5

T2

4

T3

56

values[0x1]

all_enables

biggest_size

7864626

1

T1

5

T2

6

T3

34