Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

53335208

1

T1

1998

T2

1715

T3

1698

full_word

15868598

1

T1

1682

T2

424

T3

1479

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69203496	1			T1	3680		T2	2139		T3	3177
auto[TlIntgErrCmd]	91	1			T282	4		T283	1		T284	3
auto[TlIntgErrData]	102	1			T282	8		T283	5		T284	3
auto[TlIntgErrBoth]	117	1			T282	8		T283	4		T284	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13277290

1

T1

3093

T2

2032

T3

2830

auto[1]

55926516

1

T1

587

T2

107

T3

347

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8028898	1			T1	1670		T2	1644		T3	1509
auto[TlIntgErrNone]	partial	auto[1]	45306033	1			T1	328		T2	71		T3	189
auto[TlIntgErrNone]	full_word	auto[0]	5248254	1			T1	1423		T2	388		T3	1321
auto[TlIntgErrNone]	full_word	auto[1]	10620311	1			T1	259		T2	36		T3	158
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T282	1		T283	1		T284	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T282	3		T284	1		T288	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T362	1		T357	1		T363	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T355	1		T356	1		T286	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T282	4		T283	1		T284	1
auto[TlIntgErrData]	partial	auto[1]	44	1			T282	4		T283	2		T284	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T284	1		T288	1		T358	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T283	2		T355	1		T364	3
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T282	6		T284	1		T288	6
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T282	1		T283	4		T284	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T360	1		T359	1		T286	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T282	1		T288	1		T354	1