Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50219593

1

T1

7737

T2

1256

T3

2189

full_word

14951815

1

T1

3658

T2

490

T3

535

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65171128	1			T1	11395		T2	1746		T3	2724
auto[TlIntgErrCmd]	96	1			T264	7		T265	3		T266	3
auto[TlIntgErrData]	100	1			T264	2		T265	5		T266	4
auto[TlIntgErrBoth]	84	1			T264	1		T265	2		T266	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12218804

1

T1

9982

T2

1609

T3

2548

auto[1]

52952604

1

T1

1413

T2

137

T3

176

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7305133	1			T1	6890		T2	1181		T3	2103
auto[TlIntgErrNone]	partial	auto[1]	42914207	1			T1	847		T2	75		T3	86
auto[TlIntgErrNone]	full_word	auto[0]	4913539	1			T1	3092		T2	428		T3	445
auto[TlIntgErrNone]	full_word	auto[1]	10038249	1			T1	566		T2	62		T3	90
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T264	4		T265	1		T266	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T264	2		T265	2		T266	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T270	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T264	1		T345	1		T342	2
auto[TlIntgErrData]	partial	auto[0]	50	1			T264	1		T265	2		T266	4
auto[TlIntgErrData]	partial	auto[1]	41	1			T264	1		T265	3		T271	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T270	1		T346	1		T347	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T341	1		T348	1		T349	2
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T265	1		T266	1		T270	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T264	1		T266	2		T271	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T265	1		T346	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T341	1		T343	1		T344	1