Unified Coverage Report :: Module :: otp_ctrl_ecc_reg

Module : otp_ctrl_ecc_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	100.00		97.87		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.64	92.39	93.55		72.00	89.13	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	100.00		97.87		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.01	100.00	97.06		88.00	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	100.00		97.87		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.01	100.00	97.06		88.00	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	100.00		97.87		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.35	100.00	97.06		64.71	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	100.00		97.87		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.35	100.00	97.06		64.71	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.83	100.00		95.33		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
74.42	78.75	81.25		58.33	71.43	82.35	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.45	100.00		93.79		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.75	79.38	85.42		69.44	77.14	82.35	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.56	100.00		94.23		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.57	91.88	86.54		70.21	84.93	94.29	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.42	100.00		93.69		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.57	91.88	86.54		70.21	84.93	94.29	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.42	100.00		93.69		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.99	91.88	86.54		72.34	84.93	94.29	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.42	100.00		69.69		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
67.73	71.76	75.00		40.43	69.64	81.82	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	69.86			69.86
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	70.55			70.55
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	72.60			72.60
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	64.38			64.38
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	65.75			65.75
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	72.60			72.60
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	69.86			69.86
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	63.70			63.70
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	64.38			64.38
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	58.90			58.90
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	65.75			65.75
u_prim_secded_inv_72_64_enc	100.00			100.00

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=9,Aw=4,EccWidth=8 + Width=64,Depth=2,Aw=1,EccWidth=8 + Width=64,Depth=5,Aw=3,EccWidth=8 + Width=64,Depth=11,Aw=4,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=1,Aw=1,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Module : otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T28,T30,T242

---

Assert Coverage for Module : otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
RDataOutKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	12397	12397	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2059860	2025089	0	0
T2	131065	128953	0	0
T3	143792	134695	0	0
T4	493086	485672	0	0
T9	917719	915068	0	0
T10	122892	119592	0	0
T11	53328	52745	0	0
T12	165594	162272	0	0
T13	158323	154671	0	0
T14	132891	129877	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2059860	2025089	0	0
T2	131065	128953	0	0
T3	143792	134695	0	0
T4	493086	485672	0	0
T9	917719	915068	0	0
T10	122892	119592	0	0
T11	53328	52745	0	0
T12	165594	162272	0	0
T13	158323	154671	0	0
T14	132891	129877	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2059860	2025089	0	0
T2	131065	128953	0	0
T3	143792	134695	0	0
T4	493086	485672	0	0
T9	917719	915068	0	0
T10	122892	119592	0	0
T11	53328	52745	0	0
T12	165594	162272	0	0
T13	158323	154671	0	0
T14	132891	129877	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2059860	2025089	0	0
T2	131065	128953	0	0
T3	143792	134695	0	0
T4	493086	485672	0	0
T9	917719	915068	0	0
T10	122892	119592	0	0
T11	53328	52745	0	0
T12	165594	162272	0	0
T13	158323	154671	0	0
T14	132891	129877	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2059860	2025089	0	0
T2	131065	128953	0	0
T3	143792	134695	0	0
T4	493086	485672	0	0
T9	917719	915068	0	0
T10	122892	119592	0	0
T11	53328	52745	0	0
T12	165594	162272	0	0
T13	158323	154671	0	0
T14	132891	129877	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12397	12397	0	0
T1	11	11	0	0
T2	11	11	0	0
T3	11	11	0	0
T4	11	11	0	0
T9	11	11	0	0
T10	11	11	0	0
T11	11	11	0	0
T12	11	11	0	0
T13	11	11	0	0
T14	11	11	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T28,T30,T242

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T28,T30,T242

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T28,T30,T242

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T28,T30,T242

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T28,T30,T242

---

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1584582250	1583735421	0	0
DataOutKnown_A	1584582250	1583735421	0	0
EccErrKnown_A	1584582250	1583735421	0	0
EccKnown_A	1584582250	1583735421	0	0
RDataOutKnown_A	1584582250	1583735421	0	0
WidthMustBe64bit_A	1127	1127	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584582250	1583735421	0	0
T1	187260	184099	0	0
T2	11915	11723	0	0
T3	13072	12245	0	0
T4	44826	44152	0	0
T9	83429	83188	0	0
T10	11172	10872	0	0
T11	4848	4795	0	0
T12	15054	14752	0	0
T13	14393	14061	0	0
T14	12081	11807	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127	1127	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0