Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_prog_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_prog_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_lc_esc	2	0	2	100.00	100	1	1	0
lc_prog_req_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_prog_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_prog_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24130

1

T1

57

T3

102

T4

2

auto[1]

748

1

T1

5

T6

9

T101

1

---

Summary for Variable lc_prog_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23982

1

T1

59

T3

101

T4

2

auto[1]

896

1

T1

3

T3

1

T47

1

---

Summary for Variable lc_prog_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lc_prog_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

24843

1

T1

62

T3

102

T4

2

lc_esc_on

35

1

T6

1

T204

1

T261

1

---

Summary for Variable lc_prog_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23228

1

T1

61

T3

101

T4

2

auto[1]

1650

1

T1

1

T3

1

T12

1

---

Summary for Variable lc_prog_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13374

1

T1

41

T3

53

T4

1

auto[1]

11504

1

T1

21

T3

49

T4

1

---

Summary for Variable lc_prog_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23204

1

T1

55

T3

101

T4

2

auto[1]

1674

1

T1

7

T3

1

T47

2

---

Summary for Variable lc_prog_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_prog_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23259

1

T1

58

T3

102

T4

2

auto[1]

1619

1

T1

4

T47

2

T6

11