Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.56	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	12	60	83.33

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	12	60	83.33	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	51531	1			T3	1025		T8	220		T61	19
access_err	58900	1			T1	4		T3	629		T5	17
write_blank_err	367	1			T5	2		T6	17		T135	4
ecc_uncorr_err	59864	1			T5	273		T6	1726		T135	459
ecc_corr_err	1265	1			T6	1		T64	6		T60	4
no_err	84530	1			T1	8		T3	768		T4	25

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	949	1			T5	2		T6	15		T15	12
secret2	21779	1			T1	2		T3	136		T4	3
secret1	25185	1			T1	1		T3	135		T12	12
secret0	34093	1			T3	134		T12	20		T5	276
hw_cfg1	32750	1			T3	576		T4	4		T12	5
hw_cfg0	22910	1			T3	133		T4	7		T12	12
rot_creator_auth_state	22250	1			T1	2		T3	129		T4	3
rot_creator_auth_codesign	19346	1			T3	143		T12	14		T5	13
owner_sw_cfg	21334	1			T1	1		T3	539		T4	4
creator_sw_cfg	20358	1			T1	2		T3	179		T4	2
vendor_test	35503	1			T1	4		T3	318		T4	2

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	12	60	83.33	12
Automatically Generated Cross Bins	72	12	60	83.33	12
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	life_cycle	319	1			T155	319		-	-		-	-
fsm_err	secret2	1204	1			T154	176		T338	264		T339	8
fsm_err	secret1	4978	1			T61	19		T89	603		T139	1034
fsm_err	secret0	5091	1			T205	195		T103	389		T14	167
fsm_err	hw_cfg1	4042	1			T3	448		T6	147		T33	193
fsm_err	hw_cfg0	2819	1			T340	243		T14	93		T144	154
fsm_err	rot_creator_auth_state	4263	1			T8	220		T250	155		T341	346
fsm_err	rot_creator_auth_codesign	1981	1			T144	103		T342	28		T157	24
fsm_err	owner_sw_cfg	4625	1			T3	407		T343	31		T261	1
fsm_err	creator_sw_cfg	3204	1			T344	61		T249	305		T169	6
fsm_err	vendor_test	19005	1			T3	170		T64	62		T106	119
access_err	life_cycle	630	1			T5	2		T6	15		T15	12
access_err	secret2	10232	1			T1	1		T3	96		T6	176
access_err	secret1	6095	1			T3	53		T6	209		T64	1
access_err	secret0	4656	1			T3	92		T6	140		T7	2
access_err	hw_cfg1	1286	1			T3	21		T5	1		T6	23
access_err	hw_cfg0	2246	1			T3	21		T6	43		T64	3
access_err	rot_creator_auth_state	5606	1			T3	49		T5	3		T6	108
access_err	rot_creator_auth_codesign	7234	1			T3	69		T5	4		T6	131
access_err	owner_sw_cfg	6399	1			T3	74		T6	159		T7	35
access_err	creator_sw_cfg	7575	1			T1	1		T3	89		T5	6
access_err	vendor_test	6941	1			T1	2		T3	65		T5	1
write_blank_err	secret2	12	1			T6	2		T163	1		T247	2
write_blank_err	secret1	14	1			T6	1		T139	1		T275	1
write_blank_err	secret0	40	1			T5	1		T6	1		T135	1
write_blank_err	hw_cfg1	67	1			T6	1		T103	1		T17	1
write_blank_err	hw_cfg0	17	1			T103	1		T333	1		T236	1
write_blank_err	rot_creator_auth_state	117	1			T5	1		T6	7		T135	1
write_blank_err	rot_creator_auth_codesign	32	1			T6	4		T135	2		T17	2
write_blank_err	owner_sw_cfg	33	1			T236	2		T336	1		T279	1
write_blank_err	creator_sw_cfg	12	1			T92	1		T17	1		T333	2
write_blank_err	vendor_test	23	1			T6	1		T103	1		T17	1
ecc_uncorr_err	secret2	5094	1			T6	850		T161	51		T163	444
ecc_uncorr_err	secret1	5911	1			T6	591		T161	51		T139	198
ecc_uncorr_err	secret0	16481	1			T5	273		T6	285		T135	459
ecc_uncorr_err	hw_cfg1	17340	1			T345	261		T238	136		T170	70
ecc_uncorr_err	hw_cfg0	6373	1			T103	389		T333	506		T236	347
ecc_uncorr_err	rot_creator_auth_state	4058	1			T15	465		T346	58		T220	38
ecc_uncorr_err	rot_creator_auth_codesign	1666	1			T91	65		T347	63		T157	31
ecc_uncorr_err	owner_sw_cfg	1387	1			T170	128		T157	38		T156	444
ecc_uncorr_err	creator_sw_cfg	1554	1			T161	45		T91	62		T170	131
ecc_corr_err	secret2	66	1			T60	1		T69	1		T286	3
ecc_corr_err	secret1	140	1			T58	1		T169	1		T286	3
ecc_corr_err	secret0	132	1			T64	1		T58	3		T71	4
ecc_corr_err	hw_cfg1	242	1			T6	1		T58	8		T71	9
ecc_corr_err	hw_cfg0	202	1			T64	2		T58	5		T42	1
ecc_corr_err	rot_creator_auth_state	117	1			T64	1		T60	3		T161	1
ecc_corr_err	rot_creator_auth_codesign	121	1			T64	1		T71	2		T50	3
ecc_corr_err	owner_sw_cfg	118	1			T58	2		T71	8		T69	1
ecc_corr_err	creator_sw_cfg	127	1			T64	1		T58	4		T42	6
no_err	secret2	5171	1			T1	1		T3	40		T4	3
no_err	secret1	8047	1			T1	1		T3	82		T12	12
no_err	secret0	7693	1			T3	42		T12	20		T5	2
no_err	hw_cfg1	9773	1			T3	107		T4	4		T12	5
no_err	hw_cfg0	11253	1			T3	112		T4	7		T12	12
no_err	rot_creator_auth_state	8089	1			T1	2		T3	80		T4	3
no_err	rot_creator_auth_codesign	8312	1			T3	74		T12	14		T5	9
no_err	owner_sw_cfg	8772	1			T1	1		T3	58		T4	4
no_err	creator_sw_cfg	7886	1			T1	1		T3	90		T4	2
no_err	vendor_test	9534	1			T1	2		T3	83		T4	2

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded