Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50073668

1

T1

4978

T2

531

T3

490

full_word

14919465

1

T1

2657

T2

421

T3

481

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	64992833	1			T1	7635		T2	952		T3	971
auto[TlIntgErrCmd]	95	1			T272	2		T274	9		T278	10
auto[TlIntgErrData]	97	1			T272	4		T273	5		T274	4
auto[TlIntgErrBoth]	108	1			T272	4		T273	5		T274	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12194559

1

T1

6810

T2

801

T3

843

auto[1]

52798574

1

T1

825

T2

151

T3

128

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7280506	1			T1	4515		T2	451		T3	422
auto[TlIntgErrNone]	partial	auto[1]	42792891	1			T1	463		T2	80		T3	68
auto[TlIntgErrNone]	full_word	auto[0]	4913913	1			T1	2295		T2	350		T3	421
auto[TlIntgErrNone]	full_word	auto[1]	10005523	1			T1	362		T2	71		T3	60
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T272	1		T274	5		T278	3
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T272	1		T274	3		T278	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T274	1		T279	1		T359	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T276	1		T360	1		T365	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T273	3		T278	2		T279	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T272	3		T273	1		T274	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T272	1		T277	1		T366	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T273	1		T274	1		T276	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T272	2		T273	1		T274	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T272	2		T273	3		T274	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T273	1		T274	1		T276	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T363	1		T360	2		T367	2