Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[CreatorSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[OwnerSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthStateIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[VendorTestIdx]	100.00	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[CreatorSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OwnerSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[VendorTestIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

23921

1

T1

8

T2

6

T4

12

write_op

5881

1

T1

3

T2

3

T4

3

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11285

1

T1

11

T2

9

T4

15

auto[1]

18517

1

T12

16

T6

181

T7

22

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21666

1

T1

11

T2

9

T4

15

auto[1]

8136

1

T6

175

T21

25

T90

27

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5010	1			T1	8		T2	6		T4	12
auto[0]	auto[0]	write_op	2809	1			T1	3		T2	3		T4	3
auto[0]	auto[1]	read_op	2584	1			T6	62		T21	13		T90	9
auto[0]	auto[1]	write_op	882	1			T6	22		T21	3		T90	2
auto[1]	auto[0]	read_op	12383	1			T12	16		T6	74		T7	22
auto[1]	auto[0]	write_op	1464	1			T6	16		T21	3		T34	13
auto[1]	auto[1]	read_op	3944	1			T6	75		T21	9		T90	14
auto[1]	auto[1]	write_op	726	1			T6	16		T90	2		T34	19

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

24815

1

T1

8

T2

4

T4

10

write_op

5639

1

T1

3

T2

2

T4

4

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11055

1

T1

11

T2

6

T4

14

auto[1]

19399

1

T12

4

T6

185

T7

28

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24995

1

T1

11

T2

6

T4

14

auto[1]

5459

1

T6

124

T22

1

T34

135

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	6043	1			T1	8		T2	4		T4	10
auto[0]	auto[0]	write_op	2935	1			T1	3		T2	2		T4	4
auto[0]	auto[1]	read_op	1567	1			T6	30		T22	1		T34	26
auto[0]	auto[1]	write_op	510	1			T6	9		T34	8		T60	1
auto[1]	auto[0]	read_op	14385	1			T12	4		T6	78		T7	28
auto[1]	auto[0]	write_op	1632	1			T6	22		T8	2		T21	1
auto[1]	auto[1]	read_op	2820	1			T6	68		T34	76		T60	19
auto[1]	auto[1]	write_op	562	1			T6	17		T34	25		T60	3

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

24560

1

T2

4

T4

4

T5

11

write_op

5911

1

T2

2

T4

2

T5

3

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11039

1

T2

6

T4

6

T5

14

auto[1]

19432

1

T12

6

T6

184

T7

25

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22081

1

T2

6

T4

6

T5

14

auto[1]

8390

1

T6

201

T21

33

T22

2

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5009	1			T2	4		T4	4		T5	11
auto[0]	auto[0]	write_op	2783	1			T2	2		T4	2		T5	3
auto[0]	auto[1]	read_op	2423	1			T6	59		T21	15		T90	4
auto[0]	auto[1]	write_op	824	1			T6	26		T21	4		T34	11
auto[1]	auto[0]	read_op	12816	1			T12	6		T6	56		T7	25
auto[1]	auto[0]	write_op	1473	1			T6	12		T34	13		T60	1
auto[1]	auto[1]	read_op	4312	1			T6	97		T21	11		T22	2
auto[1]	auto[1]	write_op	831	1			T6	19		T21	3		T90	2

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

23387

1

T1

6

T2

4

T4

10

write_op

4258

1

T1

3

T2

1

T4

3

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10108

1

T1

9

T2

5

T4

13

auto[1]

17537

1

T12

2

T6

191

T7

20

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24515

1

T1

9

T2

5

T4

13

auto[1]

3130

1

T6

44

T21

14

T90

22

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	6360	1			T1	6		T2	4		T4	10
auto[0]	auto[0]	write_op	2506	1			T1	3		T2	1		T4	3
auto[0]	auto[1]	read_op	1002	1			T6	10		T21	10		T90	4
auto[0]	auto[1]	write_op	240	1			T6	1		T21	3		T34	3
auto[1]	auto[0]	read_op	14351	1			T12	2		T6	143		T7	20
auto[1]	auto[0]	write_op	1298	1			T6	15		T8	2		T21	3
auto[1]	auto[1]	read_op	1674	1			T6	29		T21	1		T90	16
auto[1]	auto[1]	write_op	214	1			T6	4		T90	2		T34	4

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

23542

1

T1

8

T2

4

T4

14

write_op

5244

1

T1

4

T2

2

T4

6

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10709

1

T1

12

T2

6

T4

20

auto[1]

18077

1

T12

4

T6

249

T7

28

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20710

1

T1

12

T2

6

T4

20

auto[1]

8076

1

T6

234

T21

22

T90

5

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	4900	1			T1	8		T2	4		T4	14
auto[0]	auto[0]	write_op	2613	1			T1	4		T2	2		T4	6
auto[0]	auto[1]	read_op	2490	1			T6	49		T21	9		T34	46
auto[0]	auto[1]	write_op	706	1			T6	10		T21	3		T90	1
auto[1]	auto[0]	read_op	11928	1			T12	4		T6	63		T7	28
auto[1]	auto[0]	write_op	1269	1			T6	11		T8	1		T21	3
auto[1]	auto[1]	read_op	4224	1			T6	147		T21	8		T90	4
auto[1]	auto[1]	write_op	656	1			T6	28		T21	2		T34	16