Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8199651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10702274

1

T1

184

T2

156

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8592866	1			T1	746		T2	289		T3	1
values[0x0]	3792506	1			T1	107		T2	90		T3	12
values[0x1]	6516553	1			T1	107		T2	89		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4815457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14086468

1

T1

416

T2

232

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	65957	1			T1	3		T5	8		T10	3
valid_sources[0x01]	70054	1			T1	2		T2	12		T5	10
valid_sources[0x02]	66204	1			T1	3		T2	7		T5	20
valid_sources[0x03]	68660	1			T5	11		T10	3		T11	11
valid_sources[0x04]	67817	1			T1	7		T5	9		T12	10
valid_sources[0x05]	74233	1			T1	1		T5	9		T10	3
valid_sources[0x06]	65944	1			T1	2		T5	9		T10	2
valid_sources[0x07]	64269	1			T1	4		T2	3		T5	13
valid_sources[0x08]	79144	1			T1	4		T5	5		T10	1
valid_sources[0x09]	77810	1			T5	11		T11	5		T12	6
valid_sources[0x0a]	69424	1			T1	6		T5	13		T12	12
valid_sources[0x0b]	86579	1			T1	1		T5	16		T10	8
valid_sources[0x0c]	78455	1			T1	3		T5	11		T10	2
valid_sources[0x0d]	68918	1			T1	2		T5	15		T10	1
valid_sources[0x0e]	69080	1			T5	12		T11	23		T12	4
valid_sources[0x0f]	103730	1			T1	6		T5	14		T12	13
valid_sources[0x10]	71856	1			T1	1		T5	9		T12	10
valid_sources[0x11]	74853	1			T1	1		T5	9		T10	2
valid_sources[0x12]	68445	1			T1	1		T5	11		T10	1
valid_sources[0x13]	76451	1			T1	2		T5	11		T12	10
valid_sources[0x14]	66197	1			T1	5		T5	12		T11	3
valid_sources[0x15]	78509	1			T1	4		T3	1		T5	23
valid_sources[0x16]	65816	1			T1	1		T5	13		T10	2
valid_sources[0x17]	71579	1			T1	1		T5	14		T10	9
valid_sources[0x18]	75052	1			T1	3		T5	14		T11	1
valid_sources[0x19]	68153	1			T1	2		T2	13		T5	15
valid_sources[0x1a]	83706	1			T1	4		T5	18		T11	15
valid_sources[0x1b]	72425	1			T1	1		T5	14		T10	13
valid_sources[0x1c]	67081	1			T1	14		T2	27		T5	13
valid_sources[0x1d]	68290	1			T1	3		T5	7		T11	3
valid_sources[0x1e]	67088	1			T1	4		T5	11		T10	7
valid_sources[0x1f]	71369	1			T1	3		T5	12		T10	9
valid_sources[0x20]	132974	1			T1	2		T5	12		T10	3
valid_sources[0x21]	72295	1			T1	5		T2	1		T5	8
valid_sources[0x22]	76615	1			T1	3		T5	16		T10	3
valid_sources[0x23]	65182	1			T1	7		T5	13		T10	12
valid_sources[0x24]	73451	1			T1	2		T5	16		T10	8
valid_sources[0x25]	67193	1			T2	3		T5	13		T10	1
valid_sources[0x26]	65532	1			T1	11		T5	10		T10	3
valid_sources[0x27]	75130	1			T1	2		T5	16		T10	10
valid_sources[0x28]	64575	1			T1	4		T2	1		T5	15
valid_sources[0x29]	69073	1			T5	22		T10	2		T11	1
valid_sources[0x2a]	75916	1			T1	17		T5	17		T10	5
valid_sources[0x2b]	67343	1			T1	1		T5	16		T10	3
valid_sources[0x2c]	76026	1			T3	1		T5	6		T10	3
valid_sources[0x2d]	70274	1			T1	6		T2	11		T5	10
valid_sources[0x2e]	169603	1			T1	3		T2	2		T5	11
valid_sources[0x2f]	66541	1			T1	10		T5	14		T12	9
valid_sources[0x30]	71887	1			T1	11		T5	19		T12	7
valid_sources[0x31]	90653	1			T1	1		T2	15		T5	9
valid_sources[0x32]	78524	1			T1	4		T2	2		T5	14
valid_sources[0x33]	64738	1			T1	2		T2	9		T5	17
valid_sources[0x34]	72468	1			T1	1		T2	8		T5	14
valid_sources[0x35]	67845	1			T1	5		T2	19		T5	12
valid_sources[0x36]	66773	1			T1	1		T5	8		T12	4
valid_sources[0x37]	113878	1			T1	1		T2	8		T5	14
valid_sources[0x38]	64949	1			T1	3		T5	9		T10	1
valid_sources[0x39]	67342	1			T1	7		T5	18		T10	1
valid_sources[0x3a]	66148	1			T1	6		T2	16		T5	11
valid_sources[0x3b]	67046	1			T5	7		T11	17		T12	7
valid_sources[0x3c]	67918	1			T1	11		T5	14		T12	1
valid_sources[0x3d]	73701	1			T1	3		T2	5		T5	5
valid_sources[0x3e]	72120	1			T1	6		T5	17		T10	2
valid_sources[0x3f]	67256	1			T1	5		T5	14		T11	1
valid_sources[0x40]	70781	1			T1	8		T5	6		T10	2
valid_sources[0x41]	74379	1			T1	1		T5	13		T11	2
valid_sources[0x42]	76041	1			T1	5		T5	8		T10	3
valid_sources[0x43]	67087	1			T1	2		T5	12		T10	3
valid_sources[0x44]	69669	1			T1	10		T2	6		T3	1
valid_sources[0x45]	65489	1			T1	2		T2	8		T5	21
valid_sources[0x46]	63989	1			T1	2		T5	16		T10	4
valid_sources[0x47]	79229	1			T1	2		T5	8		T10	1
valid_sources[0x48]	67379	1			T1	5		T5	12		T12	7
valid_sources[0x49]	74065	1			T1	2		T5	13		T10	4
valid_sources[0x4a]	66109	1			T1	3		T5	15		T12	6
valid_sources[0x4b]	67104	1			T1	1		T5	13		T10	4
valid_sources[0x4c]	71092	1			T1	5		T5	12		T12	2
valid_sources[0x4d]	70806	1			T1	1		T5	9		T12	10
valid_sources[0x4e]	72085	1			T1	4		T5	6		T10	7
valid_sources[0x4f]	74474	1			T1	5		T5	13		T10	4
valid_sources[0x50]	76624	1			T1	5		T3	1		T5	16
valid_sources[0x51]	65624	1			T1	1		T5	15		T10	4
valid_sources[0x52]	66010	1			T1	3		T5	14		T12	12
valid_sources[0x53]	67373	1			T1	1		T2	3		T5	8
valid_sources[0x54]	66909	1			T1	5		T5	7		T10	1
valid_sources[0x55]	65242	1			T1	2		T5	14		T10	4
valid_sources[0x56]	87825	1			T5	11		T10	3		T12	7
valid_sources[0x57]	68680	1			T1	7		T5	16		T10	5
valid_sources[0x58]	66176	1			T1	1		T5	9		T10	3
valid_sources[0x59]	67580	1			T1	3		T5	8		T11	2
valid_sources[0x5a]	72505	1			T4	1012		T5	13		T10	2
valid_sources[0x5b]	65427	1			T1	4		T5	13		T11	15
valid_sources[0x5c]	71774	1			T1	1		T5	8		T10	4
valid_sources[0x5d]	68515	1			T2	3		T5	9		T11	5
valid_sources[0x5e]	68168	1			T5	12		T10	7		T12	8
valid_sources[0x5f]	68575	1			T1	8		T5	13		T10	8
valid_sources[0x60]	66922	1			T1	10		T5	7		T10	6
valid_sources[0x61]	69451	1			T1	4		T2	7		T3	1
valid_sources[0x62]	70775	1			T1	5		T2	2		T5	9
valid_sources[0x63]	68176	1			T2	14		T5	11		T10	2
valid_sources[0x64]	71017	1			T1	3		T2	4		T5	9
valid_sources[0x65]	65311	1			T1	1		T5	14		T10	8
valid_sources[0x66]	69420	1			T1	4		T5	13		T10	4
valid_sources[0x67]	73609	1			T1	6		T5	13		T10	9
valid_sources[0x68]	79886	1			T1	5		T5	10		T11	27
valid_sources[0x69]	133911	1			T1	5		T5	9		T10	2
valid_sources[0x6a]	70700	1			T1	9		T3	1		T5	9
valid_sources[0x6b]	71845	1			T1	4		T5	10		T10	1
valid_sources[0x6c]	68199	1			T5	13		T10	3		T12	3
valid_sources[0x6d]	68094	1			T1	4		T2	8		T5	12
valid_sources[0x6e]	66391	1			T1	2		T2	7		T5	12
valid_sources[0x6f]	66954	1			T1	2		T5	11		T10	6
valid_sources[0x70]	65857	1			T1	5		T2	13		T5	16
valid_sources[0x71]	71334	1			T1	2		T3	2		T5	17
valid_sources[0x72]	66538	1			T1	4		T5	14		T10	4
valid_sources[0x73]	72800	1			T1	4		T5	9		T10	1
valid_sources[0x74]	64507	1			T1	8		T3	1		T5	13
valid_sources[0x75]	69585	1			T1	6		T5	14		T10	6
valid_sources[0x76]	66622	1			T1	1		T5	13		T12	7
valid_sources[0x77]	68986	1			T1	6		T5	12		T10	8
valid_sources[0x78]	67219	1			T5	10		T10	8		T12	10
valid_sources[0x79]	69891	1			T1	2		T2	1		T5	8
valid_sources[0x7a]	75890	1			T1	8		T5	7		T10	1
valid_sources[0x7b]	71113	1			T1	1		T5	15		T12	11
valid_sources[0x7c]	71143	1			T1	5		T5	10		T10	6
valid_sources[0x7d]	72989	1			T1	3		T5	15		T12	7
valid_sources[0x7e]	68578	1			T1	5		T5	3		T10	1
valid_sources[0x7f]	146162	1			T1	1		T5	17		T10	12
valid_sources[0x80]	75711	1			T1	3		T2	1		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4150211

1

T1

91

T2

83

T4

132

values[0x0]

all_enables

biggest_size

3311571

1

T1

51

T2

50

T3

4

values[0x1]

all_enables

biggest_size

3240492

1

T1

42

T2

23

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	451899	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16472658

1

T5

40

T12

40

T6

1320

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4166056	1			T5	20		T12	20		T6	660
values[0x0]	6184882	1			T5	8		T12	8		T6	344
values[0x1]	6573619	1			T5	12		T12	12		T6	316

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16766384

1

T5

40

T12

40

T6

1320

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	68015	1			T7	1		T22	1		T34	10
valid_sources[0x01]	66176	1			T22	2		T153	1		T154	1
valid_sources[0x02]	66595	1			T22	1		T34	1		T60	1
valid_sources[0x03]	64288	1			T22	1		T34	1		T57	5
valid_sources[0x04]	69299	1			T7	1		T90	1		T60	3
valid_sources[0x05]	67643	1			T22	1		T91	1		T34	7
valid_sources[0x06]	66714	1			T39	3		T21	3		T22	1
valid_sources[0x07]	68802	1			T34	10		T184	2		T80	1
valid_sources[0x08]	66751	1			T34	8		T79	3		T184	3
valid_sources[0x09]	64838	1			T90	1		T91	1		T34	1
valid_sources[0x0a]	69972	1			T90	1		T34	1		T160	2
valid_sources[0x0b]	64687	1			T7	2		T189	1		T34	6
valid_sources[0x0c]	66112	1			T90	1		T34	2		T79	1
valid_sources[0x0d]	63680	1			T7	2		T34	6		T60	2
valid_sources[0x0e]	66298	1			T21	12		T34	2		T60	2
valid_sources[0x0f]	63627	1			T87	1		T22	2		T34	4
valid_sources[0x10]	66042	1			T7	1		T22	1		T186	1
valid_sources[0x11]	63670	1			T5	1		T7	1		T22	1
valid_sources[0x12]	64448	1			T7	1		T80	1		T81	1
valid_sources[0x13]	68873	1			T7	1		T87	2		T22	3
valid_sources[0x14]	66753	1			T7	1		T39	2		T22	5
valid_sources[0x15]	66582	1			T90	1		T34	3		T160	1
valid_sources[0x16]	68490	1			T90	1		T60	1		T154	2
valid_sources[0x17]	67217	1			T7	1		T39	1		T90	2
valid_sources[0x18]	66705	1			T7	2		T34	18		T80	1
valid_sources[0x19]	64350	1			T7	1		T34	9		T108	1
valid_sources[0x1a]	66803	1			T5	2		T34	1		T79	2
valid_sources[0x1b]	66223	1			T7	2		T8	1		T184	4
valid_sources[0x1c]	69584	1			T7	1		T34	10		T60	1
valid_sources[0x1d]	67125	1			T89	2		T91	1		T80	1
valid_sources[0x1e]	66880	1			T88	1		T189	1		T34	9
valid_sources[0x1f]	66354	1			T90	1		T34	6		T79	1
valid_sources[0x20]	66153	1			T7	1		T90	1		T91	1
valid_sources[0x21]	64736	1			T90	2		T34	4		T60	3
valid_sources[0x22]	69066	1			T22	2		T34	9		T60	3
valid_sources[0x23]	67701	1			T22	3		T34	1		T60	3
valid_sources[0x24]	65267	1			T22	2		T90	1		T34	5
valid_sources[0x25]	69295	1			T7	2		T87	1		T34	7
valid_sources[0x26]	65946	1			T7	2		T22	1		T91	1
valid_sources[0x27]	62925	1			T7	3		T88	2		T22	1
valid_sources[0x28]	68448	1			T34	4		T60	1		T57	1
valid_sources[0x29]	64398	1			T7	2		T22	1		T189	1
valid_sources[0x2a]	67320	1			T7	1		T90	1		T34	7
valid_sources[0x2b]	67119	1			T88	1		T34	6		T79	1
valid_sources[0x2c]	66040	1			T22	1		T90	1		T184	2
valid_sources[0x2d]	66296	1			T22	1		T34	6		T57	2
valid_sources[0x2e]	63874	1			T7	1		T60	1		T184	2
valid_sources[0x2f]	64693	1			T87	2		T22	1		T189	1
valid_sources[0x30]	67135	1			T5	3		T7	2		T34	1
valid_sources[0x31]	65164	1			T87	1		T39	2		T22	2
valid_sources[0x32]	62925	1			T7	1		T87	2		T22	1
valid_sources[0x33]	63767	1			T7	3		T39	1		T22	1
valid_sources[0x34]	66676	1			T7	1		T22	1		T60	2
valid_sources[0x35]	67710	1			T7	1		T22	1		T90	1
valid_sources[0x36]	65077	1			T5	1		T22	1		T34	3
valid_sources[0x37]	64900	1			T7	3		T189	2		T90	1
valid_sources[0x38]	63897	1			T21	11		T22	1		T90	1
valid_sources[0x39]	63457	1			T7	1		T22	2		T34	2
valid_sources[0x3a]	66320	1			T5	1		T22	3		T91	1
valid_sources[0x3b]	67991	1			T34	1		T60	2		T184	1
valid_sources[0x3c]	66201	1			T90	1		T34	6		T60	3
valid_sources[0x3d]	63723	1			T22	2		T90	1		T34	7
valid_sources[0x3e]	70028	1			T5	3		T34	12		T81	3
valid_sources[0x3f]	64614	1			T7	1		T90	1		T34	1
valid_sources[0x40]	69459	1			T7	3		T88	1		T34	1
valid_sources[0x41]	65177	1			T34	9		T57	10		T186	1
valid_sources[0x42]	69955	1			T34	9		T60	1		T79	1
valid_sources[0x43]	67680	1			T87	1		T8	4		T91	1
valid_sources[0x44]	64970	1			T34	2		T57	1		T80	1
valid_sources[0x45]	65822	1			T91	2		T34	11		T79	2
valid_sources[0x46]	69834	1			T7	2		T8	2		T184	1
valid_sources[0x47]	65443	1			T7	1		T22	1		T57	1
valid_sources[0x48]	68033	1			T5	1		T7	2		T87	3
valid_sources[0x49]	63757	1			T7	2		T34	9		T57	5
valid_sources[0x4a]	70090	1			T91	1		T34	3		T57	2
valid_sources[0x4b]	67439	1			T87	1		T91	1		T34	4
valid_sources[0x4c]	68142	1			T12	1		T87	2		T57	1
valid_sources[0x4d]	69180	1			T8	5		T34	8		T60	1
valid_sources[0x4e]	65883	1			T91	1		T34	7		T153	2
valid_sources[0x4f]	67567	1			T8	1		T90	1		T34	3
valid_sources[0x50]	66310	1			T34	17		T60	1		T57	12
valid_sources[0x51]	64911	1			T7	1		T87	8		T21	4
valid_sources[0x52]	66937	1			T34	4		T79	3		T184	4
valid_sources[0x53]	65013	1			T7	3		T22	4		T91	2
valid_sources[0x54]	66013	1			T22	1		T90	3		T34	4
valid_sources[0x55]	65845	1			T88	2		T39	2		T34	7
valid_sources[0x56]	64126	1			T7	2		T87	1		T22	1
valid_sources[0x57]	67740	1			T7	2		T34	8		T80	1
valid_sources[0x58]	64678	1			T12	1		T21	2		T60	2
valid_sources[0x59]	64430	1			T7	1		T34	7		T153	1
valid_sources[0x5a]	67246	1			T5	8		T22	1		T189	2
valid_sources[0x5b]	64482	1			T7	1		T34	6		T60	1
valid_sources[0x5c]	63265	1			T5	1		T21	10		T22	2
valid_sources[0x5d]	67611	1			T90	1		T34	3		T60	1
valid_sources[0x5e]	64533	1			T7	2		T87	2		T22	1
valid_sources[0x5f]	67451	1			T7	1		T8	1		T21	4
valid_sources[0x60]	64280	1			T91	1		T34	1		T60	1
valid_sources[0x61]	64625	1			T7	1		T34	5		T60	1
valid_sources[0x62]	64842	1			T39	1		T34	20		T60	3
valid_sources[0x63]	65260	1			T7	1		T22	2		T34	9
valid_sources[0x64]	65809	1			T90	1		T91	3		T34	2
valid_sources[0x65]	65188	1			T87	2		T22	3		T34	2
valid_sources[0x66]	65469	1			T88	1		T90	1		T34	4
valid_sources[0x67]	66073	1			T39	1		T60	1		T79	1
valid_sources[0x68]	64176	1			T7	1		T34	3		T60	1
valid_sources[0x69]	68327	1			T34	5		T57	5		T184	1
valid_sources[0x6a]	64777	1			T39	1		T22	1		T79	2
valid_sources[0x6b]	64112	1			T60	1		T80	3		T81	3
valid_sources[0x6c]	64153	1			T7	1		T34	5		T79	1
valid_sources[0x6d]	63603	1			T7	1		T189	1		T34	3
valid_sources[0x6e]	65492	1			T7	1		T22	1		T34	6
valid_sources[0x6f]	65274	1			T7	2		T8	2		T22	2
valid_sources[0x70]	63910	1			T87	6		T88	1		T39	3
valid_sources[0x71]	67119	1			T5	1		T7	2		T34	9
valid_sources[0x72]	65979	1			T39	1		T90	1		T91	1
valid_sources[0x73]	65872	1			T7	1		T22	1		T34	7
valid_sources[0x74]	67428	1			T39	1		T22	1		T90	1
valid_sources[0x75]	64593	1			T12	3		T91	1		T34	2
valid_sources[0x76]	67104	1			T7	2		T87	2		T189	1
valid_sources[0x77]	65328	1			T7	2		T34	2		T80	1
valid_sources[0x78]	64503	1			T89	4		T34	19		T184	1
valid_sources[0x79]	65229	1			T7	2		T8	2		T34	4
valid_sources[0x7a]	64897	1			T34	4		T60	1		T160	1
valid_sources[0x7b]	66381	1			T87	2		T89	3		T189	2
valid_sources[0x7c]	65894	1			T12	4		T7	2		T21	5
valid_sources[0x7d]	68966	1			T7	2		T22	1		T34	4
valid_sources[0x7e]	66767	1			T7	1		T90	1		T34	5
valid_sources[0x7f]	65300	1			T21	12		T22	1		T34	8
valid_sources[0x80]	67040	1			T7	2		T21	10		T22	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4153134

1

T5

20

T12

20

T6

660

values[0x0]

all_enables

biggest_size

6153830

1

T5

8

T12

8

T6

344

values[0x1]

all_enables

biggest_size

6165694

1

T5

12

T12

12

T6

316