Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42190281

1

T1

776

T2

312

T3

14

full_word

12765726

1

T1

184

T2

156

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	54955717	1			T1	960		T2	468		T3	19
auto[TlIntgErrCmd]	87	1			T244	3		T245	3		T246	3
auto[TlIntgErrData]	115	1			T244	4		T245	5		T246	5
auto[TlIntgErrBoth]	88	1			T244	3		T245	2		T246	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11072286

1

T1

746

T2

289

T3

1

auto[1]

43883721

1

T1

214

T2

179

T3

18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6670595	1			T1	655		T2	206		T3	1
auto[TlIntgErrNone]	partial	auto[1]	35519408	1			T1	121		T2	106		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	4401555	1			T1	91		T2	83		T4	132
auto[TlIntgErrNone]	full_word	auto[1]	8364159	1			T1	93		T2	73		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T245	1		T246	1		T331	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T244	3		T245	2		T246	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T332	1		T333	1		-	-
auto[TlIntgErrData]	partial	auto[0]	59	1			T244	3		T245	3		T246	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T244	1		T245	2		T246	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T252	1		T334	1		T335	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T331	1		T336	1		T337	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T245	1		T246	1		T331	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T244	3		T245	1		T246	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T331	1		T334	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T333	1		-	-		-	-