Module Definition
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Module : otp_ctrl_core_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.otp_ctrl_core_csr_assert 100.00 100.00


Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.86 97.40 96.15 97.12 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1311519950 15018475 0 0
check_regwen_rd_A 1311519950 4334 0 0
check_timeout_rd_A 1311519950 3783 0 0
check_trigger_regwen_rd_A 1311519950 4450 0 0
consistency_check_period_rd_A 1311519950 5003 0 0
creator_sw_cfg_read_lock_rd_A 1311519950 3640 0 0
direct_access_address_rd_A 1311519950 3797 0 0
direct_access_wdata_0_rd_A 1311519950 2876 0 0
direct_access_wdata_1_rd_A 1311519950 3322 0 0
integrity_check_period_rd_A 1311519950 4319 0 0
intr_enable_rd_A 1311519950 5195 0 0
owner_sw_cfg_read_lock_rd_A 1311519950 3464 0 0
rot_creator_auth_codesign_read_lock_rd_A 1311519950 4058 0 0
rot_creator_auth_state_read_lock_rd_A 1311519950 3628 0 0
vendor_test_read_lock_rd_A 1311519950 3665 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 15018475 0 0
T14 328272 534434 0 0
T15 514506 327861 0 0
T16 0 390788 0 0
T20 0 503635 0 0
T33 0 562749 0 0
T42 14521 0 0 0
T86 142990 0 0 0
T103 116386 0 0 0
T123 0 256896 0 0
T128 0 333306 0 0
T134 0 58306 0 0
T177 125800 0 0 0
T203 0 74236 0 0
T214 0 326172 0 0
T253 67640 0 0 0
T254 48648 0 0 0
T255 24852 0 0 0
T256 9337 0 0 0

check_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 4334 0 0
T31 16806 0 0 0
T33 430602 474 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 116 0 0
T262 0 277 0 0
T266 0 60 0 0
T273 0 258 0 0
T285 0 191 0 0
T302 0 249 0 0
T303 0 124 0 0
T304 0 577 0 0
T305 0 333 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

check_timeout_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 3783 0 0
T31 16806 0 0 0
T33 430602 571 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 93 0 0
T262 0 238 0 0
T266 0 82 0 0
T273 0 226 0 0
T285 0 219 0 0
T302 0 329 0 0
T303 0 170 0 0
T304 0 642 0 0
T305 0 316 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

check_trigger_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 4450 0 0
T31 16806 0 0 0
T33 430602 479 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 111 0 0
T262 0 312 0 0
T266 0 69 0 0
T273 0 233 0 0
T285 0 204 0 0
T302 0 290 0 0
T303 0 166 0 0
T304 0 496 0 0
T305 0 305 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

consistency_check_period_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 5003 0 0
T31 16806 0 0 0
T33 430602 719 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 142 0 0
T262 0 303 0 0
T266 0 56 0 0
T273 0 192 0 0
T285 0 252 0 0
T302 0 313 0 0
T303 0 212 0 0
T304 0 615 0 0
T305 0 393 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

creator_sw_cfg_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 3640 0 0
T31 16806 0 0 0
T33 430602 471 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 137 0 0
T262 0 253 0 0
T266 0 94 0 0
T273 0 187 0 0
T285 0 206 0 0
T302 0 239 0 0
T303 0 218 0 0
T304 0 676 0 0
T305 0 270 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

direct_access_address_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 3797 0 0
T31 16806 0 0 0
T33 430602 648 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 122 0 0
T262 0 231 0 0
T266 0 49 0 0
T273 0 244 0 0
T285 0 210 0 0
T302 0 333 0 0
T303 0 214 0 0
T304 0 661 0 0
T305 0 352 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

direct_access_wdata_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 2876 0 0
T31 16806 0 0 0
T33 430602 498 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 94 0 0
T262 0 219 0 0
T266 0 26 0 0
T273 0 173 0 0
T285 0 241 0 0
T302 0 189 0 0
T303 0 190 0 0
T304 0 533 0 0
T305 0 255 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

direct_access_wdata_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 3322 0 0
T31 16806 0 0 0
T33 430602 549 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 122 0 0
T262 0 268 0 0
T266 0 36 0 0
T273 0 150 0 0
T285 0 236 0 0
T302 0 292 0 0
T303 0 176 0 0
T304 0 464 0 0
T305 0 322 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

integrity_check_period_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 4319 0 0
T31 16806 0 0 0
T33 430602 508 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 132 0 0
T262 0 310 0 0
T266 0 78 0 0
T273 0 150 0 0
T285 0 277 0 0
T302 0 275 0 0
T303 0 176 0 0
T304 0 540 0 0
T305 0 256 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 5195 0 0
T33 0 571 0 0
T64 0 11 0 0
T117 157569 8 0 0
T146 64515 0 0 0
T179 16733 0 0 0
T190 30051 0 0 0
T216 94609 0 0 0
T227 0 162 0 0
T229 74850 0 0 0
T262 0 337 0 0
T266 0 49 0 0
T310 0 12 0 0
T311 0 28 0 0
T312 0 15 0 0
T313 0 56 0 0
T314 34534 0 0 0
T315 27153 0 0 0
T316 23387 0 0 0
T317 17369 0 0 0

owner_sw_cfg_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 3464 0 0
T31 16806 0 0 0
T33 430602 600 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 104 0 0
T262 0 286 0 0
T266 0 87 0 0
T273 0 130 0 0
T285 0 211 0 0
T302 0 189 0 0
T303 0 165 0 0
T304 0 542 0 0
T305 0 281 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

rot_creator_auth_codesign_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 4058 0 0
T31 16806 0 0 0
T33 430602 722 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 138 0 0
T262 0 373 0 0
T266 0 68 0 0
T273 0 206 0 0
T285 0 252 0 0
T302 0 229 0 0
T303 0 202 0 0
T304 0 543 0 0
T305 0 330 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

rot_creator_auth_state_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 3628 0 0
T31 16806 0 0 0
T33 430602 458 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 119 0 0
T262 0 297 0 0
T266 0 76 0 0
T273 0 181 0 0
T285 0 251 0 0
T302 0 313 0 0
T303 0 171 0 0
T304 0 492 0 0
T305 0 341 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

vendor_test_read_lock_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1311519950 3665 0 0
T31 16806 0 0 0
T33 430602 560 0 0
T50 16332 0 0 0
T97 55031 0 0 0
T156 13862 0 0 0
T205 9514 0 0 0
T227 0 106 0 0
T262 0 249 0 0
T266 0 79 0 0
T273 0 192 0 0
T285 0 188 0 0
T302 0 291 0 0
T303 0 239 0 0
T304 0 519 0 0
T305 0 337 0 0
T306 17450 0 0 0
T307 69456 0 0 0
T308 58703 0 0 0
T309 17682 0 0 0

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