Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7186805	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6571896

1

T1

255

T2

81061

T3

75184

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8418193	1			T1	1705		T2	69664		T3	33052
values[0x0]	2051416	1			T1	41		T2	29169		T3	29412
values[0x1]	3289092	1			T1	28		T2	50854		T3	51002

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4746321	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9012380

1

T1

733

T2

109443

T3

95379

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49583	1			T1	3		T2	545		T3	463
valid_sources[0x01]	55018	1			T1	28		T2	572		T3	486
valid_sources[0x02]	46852	1			T1	13		T2	597		T3	448
valid_sources[0x03]	52994	1			T1	8		T2	562		T3	441
valid_sources[0x04]	46031	1			T1	9		T2	524		T3	414
valid_sources[0x05]	45539	1			T1	4		T2	552		T3	453
valid_sources[0x06]	53540	1			T1	6		T2	562		T3	438
valid_sources[0x07]	53364	1			T2	586		T3	438		T4	34
valid_sources[0x08]	43515	1			T1	8		T2	506		T3	442
valid_sources[0x09]	56655	1			T1	17		T2	618		T3	450
valid_sources[0x0a]	53324	1			T1	12		T2	635		T3	446
valid_sources[0x0b]	47527	1			T2	589		T3	460		T4	28
valid_sources[0x0c]	60291	1			T1	3		T2	588		T3	407
valid_sources[0x0d]	50410	1			T1	3		T2	563		T3	392
valid_sources[0x0e]	66218	1			T1	14		T2	582		T3	463
valid_sources[0x0f]	59700	1			T1	15		T2	576		T3	457
valid_sources[0x10]	52074	1			T1	10		T2	605		T3	461
valid_sources[0x11]	51973	1			T1	14		T2	559		T3	426
valid_sources[0x12]	47347	1			T1	7		T2	586		T3	438
valid_sources[0x13]	50402	1			T1	3		T2	599		T3	460
valid_sources[0x14]	49721	1			T1	6		T2	605		T3	457
valid_sources[0x15]	52892	1			T1	2		T2	575		T3	465
valid_sources[0x16]	49950	1			T1	1		T2	621		T3	417
valid_sources[0x17]	48029	1			T1	29		T2	591		T3	452
valid_sources[0x18]	48105	1			T2	586		T3	436		T4	29
valid_sources[0x19]	49882	1			T1	11		T2	568		T3	467
valid_sources[0x1a]	50412	1			T1	1		T2	599		T3	438
valid_sources[0x1b]	45461	1			T1	1		T2	554		T3	491
valid_sources[0x1c]	47533	1			T1	4		T2	584		T3	446
valid_sources[0x1d]	53727	1			T1	1		T2	604		T3	508
valid_sources[0x1e]	48136	1			T1	22		T2	568		T3	451
valid_sources[0x1f]	46505	1			T2	554		T3	448		T4	26
valid_sources[0x20]	47454	1			T2	536		T3	456		T4	22
valid_sources[0x21]	54765	1			T1	12		T2	568		T3	440
valid_sources[0x22]	49263	1			T1	1		T2	561		T3	462
valid_sources[0x23]	48904	1			T1	3		T2	587		T3	419
valid_sources[0x24]	48813	1			T2	673		T3	438		T4	31
valid_sources[0x25]	45804	1			T2	571		T3	450		T4	24
valid_sources[0x26]	51490	1			T1	1		T2	564		T3	502
valid_sources[0x27]	48187	1			T2	551		T3	451		T4	27
valid_sources[0x28]	45934	1			T1	10		T2	567		T3	423
valid_sources[0x29]	46094	1			T1	11		T2	586		T3	446
valid_sources[0x2a]	65410	1			T2	580		T3	481		T4	22
valid_sources[0x2b]	51938	1			T1	8		T2	573		T3	453
valid_sources[0x2c]	56441	1			T1	1		T2	602		T3	420
valid_sources[0x2d]	62104	1			T1	4		T2	575		T3	448
valid_sources[0x2e]	70819	1			T1	14		T2	575		T3	445
valid_sources[0x2f]	45859	1			T1	12		T2	576		T3	434
valid_sources[0x30]	47254	1			T2	570		T3	423		T4	31
valid_sources[0x31]	50727	1			T1	8		T2	611		T3	406
valid_sources[0x32]	52085	1			T1	3		T2	575		T3	459
valid_sources[0x33]	46635	1			T1	4		T2	566		T3	455
valid_sources[0x34]	46161	1			T1	10		T2	587		T3	432
valid_sources[0x35]	44987	1			T1	1		T2	555		T3	447
valid_sources[0x36]	48566	1			T1	4		T2	596		T3	419
valid_sources[0x37]	46632	1			T1	11		T2	597		T3	469
valid_sources[0x38]	49170	1			T1	13		T2	559		T3	462
valid_sources[0x39]	47867	1			T1	28		T2	615		T3	405
valid_sources[0x3a]	50744	1			T1	3		T2	580		T3	493
valid_sources[0x3b]	47755	1			T1	9		T2	605		T3	417
valid_sources[0x3c]	56405	1			T1	8		T2	616		T3	395
valid_sources[0x3d]	48056	1			T2	572		T3	430		T4	29
valid_sources[0x3e]	54865	1			T1	13		T2	567		T3	419
valid_sources[0x3f]	46380	1			T1	4		T2	600		T3	457
valid_sources[0x40]	47552	1			T2	563		T3	453		T4	26
valid_sources[0x41]	48067	1			T1	8		T2	572		T3	400
valid_sources[0x42]	47457	1			T2	620		T3	440		T4	36
valid_sources[0x43]	48767	1			T1	1		T2	563		T3	439
valid_sources[0x44]	51162	1			T2	638		T3	460		T4	23
valid_sources[0x45]	47337	1			T1	13		T2	586		T3	440
valid_sources[0x46]	60524	1			T1	6		T2	588		T3	430
valid_sources[0x47]	48279	1			T2	591		T3	472		T4	26
valid_sources[0x48]	50990	1			T2	612		T3	403		T4	19
valid_sources[0x49]	54610	1			T1	22		T2	567		T3	421
valid_sources[0x4a]	45763	1			T2	573		T3	418		T4	22
valid_sources[0x4b]	47532	1			T1	11		T2	543		T3	476
valid_sources[0x4c]	55832	1			T1	3		T2	563		T3	435
valid_sources[0x4d]	54104	1			T2	594		T3	435		T4	34
valid_sources[0x4e]	52699	1			T1	22		T2	629		T3	439
valid_sources[0x4f]	59010	1			T1	1		T2	587		T3	423
valid_sources[0x50]	51537	1			T1	20		T2	586		T3	428
valid_sources[0x51]	49673	1			T1	1		T2	577		T3	429
valid_sources[0x52]	53852	1			T1	2		T2	593		T3	440
valid_sources[0x53]	73678	1			T1	9		T2	569		T3	458
valid_sources[0x54]	47701	1			T1	1		T2	577		T3	424
valid_sources[0x55]	47412	1			T1	16		T2	642		T3	434
valid_sources[0x56]	47548	1			T1	6		T2	579		T3	472
valid_sources[0x57]	50835	1			T1	2		T2	555		T3	459
valid_sources[0x58]	105892	1			T1	1		T2	571		T3	470
valid_sources[0x59]	49103	1			T2	509		T3	449		T4	20
valid_sources[0x5a]	47924	1			T2	543		T3	448		T4	35
valid_sources[0x5b]	51508	1			T2	558		T3	413		T4	23
valid_sources[0x5c]	52232	1			T1	9		T2	599		T3	419
valid_sources[0x5d]	45538	1			T2	576		T3	434		T4	20
valid_sources[0x5e]	47248	1			T1	6		T2	630		T3	422
valid_sources[0x5f]	48642	1			T1	7		T2	560		T3	461
valid_sources[0x60]	46593	1			T1	10		T2	571		T3	447
valid_sources[0x61]	49280	1			T1	1		T2	579		T3	470
valid_sources[0x62]	46441	1			T1	36		T2	616		T3	436
valid_sources[0x63]	50021	1			T1	11		T2	601		T3	459
valid_sources[0x64]	56460	1			T1	1		T2	644		T3	469
valid_sources[0x65]	48372	1			T1	1		T2	583		T3	420
valid_sources[0x66]	46964	1			T1	15		T2	594		T3	445
valid_sources[0x67]	53966	1			T1	6		T2	581		T3	474
valid_sources[0x68]	53795	1			T1	5		T2	625		T3	430
valid_sources[0x69]	50626	1			T1	8		T2	602		T3	495
valid_sources[0x6a]	52222	1			T1	4		T2	565		T3	432
valid_sources[0x6b]	49265	1			T1	29		T2	580		T3	441
valid_sources[0x6c]	44085	1			T1	3		T2	599		T3	450
valid_sources[0x6d]	46973	1			T1	18		T2	516		T3	469
valid_sources[0x6e]	49730	1			T1	9		T2	591		T3	465
valid_sources[0x6f]	58037	1			T1	14		T2	593		T3	453
valid_sources[0x70]	143502	1			T2	569		T3	418		T4	40
valid_sources[0x71]	50169	1			T1	8		T2	564		T3	441
valid_sources[0x72]	46263	1			T1	3		T2	567		T3	436
valid_sources[0x73]	123262	1			T1	5		T2	600		T3	423
valid_sources[0x74]	62893	1			T1	2		T2	542		T3	466
valid_sources[0x75]	47487	1			T2	596		T3	443		T4	26
valid_sources[0x76]	46251	1			T1	24		T2	546		T3	450
valid_sources[0x77]	50587	1			T1	18		T2	569		T3	466
valid_sources[0x78]	46517	1			T1	29		T2	613		T3	426
valid_sources[0x79]	56935	1			T1	11		T2	611		T3	404
valid_sources[0x7a]	48500	1			T2	560		T3	439		T4	28
valid_sources[0x7b]	55819	1			T1	5		T2	560		T3	459
valid_sources[0x7c]	46561	1			T1	10		T2	584		T3	423
valid_sources[0x7d]	54780	1			T2	624		T3	467		T5	6869
valid_sources[0x7e]	47739	1			T2	584		T3	458		T4	31
valid_sources[0x7f]	72598	1			T1	2		T2	619		T3	434
valid_sources[0x80]	45864	1			T2	599		T3	427		T4	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3315100

1

T1

223

T2

30040

T3

21888

values[0x0]

all_enables

biggest_size

1667928

1

T1

23

T2

25692

T3

26713

values[0x1]

all_enables

biggest_size

1588868

1

T1

9

T2

25329

T3

26583

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	218795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7608543

1

T1

20

T2

135155

T3

138321

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1954465	1			T1	10		T2	34403		T3	34717
values[0x0]	2850990	1			T1	7		T2	50708		T3	52339
values[0x1]	3021883	1			T1	3		T2	53680		T3	54707

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	79719	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7747619

1

T1

20

T2

137576

T3

140563

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32107	1			T2	552		T3	587		T5	2
valid_sources[0x01]	29768	1			T2	497		T3	688		T11	180
valid_sources[0x02]	32253	1			T2	530		T3	493		T5	1
valid_sources[0x03]	29381	1			T2	560		T3	381		T11	183
valid_sources[0x04]	32498	1			T2	545		T3	554		T11	201
valid_sources[0x05]	30059	1			T2	562		T3	621		T5	1
valid_sources[0x06]	29774	1			T2	529		T3	378		T5	1
valid_sources[0x07]	28182	1			T2	558		T3	355		T5	2
valid_sources[0x08]	30318	1			T1	1		T2	540		T3	737
valid_sources[0x09]	32781	1			T2	544		T3	668		T7	1
valid_sources[0x0a]	30771	1			T2	514		T3	386		T8	1
valid_sources[0x0b]	36498	1			T1	1		T2	577		T3	527
valid_sources[0x0c]	30235	1			T2	560		T3	525		T12	1300
valid_sources[0x0d]	28044	1			T2	550		T3	467		T11	233
valid_sources[0x0e]	29742	1			T2	569		T3	381		T5	2
valid_sources[0x0f]	28750	1			T2	564		T3	315		T7	1
valid_sources[0x10]	31847	1			T2	571		T3	417		T5	1
valid_sources[0x11]	29073	1			T2	485		T3	494		T7	1
valid_sources[0x12]	32885	1			T2	552		T3	685		T5	1
valid_sources[0x13]	31262	1			T2	564		T3	527		T106	1
valid_sources[0x14]	29482	1			T2	550		T3	431		T106	1
valid_sources[0x15]	30863	1			T2	575		T3	327		T5	1
valid_sources[0x16]	30231	1			T2	573		T3	723		T106	3
valid_sources[0x17]	33409	1			T1	1		T2	588		T3	609
valid_sources[0x18]	30338	1			T2	574		T3	531		T106	2
valid_sources[0x19]	29734	1			T2	523		T3	640		T11	210
valid_sources[0x1a]	28849	1			T2	526		T3	621		T106	2
valid_sources[0x1b]	30570	1			T2	554		T3	686		T11	190
valid_sources[0x1c]	30130	1			T2	518		T3	526		T5	1
valid_sources[0x1d]	29208	1			T2	526		T3	509		T11	174
valid_sources[0x1e]	30533	1			T2	534		T3	596		T5	1
valid_sources[0x1f]	31763	1			T1	1		T2	563		T3	381
valid_sources[0x20]	31317	1			T2	561		T3	342		T7	1
valid_sources[0x21]	29290	1			T2	557		T3	744		T5	2
valid_sources[0x22]	29729	1			T2	556		T3	628		T106	1
valid_sources[0x23]	31400	1			T2	545		T3	489		T5	2
valid_sources[0x24]	28942	1			T2	572		T3	476		T106	4
valid_sources[0x25]	29393	1			T2	542		T3	508		T106	1
valid_sources[0x26]	33551	1			T2	546		T3	451		T5	1
valid_sources[0x27]	28871	1			T2	531		T3	409		T106	1
valid_sources[0x28]	30872	1			T2	556		T3	516		T5	1
valid_sources[0x29]	29795	1			T2	537		T3	396		T11	206
valid_sources[0x2a]	29331	1			T2	555		T3	619		T7	1
valid_sources[0x2b]	30194	1			T2	523		T3	658		T106	1
valid_sources[0x2c]	29733	1			T2	515		T3	620		T11	179
valid_sources[0x2d]	29844	1			T2	548		T3	509		T11	183
valid_sources[0x2e]	28126	1			T2	566		T3	485		T5	2
valid_sources[0x2f]	30492	1			T2	559		T3	333		T7	1
valid_sources[0x30]	29361	1			T2	533		T3	759		T11	192
valid_sources[0x31]	31207	1			T2	531		T3	377		T106	1
valid_sources[0x32]	31773	1			T2	533		T3	429		T106	1
valid_sources[0x33]	29868	1			T2	567		T3	491		T5	1
valid_sources[0x34]	30385	1			T2	560		T3	481		T5	1
valid_sources[0x35]	30232	1			T2	562		T3	727		T5	2
valid_sources[0x36]	32066	1			T2	553		T3	502		T5	1
valid_sources[0x37]	29431	1			T2	570		T3	670		T7	3
valid_sources[0x38]	30674	1			T2	559		T3	376		T7	2
valid_sources[0x39]	30559	1			T2	549		T3	507		T11	187
valid_sources[0x3a]	28271	1			T2	561		T3	453		T8	2
valid_sources[0x3b]	31936	1			T2	549		T3	486		T6	1
valid_sources[0x3c]	29460	1			T2	557		T3	413		T106	1
valid_sources[0x3d]	29211	1			T2	521		T3	350		T106	1
valid_sources[0x3e]	29718	1			T2	558		T3	520		T5	1
valid_sources[0x3f]	29999	1			T2	489		T3	825		T7	2
valid_sources[0x40]	30238	1			T2	546		T3	691		T106	1
valid_sources[0x41]	32647	1			T2	529		T3	558		T106	1
valid_sources[0x42]	30684	1			T2	554		T3	970		T5	1
valid_sources[0x43]	28233	1			T2	533		T3	282		T5	2
valid_sources[0x44]	30459	1			T2	543		T3	472		T11	185
valid_sources[0x45]	30278	1			T2	539		T3	799		T5	1
valid_sources[0x46]	31022	1			T2	528		T3	836		T11	187
valid_sources[0x47]	29813	1			T2	549		T3	500		T11	182
valid_sources[0x48]	31174	1			T2	538		T3	392		T5	1
valid_sources[0x49]	28058	1			T2	531		T3	691		T11	187
valid_sources[0x4a]	32289	1			T2	532		T3	435		T7	1
valid_sources[0x4b]	33761	1			T2	547		T3	785		T7	2
valid_sources[0x4c]	30747	1			T2	553		T3	748		T5	1
valid_sources[0x4d]	29322	1			T2	545		T3	703		T11	196
valid_sources[0x4e]	32940	1			T2	556		T3	763		T5	1
valid_sources[0x4f]	30028	1			T2	567		T3	818		T11	190
valid_sources[0x50]	28036	1			T2	580		T3	232		T5	2
valid_sources[0x51]	31288	1			T2	498		T3	356		T11	203
valid_sources[0x52]	29694	1			T2	531		T3	430		T5	1
valid_sources[0x53]	30698	1			T2	544		T3	308		T7	3
valid_sources[0x54]	30014	1			T2	556		T3	442		T5	2
valid_sources[0x55]	27909	1			T2	516		T3	408		T5	1
valid_sources[0x56]	30211	1			T2	541		T3	552		T11	193
valid_sources[0x57]	30631	1			T2	554		T3	370		T5	2
valid_sources[0x58]	29358	1			T2	551		T3	430		T11	181
valid_sources[0x59]	28648	1			T2	556		T3	552		T5	1
valid_sources[0x5a]	30797	1			T2	543		T3	288		T11	200
valid_sources[0x5b]	32475	1			T2	547		T3	834		T5	2
valid_sources[0x5c]	31376	1			T2	548		T3	537		T5	2
valid_sources[0x5d]	29976	1			T1	1		T2	523		T3	353
valid_sources[0x5e]	29403	1			T2	517		T3	518		T5	1
valid_sources[0x5f]	29978	1			T2	550		T3	728		T7	1
valid_sources[0x60]	29061	1			T2	589		T3	618		T106	1
valid_sources[0x61]	32200	1			T2	544		T3	679		T106	2
valid_sources[0x62]	31737	1			T2	539		T3	366		T106	1
valid_sources[0x63]	32842	1			T2	537		T3	513		T5	3
valid_sources[0x64]	32800	1			T1	1		T2	541		T3	342
valid_sources[0x65]	35671	1			T2	543		T3	702		T7	1
valid_sources[0x66]	31678	1			T2	529		T3	504		T11	219
valid_sources[0x67]	29405	1			T1	1		T2	545		T3	592
valid_sources[0x68]	33762	1			T2	511		T3	677		T106	1
valid_sources[0x69]	32117	1			T2	545		T3	531		T7	1
valid_sources[0x6a]	30884	1			T2	582		T3	578		T7	1
valid_sources[0x6b]	28628	1			T2	490		T3	366		T7	2
valid_sources[0x6c]	29886	1			T2	577		T3	331		T5	1
valid_sources[0x6d]	32998	1			T2	534		T3	414		T106	1
valid_sources[0x6e]	30115	1			T2	501		T3	671		T106	1
valid_sources[0x6f]	31283	1			T1	1		T2	523		T3	791
valid_sources[0x70]	32903	1			T2	511		T3	372		T5	1
valid_sources[0x71]	33306	1			T2	528		T3	553		T11	192
valid_sources[0x72]	30566	1			T2	556		T3	479		T106	2
valid_sources[0x73]	31356	1			T2	530		T3	546		T8	1
valid_sources[0x74]	31300	1			T2	543		T3	686		T11	177
valid_sources[0x75]	30890	1			T2	521		T3	402		T7	1
valid_sources[0x76]	34054	1			T2	553		T3	541		T11	191
valid_sources[0x77]	28967	1			T2	553		T3	693		T5	1
valid_sources[0x78]	28999	1			T1	1		T2	544		T3	483
valid_sources[0x79]	28766	1			T2	558		T3	369		T5	1
valid_sources[0x7a]	28593	1			T2	534		T3	410		T5	1
valid_sources[0x7b]	27931	1			T2	535		T3	717		T106	2
valid_sources[0x7c]	29853	1			T2	531		T3	486		T7	1
valid_sources[0x7d]	33636	1			T2	587		T3	429		T106	4
valid_sources[0x7e]	31349	1			T2	509		T3	373		T106	1
valid_sources[0x7f]	31925	1			T2	529		T3	692		T11	181
valid_sources[0x80]	31309	1			T2	534		T3	488		T106	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1940383

1

T1

10

T2

34358

T3

34703

values[0x0]

all_enables

biggest_size

2836074

1

T1

7

T2

50480

T3

52078

values[0x1]

all_enables

biggest_size

2832086

1

T1

3

T2

50317

T3

51540