Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22605092

1

T1

1519

T2

338701

T3

312150

full_word

7507279

1

T1

255

T2

97580

T3

92145

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30112061	1			T1	1774		T2	436281		T3	404295
auto[TlIntgErrCmd]	103	1			T260	1		T261	4		T262	3
auto[TlIntgErrData]	101	1			T260	3		T261	7		T262	3
auto[TlIntgErrBoth]	106	1			T260	6		T261	9		T262	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9542199

1

T1

1705

T2

89668

T3

53621

auto[1]

20570172

1

T1

69

T2

346613

T3

350674

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6113219	1			T1	1482		T2	57615		T3	29587
auto[TlIntgErrNone]	partial	auto[1]	16491598	1			T1	37		T2	281086		T3	282563
auto[TlIntgErrNone]	full_word	auto[0]	3428832	1			T1	223		T2	32053		T3	24034
auto[TlIntgErrNone]	full_word	auto[1]	4078412	1			T1	32		T2	65527		T3	68111
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T261	2		T262	1		T346	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T260	1		T261	2		T346	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T262	1		T346	1		T347	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T262	1		T347	1		T352	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T260	3		T261	5		T346	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T261	1		T262	2		T346	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T261	1		T262	1		T347	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T353	1		T354	1		T355	3
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T260	4		T261	3		T262	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T260	2		T261	6		T262	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T351	1		T267	1		T354	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T352	1		-	-		-	-