Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	96.75	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	406971416	6807802	0	0
check_regwen_rd_A	406971416	3636	0	0
check_timeout_rd_A	406971416	3586	0	0
check_trigger_regwen_rd_A	406971416	3512	0	0
consistency_check_period_rd_A	406971416	3956	0	0
creator_sw_cfg_read_lock_rd_A	406971416	3581	0	0
direct_access_address_rd_A	406971416	3088	0	0
direct_access_wdata_0_rd_A	406971416	1973	0	0
direct_access_wdata_1_rd_A	406971416	2267	0	0
integrity_check_period_rd_A	406971416	3844	0	0
intr_enable_rd_A	406971416	4587	0	0
owner_sw_cfg_read_lock_rd_A	406971416	3048	0	0
rot_creator_auth_codesign_read_lock_rd_A	406971416	3553	0	0
rot_creator_auth_state_read_lock_rd_A	406971416	3413	0	0
vendor_test_read_lock_rd_A	406971416	3105	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	6807802	0	0
T2	380768	118319	0	0
T3	639258	123689	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	42930	0	0
T13	0	43927	0	0
T14	0	19901	0	0
T31	0	26414	0	0
T32	0	126758	0	0
T42	0	15525	0	0
T70	0	213256	0	0
T106	67146	0	0	0
T164	0	95060	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3636	0	0
T3	639258	146	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	33	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	49	0	0
T164	0	115	0	0
T333	0	130	0	0
T334	0	70	0	0
T335	0	124	0	0
T336	0	79	0	0
T337	0	24	0	0
T338	0	206	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3586	0	0
T3	639258	90	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	25	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	38	0	0
T164	0	88	0	0
T333	0	140	0	0
T334	0	77	0	0
T335	0	171	0	0
T336	0	57	0	0
T337	0	26	0	0
T338	0	213	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3512	0	0
T3	639258	99	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	12	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	80	0	0
T164	0	140	0	0
T333	0	90	0	0
T334	0	93	0	0
T335	0	137	0	0
T336	0	60	0	0
T337	0	56	0	0
T338	0	163	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3956	0	0
T3	639258	147	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	10	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	79	0	0
T164	0	101	0	0
T333	0	140	0	0
T334	0	75	0	0
T335	0	147	0	0
T336	0	46	0	0
T337	0	35	0	0
T338	0	183	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3581	0	0
T3	639258	104	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	33	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	107	0	0
T164	0	134	0	0
T333	0	170	0	0
T334	0	69	0	0
T335	0	143	0	0
T336	0	59	0	0
T337	0	49	0	0
T338	0	140	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3088	0	0
T3	639258	108	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	28	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	69	0	0
T164	0	83	0	0
T333	0	144	0	0
T334	0	77	0	0
T335	0	189	0	0
T336	0	56	0	0
T337	0	33	0	0
T338	0	143	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	1973	0	0
T3	639258	156	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	8	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	36	0	0
T164	0	115	0	0
T333	0	53	0	0
T334	0	28	0	0
T335	0	107	0	0
T336	0	22	0	0
T337	0	27	0	0
T338	0	154	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	2267	0	0
T3	639258	99	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	18	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	70	0	0
T164	0	116	0	0
T333	0	61	0	0
T334	0	57	0	0
T335	0	125	0	0
T336	0	47	0	0
T337	0	33	0	0
T338	0	141	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3844	0	0
T3	639258	137	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	35	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	60	0	0
T164	0	91	0	0
T333	0	143	0	0
T334	0	54	0	0
T335	0	148	0	0
T336	0	77	0	0
T337	0	55	0	0
T338	0	175	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	4587	0	0
T3	639258	104	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	21	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T140	0	6	0	0
T142	0	61	0	0
T164	0	119	0	0
T228	0	35	0	0
T333	0	122	0	0
T334	0	101	0	0
T335	0	153	0	0
T336	0	59	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3048	0	0
T3	639258	115	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	31	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	52	0	0
T164	0	99	0	0
T333	0	102	0	0
T334	0	82	0	0
T335	0	86	0	0
T336	0	52	0	0
T337	0	46	0	0
T338	0	158	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3553	0	0
T3	639258	120	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	34	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	87	0	0
T164	0	76	0	0
T333	0	194	0	0
T334	0	55	0	0
T335	0	159	0	0
T336	0	81	0	0
T337	0	26	0	0
T338	0	185	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3413	0	0
T3	639258	196	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	33	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	67	0	0
T164	0	92	0	0
T333	0	84	0	0
T334	0	126	0	0
T335	0	168	0	0
T336	0	62	0	0
T337	0	25	0	0
T338	0	214	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406971416	3105	0	0
T3	639258	109	0	0
T4	57927	0	0	0
T5	23059	0	0	0
T6	19989	0	0	0
T7	207438	0	0	0
T8	34677	0	0	0
T9	9893	0	0	0
T10	14807	0	0	0
T11	0	15	0	0
T12	585954	0	0	0
T106	67146	0	0	0
T142	0	65	0	0
T164	0	68	0	0
T333	0	109	0	0
T334	0	79	0	0
T335	0	154	0	0
T336	0	45	0	0
T337	0	39	0	0
T338	0	133	0	0